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STM32F407_RCC
0.1
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Macros | |
| #define | ADC_SR_AWD 0x00000001U |
| #define | ADC_SR_EOC 0x00000002U |
| #define | ADC_SR_JEOC 0x00000004U |
| #define | ADC_SR_JSTRT 0x00000008U |
| #define | ADC_SR_STRT 0x00000010U |
| #define | ADC_SR_OVR 0x00000020U |
| #define | ADC_CR1_AWDCH 0x0000001FU |
| #define | ADC_CR1_AWDCH_0 0x00000001U |
| #define | ADC_CR1_AWDCH_1 0x00000002U |
| #define | ADC_CR1_AWDCH_2 0x00000004U |
| #define | ADC_CR1_AWDCH_3 0x00000008U |
| #define | ADC_CR1_AWDCH_4 0x00000010U |
| #define | ADC_CR1_EOCIE 0x00000020U |
| #define | ADC_CR1_AWDIE 0x00000040U |
| #define | ADC_CR1_JEOCIE 0x00000080U |
| #define | ADC_CR1_SCAN 0x00000100U |
| #define | ADC_CR1_AWDSGL 0x00000200U |
| #define | ADC_CR1_JAUTO 0x00000400U |
| #define | ADC_CR1_DISCEN 0x00000800U |
| #define | ADC_CR1_JDISCEN 0x00001000U |
| #define | ADC_CR1_DISCNUM 0x0000E000U |
| #define | ADC_CR1_DISCNUM_0 0x00002000U |
| #define | ADC_CR1_DISCNUM_1 0x00004000U |
| #define | ADC_CR1_DISCNUM_2 0x00008000U |
| #define | ADC_CR1_JAWDEN 0x00400000U |
| #define | ADC_CR1_AWDEN 0x00800000U |
| #define | ADC_CR1_RES 0x03000000U |
| #define | ADC_CR1_RES_0 0x01000000U |
| #define | ADC_CR1_RES_1 0x02000000U |
| #define | ADC_CR1_OVRIE 0x04000000U |
| #define | ADC_CR2_ADON 0x00000001U |
| #define | ADC_CR2_CONT 0x00000002U |
| #define | ADC_CR2_DMA 0x00000100U |
| #define | ADC_CR2_DDS 0x00000200U |
| #define | ADC_CR2_EOCS 0x00000400U |
| #define | ADC_CR2_ALIGN 0x00000800U |
| #define | ADC_CR2_JEXTSEL 0x000F0000U |
| #define | ADC_CR2_JEXTSEL_0 0x00010000U |
| #define | ADC_CR2_JEXTSEL_1 0x00020000U |
| #define | ADC_CR2_JEXTSEL_2 0x00040000U |
| #define | ADC_CR2_JEXTSEL_3 0x00080000U |
| #define | ADC_CR2_JEXTEN 0x00300000U |
| #define | ADC_CR2_JEXTEN_0 0x00100000U |
| #define | ADC_CR2_JEXTEN_1 0x00200000U |
| #define | ADC_CR2_JSWSTART 0x00400000U |
| #define | ADC_CR2_EXTSEL 0x0F000000U |
| #define | ADC_CR2_EXTSEL_0 0x01000000U |
| #define | ADC_CR2_EXTSEL_1 0x02000000U |
| #define | ADC_CR2_EXTSEL_2 0x04000000U |
| #define | ADC_CR2_EXTSEL_3 0x08000000U |
| #define | ADC_CR2_EXTEN 0x30000000U |
| #define | ADC_CR2_EXTEN_0 0x10000000U |
| #define | ADC_CR2_EXTEN_1 0x20000000U |
| #define | ADC_CR2_SWSTART 0x40000000U |
| #define | ADC_SMPR1_SMP10 0x00000007U |
| #define | ADC_SMPR1_SMP10_0 0x00000001U |
| #define | ADC_SMPR1_SMP10_1 0x00000002U |
| #define | ADC_SMPR1_SMP10_2 0x00000004U |
| #define | ADC_SMPR1_SMP11 0x00000038U |
| #define | ADC_SMPR1_SMP11_0 0x00000008U |
| #define | ADC_SMPR1_SMP11_1 0x00000010U |
| #define | ADC_SMPR1_SMP11_2 0x00000020U |
| #define | ADC_SMPR1_SMP12 0x000001C0U |
| #define | ADC_SMPR1_SMP12_0 0x00000040U |
| #define | ADC_SMPR1_SMP12_1 0x00000080U |
| #define | ADC_SMPR1_SMP12_2 0x00000100U |
| #define | ADC_SMPR1_SMP13 0x00000E00U |
| #define | ADC_SMPR1_SMP13_0 0x00000200U |
| #define | ADC_SMPR1_SMP13_1 0x00000400U |
| #define | ADC_SMPR1_SMP13_2 0x00000800U |
| #define | ADC_SMPR1_SMP14 0x00007000U |
| #define | ADC_SMPR1_SMP14_0 0x00001000U |
| #define | ADC_SMPR1_SMP14_1 0x00002000U |
| #define | ADC_SMPR1_SMP14_2 0x00004000U |
| #define | ADC_SMPR1_SMP15 0x00038000U |
| #define | ADC_SMPR1_SMP15_0 0x00008000U |
| #define | ADC_SMPR1_SMP15_1 0x00010000U |
| #define | ADC_SMPR1_SMP15_2 0x00020000U |
| #define | ADC_SMPR1_SMP16 0x001C0000U |
| #define | ADC_SMPR1_SMP16_0 0x00040000U |
| #define | ADC_SMPR1_SMP16_1 0x00080000U |
| #define | ADC_SMPR1_SMP16_2 0x00100000U |
| #define | ADC_SMPR1_SMP17 0x00E00000U |
| #define | ADC_SMPR1_SMP17_0 0x00200000U |
| #define | ADC_SMPR1_SMP17_1 0x00400000U |
| #define | ADC_SMPR1_SMP17_2 0x00800000U |
| #define | ADC_SMPR1_SMP18 0x07000000U |
| #define | ADC_SMPR1_SMP18_0 0x01000000U |
| #define | ADC_SMPR1_SMP18_1 0x02000000U |
| #define | ADC_SMPR1_SMP18_2 0x04000000U |
| #define | ADC_SMPR2_SMP0 0x00000007U |
| #define | ADC_SMPR2_SMP0_0 0x00000001U |
| #define | ADC_SMPR2_SMP0_1 0x00000002U |
| #define | ADC_SMPR2_SMP0_2 0x00000004U |
| #define | ADC_SMPR2_SMP1 0x00000038U |
| #define | ADC_SMPR2_SMP1_0 0x00000008U |
| #define | ADC_SMPR2_SMP1_1 0x00000010U |
| #define | ADC_SMPR2_SMP1_2 0x00000020U |
| #define | ADC_SMPR2_SMP2 0x000001C0U |
| #define | ADC_SMPR2_SMP2_0 0x00000040U |
| #define | ADC_SMPR2_SMP2_1 0x00000080U |
| #define | ADC_SMPR2_SMP2_2 0x00000100U |
| #define | ADC_SMPR2_SMP3 0x00000E00U |
| #define | ADC_SMPR2_SMP3_0 0x00000200U |
| #define | ADC_SMPR2_SMP3_1 0x00000400U |
| #define | ADC_SMPR2_SMP3_2 0x00000800U |
| #define | ADC_SMPR2_SMP4 0x00007000U |
| #define | ADC_SMPR2_SMP4_0 0x00001000U |
| #define | ADC_SMPR2_SMP4_1 0x00002000U |
| #define | ADC_SMPR2_SMP4_2 0x00004000U |
| #define | ADC_SMPR2_SMP5 0x00038000U |
| #define | ADC_SMPR2_SMP5_0 0x00008000U |
| #define | ADC_SMPR2_SMP5_1 0x00010000U |
| #define | ADC_SMPR2_SMP5_2 0x00020000U |
| #define | ADC_SMPR2_SMP6 0x001C0000U |
| #define | ADC_SMPR2_SMP6_0 0x00040000U |
| #define | ADC_SMPR2_SMP6_1 0x00080000U |
| #define | ADC_SMPR2_SMP6_2 0x00100000U |
| #define | ADC_SMPR2_SMP7 0x00E00000U |
| #define | ADC_SMPR2_SMP7_0 0x00200000U |
| #define | ADC_SMPR2_SMP7_1 0x00400000U |
| #define | ADC_SMPR2_SMP7_2 0x00800000U |
| #define | ADC_SMPR2_SMP8 0x07000000U |
| #define | ADC_SMPR2_SMP8_0 0x01000000U |
| #define | ADC_SMPR2_SMP8_1 0x02000000U |
| #define | ADC_SMPR2_SMP8_2 0x04000000U |
| #define | ADC_SMPR2_SMP9 0x38000000U |
| #define | ADC_SMPR2_SMP9_0 0x08000000U |
| #define | ADC_SMPR2_SMP9_1 0x10000000U |
| #define | ADC_SMPR2_SMP9_2 0x20000000U |
| #define | ADC_JOFR1_JOFFSET1 0x0FFFU |
| #define | ADC_JOFR2_JOFFSET2 0x0FFFU |
| #define | ADC_JOFR3_JOFFSET3 0x0FFFU |
| #define | ADC_JOFR4_JOFFSET4 0x0FFFU |
| #define | ADC_HTR_HT 0x0FFFU |
| #define | ADC_LTR_LT 0x0FFFU |
| #define | ADC_SQR1_SQ13 0x0000001FU |
| #define | ADC_SQR1_SQ13_0 0x00000001U |
| #define | ADC_SQR1_SQ13_1 0x00000002U |
| #define | ADC_SQR1_SQ13_2 0x00000004U |
| #define | ADC_SQR1_SQ13_3 0x00000008U |
| #define | ADC_SQR1_SQ13_4 0x00000010U |
| #define | ADC_SQR1_SQ14 0x000003E0U |
| #define | ADC_SQR1_SQ14_0 0x00000020U |
| #define | ADC_SQR1_SQ14_1 0x00000040U |
| #define | ADC_SQR1_SQ14_2 0x00000080U |
| #define | ADC_SQR1_SQ14_3 0x00000100U |
| #define | ADC_SQR1_SQ14_4 0x00000200U |
| #define | ADC_SQR1_SQ15 0x00007C00U |
| #define | ADC_SQR1_SQ15_0 0x00000400U |
| #define | ADC_SQR1_SQ15_1 0x00000800U |
| #define | ADC_SQR1_SQ15_2 0x00001000U |
| #define | ADC_SQR1_SQ15_3 0x00002000U |
| #define | ADC_SQR1_SQ15_4 0x00004000U |
| #define | ADC_SQR1_SQ16 0x000F8000U |
| #define | ADC_SQR1_SQ16_0 0x00008000U |
| #define | ADC_SQR1_SQ16_1 0x00010000U |
| #define | ADC_SQR1_SQ16_2 0x00020000U |
| #define | ADC_SQR1_SQ16_3 0x00040000U |
| #define | ADC_SQR1_SQ16_4 0x00080000U |
| #define | ADC_SQR1_L 0x00F00000U |
| #define | ADC_SQR1_L_0 0x00100000U |
| #define | ADC_SQR1_L_1 0x00200000U |
| #define | ADC_SQR1_L_2 0x00400000U |
| #define | ADC_SQR1_L_3 0x00800000U |
| #define | ADC_SQR2_SQ7 0x0000001FU |
| #define | ADC_SQR2_SQ7_0 0x00000001U |
| #define | ADC_SQR2_SQ7_1 0x00000002U |
| #define | ADC_SQR2_SQ7_2 0x00000004U |
| #define | ADC_SQR2_SQ7_3 0x00000008U |
| #define | ADC_SQR2_SQ7_4 0x00000010U |
| #define | ADC_SQR2_SQ8 0x000003E0U |
| #define | ADC_SQR2_SQ8_0 0x00000020U |
| #define | ADC_SQR2_SQ8_1 0x00000040U |
| #define | ADC_SQR2_SQ8_2 0x00000080U |
| #define | ADC_SQR2_SQ8_3 0x00000100U |
| #define | ADC_SQR2_SQ8_4 0x00000200U |
| #define | ADC_SQR2_SQ9 0x00007C00U |
| #define | ADC_SQR2_SQ9_0 0x00000400U |
| #define | ADC_SQR2_SQ9_1 0x00000800U |
| #define | ADC_SQR2_SQ9_2 0x00001000U |
| #define | ADC_SQR2_SQ9_3 0x00002000U |
| #define | ADC_SQR2_SQ9_4 0x00004000U |
| #define | ADC_SQR2_SQ10 0x000F8000U |
| #define | ADC_SQR2_SQ10_0 0x00008000U |
| #define | ADC_SQR2_SQ10_1 0x00010000U |
| #define | ADC_SQR2_SQ10_2 0x00020000U |
| #define | ADC_SQR2_SQ10_3 0x00040000U |
| #define | ADC_SQR2_SQ10_4 0x00080000U |
| #define | ADC_SQR2_SQ11 0x01F00000U |
| #define | ADC_SQR2_SQ11_0 0x00100000U |
| #define | ADC_SQR2_SQ11_1 0x00200000U |
| #define | ADC_SQR2_SQ11_2 0x00400000U |
| #define | ADC_SQR2_SQ11_3 0x00800000U |
| #define | ADC_SQR2_SQ11_4 0x01000000U |
| #define | ADC_SQR2_SQ12 0x3E000000U |
| #define | ADC_SQR2_SQ12_0 0x02000000U |
| #define | ADC_SQR2_SQ12_1 0x04000000U |
| #define | ADC_SQR2_SQ12_2 0x08000000U |
| #define | ADC_SQR2_SQ12_3 0x10000000U |
| #define | ADC_SQR2_SQ12_4 0x20000000U |
| #define | ADC_SQR3_SQ1 0x0000001FU |
| #define | ADC_SQR3_SQ1_0 0x00000001U |
| #define | ADC_SQR3_SQ1_1 0x00000002U |
| #define | ADC_SQR3_SQ1_2 0x00000004U |
| #define | ADC_SQR3_SQ1_3 0x00000008U |
| #define | ADC_SQR3_SQ1_4 0x00000010U |
| #define | ADC_SQR3_SQ2 0x000003E0U |
| #define | ADC_SQR3_SQ2_0 0x00000020U |
| #define | ADC_SQR3_SQ2_1 0x00000040U |
| #define | ADC_SQR3_SQ2_2 0x00000080U |
| #define | ADC_SQR3_SQ2_3 0x00000100U |
| #define | ADC_SQR3_SQ2_4 0x00000200U |
| #define | ADC_SQR3_SQ3 0x00007C00U |
| #define | ADC_SQR3_SQ3_0 0x00000400U |
| #define | ADC_SQR3_SQ3_1 0x00000800U |
| #define | ADC_SQR3_SQ3_2 0x00001000U |
| #define | ADC_SQR3_SQ3_3 0x00002000U |
| #define | ADC_SQR3_SQ3_4 0x00004000U |
| #define | ADC_SQR3_SQ4 0x000F8000U |
| #define | ADC_SQR3_SQ4_0 0x00008000U |
| #define | ADC_SQR3_SQ4_1 0x00010000U |
| #define | ADC_SQR3_SQ4_2 0x00020000U |
| #define | ADC_SQR3_SQ4_3 0x00040000U |
| #define | ADC_SQR3_SQ4_4 0x00080000U |
| #define | ADC_SQR3_SQ5 0x01F00000U |
| #define | ADC_SQR3_SQ5_0 0x00100000U |
| #define | ADC_SQR3_SQ5_1 0x00200000U |
| #define | ADC_SQR3_SQ5_2 0x00400000U |
| #define | ADC_SQR3_SQ5_3 0x00800000U |
| #define | ADC_SQR3_SQ5_4 0x01000000U |
| #define | ADC_SQR3_SQ6 0x3E000000U |
| #define | ADC_SQR3_SQ6_0 0x02000000U |
| #define | ADC_SQR3_SQ6_1 0x04000000U |
| #define | ADC_SQR3_SQ6_2 0x08000000U |
| #define | ADC_SQR3_SQ6_3 0x10000000U |
| #define | ADC_SQR3_SQ6_4 0x20000000U |
| #define | ADC_JSQR_JSQ1 0x0000001FU |
| #define | ADC_JSQR_JSQ1_0 0x00000001U |
| #define | ADC_JSQR_JSQ1_1 0x00000002U |
| #define | ADC_JSQR_JSQ1_2 0x00000004U |
| #define | ADC_JSQR_JSQ1_3 0x00000008U |
| #define | ADC_JSQR_JSQ1_4 0x00000010U |
| #define | ADC_JSQR_JSQ2 0x000003E0U |
| #define | ADC_JSQR_JSQ2_0 0x00000020U |
| #define | ADC_JSQR_JSQ2_1 0x00000040U |
| #define | ADC_JSQR_JSQ2_2 0x00000080U |
| #define | ADC_JSQR_JSQ2_3 0x00000100U |
| #define | ADC_JSQR_JSQ2_4 0x00000200U |
| #define | ADC_JSQR_JSQ3 0x00007C00U |
| #define | ADC_JSQR_JSQ3_0 0x00000400U |
| #define | ADC_JSQR_JSQ3_1 0x00000800U |
| #define | ADC_JSQR_JSQ3_2 0x00001000U |
| #define | ADC_JSQR_JSQ3_3 0x00002000U |
| #define | ADC_JSQR_JSQ3_4 0x00004000U |
| #define | ADC_JSQR_JSQ4 0x000F8000U |
| #define | ADC_JSQR_JSQ4_0 0x00008000U |
| #define | ADC_JSQR_JSQ4_1 0x00010000U |
| #define | ADC_JSQR_JSQ4_2 0x00020000U |
| #define | ADC_JSQR_JSQ4_3 0x00040000U |
| #define | ADC_JSQR_JSQ4_4 0x00080000U |
| #define | ADC_JSQR_JL 0x00300000U |
| #define | ADC_JSQR_JL_0 0x00100000U |
| #define | ADC_JSQR_JL_1 0x00200000U |
| #define | ADC_JDR1_JDATA 0xFFFFU |
| #define | ADC_JDR2_JDATA 0xFFFFU |
| #define | ADC_JDR3_JDATA 0xFFFFU |
| #define | ADC_JDR4_JDATA 0xFFFFU |
| #define | ADC_DR_DATA 0x0000FFFFU |
| #define | ADC_DR_ADC2DATA 0xFFFF0000U |
| #define | ADC_CSR_AWD1 0x00000001U |
| #define | ADC_CSR_EOC1 0x00000002U |
| #define | ADC_CSR_JEOC1 0x00000004U |
| #define | ADC_CSR_JSTRT1 0x00000008U |
| #define | ADC_CSR_STRT1 0x00000010U |
| #define | ADC_CSR_OVR1 0x00000020U |
| #define | ADC_CSR_AWD2 0x00000100U |
| #define | ADC_CSR_EOC2 0x00000200U |
| #define | ADC_CSR_JEOC2 0x00000400U |
| #define | ADC_CSR_JSTRT2 0x00000800U |
| #define | ADC_CSR_STRT2 0x00001000U |
| #define | ADC_CSR_OVR2 0x00002000U |
| #define | ADC_CSR_AWD3 0x00010000U |
| #define | ADC_CSR_EOC3 0x00020000U |
| #define | ADC_CSR_JEOC3 0x00040000U |
| #define | ADC_CSR_JSTRT3 0x00080000U |
| #define | ADC_CSR_STRT3 0x00100000U |
| #define | ADC_CSR_OVR3 0x00200000U |
| #define | ADC_CSR_DOVR1 ADC_CSR_OVR1 |
| #define | ADC_CSR_DOVR2 ADC_CSR_OVR2 |
| #define | ADC_CSR_DOVR3 ADC_CSR_OVR3 |
| #define | ADC_CCR_MULTI 0x0000001FU |
| #define | ADC_CCR_MULTI_0 0x00000001U |
| #define | ADC_CCR_MULTI_1 0x00000002U |
| #define | ADC_CCR_MULTI_2 0x00000004U |
| #define | ADC_CCR_MULTI_3 0x00000008U |
| #define | ADC_CCR_MULTI_4 0x00000010U |
| #define | ADC_CCR_DELAY 0x00000F00U |
| #define | ADC_CCR_DELAY_0 0x00000100U |
| #define | ADC_CCR_DELAY_1 0x00000200U |
| #define | ADC_CCR_DELAY_2 0x00000400U |
| #define | ADC_CCR_DELAY_3 0x00000800U |
| #define | ADC_CCR_DDS 0x00002000U |
| #define | ADC_CCR_DMA 0x0000C000U |
| #define | ADC_CCR_DMA_0 0x00004000U |
| #define | ADC_CCR_DMA_1 0x00008000U |
| #define | ADC_CCR_ADCPRE 0x00030000U |
| #define | ADC_CCR_ADCPRE_0 0x00010000U |
| #define | ADC_CCR_ADCPRE_1 0x00020000U |
| #define | ADC_CCR_VBATE 0x00400000U |
| #define | ADC_CCR_TSVREFE 0x00800000U |
| #define | ADC_CDR_DATA1 0x0000FFFFU |
| #define | ADC_CDR_DATA2 0xFFFF0000U |
| #define | CAN_MCR_INRQ 0x00000001U |
| #define | CAN_MCR_SLEEP 0x00000002U |
| #define | CAN_MCR_TXFP 0x00000004U |
| #define | CAN_MCR_RFLM 0x00000008U |
| #define | CAN_MCR_NART 0x00000010U |
| #define | CAN_MCR_AWUM 0x00000020U |
| #define | CAN_MCR_ABOM 0x00000040U |
| #define | CAN_MCR_TTCM 0x00000080U |
| #define | CAN_MCR_RESET 0x00008000U |
| #define | CAN_MCR_DBF 0x00010000U |
| #define | CAN_MSR_INAK 0x0001U |
| #define | CAN_MSR_SLAK 0x0002U |
| #define | CAN_MSR_ERRI 0x0004U |
| #define | CAN_MSR_WKUI 0x0008U |
| #define | CAN_MSR_SLAKI 0x0010U |
| #define | CAN_MSR_TXM 0x0100U |
| #define | CAN_MSR_RXM 0x0200U |
| #define | CAN_MSR_SAMP 0x0400U |
| #define | CAN_MSR_RX 0x0800U |
| #define | CAN_TSR_RQCP0 0x00000001U |
| #define | CAN_TSR_TXOK0 0x00000002U |
| #define | CAN_TSR_ALST0 0x00000004U |
| #define | CAN_TSR_TERR0 0x00000008U |
| #define | CAN_TSR_ABRQ0 0x00000080U |
| #define | CAN_TSR_RQCP1 0x00000100U |
| #define | CAN_TSR_TXOK1 0x00000200U |
| #define | CAN_TSR_ALST1 0x00000400U |
| #define | CAN_TSR_TERR1 0x00000800U |
| #define | CAN_TSR_ABRQ1 0x00008000U |
| #define | CAN_TSR_RQCP2 0x00010000U |
| #define | CAN_TSR_TXOK2 0x00020000U |
| #define | CAN_TSR_ALST2 0x00040000U |
| #define | CAN_TSR_TERR2 0x00080000U |
| #define | CAN_TSR_ABRQ2 0x00800000U |
| #define | CAN_TSR_CODE 0x03000000U |
| #define | CAN_TSR_TME 0x1C000000U |
| #define | CAN_TSR_TME0 0x04000000U |
| #define | CAN_TSR_TME1 0x08000000U |
| #define | CAN_TSR_TME2 0x10000000U |
| #define | CAN_TSR_LOW 0xE0000000U |
| #define | CAN_TSR_LOW0 0x20000000U |
| #define | CAN_TSR_LOW1 0x40000000U |
| #define | CAN_TSR_LOW2 0x80000000U |
| #define | CAN_RF0R_FMP0 0x03U |
| #define | CAN_RF0R_FULL0 0x08U |
| #define | CAN_RF0R_FOVR0 0x10U |
| #define | CAN_RF0R_RFOM0 0x20U |
| #define | CAN_RF1R_FMP1 0x03U |
| #define | CAN_RF1R_FULL1 0x08U |
| #define | CAN_RF1R_FOVR1 0x10U |
| #define | CAN_RF1R_RFOM1 0x20U |
| #define | CAN_IER_TMEIE 0x00000001U |
| #define | CAN_IER_FMPIE0 0x00000002U |
| #define | CAN_IER_FFIE0 0x00000004U |
| #define | CAN_IER_FOVIE0 0x00000008U |
| #define | CAN_IER_FMPIE1 0x00000010U |
| #define | CAN_IER_FFIE1 0x00000020U |
| #define | CAN_IER_FOVIE1 0x00000040U |
| #define | CAN_IER_EWGIE 0x00000100U |
| #define | CAN_IER_EWGIE 0x00000100U |
| #define | CAN_IER_EPVIE 0x00000200U |
| #define | CAN_IER_EPVIE 0x00000200U |
| #define | CAN_IER_BOFIE 0x00000400U |
| #define | CAN_IER_BOFIE 0x00000400U |
| #define | CAN_IER_LECIE 0x00000800U |
| #define | CAN_IER_LECIE 0x00000800U |
| #define | CAN_IER_ERRIE 0x00008000U |
| #define | CAN_IER_ERRIE 0x00008000U |
| #define | CAN_IER_WKUIE 0x00010000U |
| #define | CAN_IER_SLKIE 0x00020000U |
| #define | CAN_ESR_EWGF 0x00000001U |
| #define | CAN_ESR_EPVF 0x00000002U |
| #define | CAN_ESR_BOFF 0x00000004U |
| #define | CAN_ESR_LEC 0x00000070U |
| #define | CAN_ESR_LEC_0 0x00000010U |
| #define | CAN_ESR_LEC_1 0x00000020U |
| #define | CAN_ESR_LEC_2 0x00000040U |
| #define | CAN_ESR_TEC 0x00FF0000U |
| #define | CAN_ESR_REC 0xFF000000U |
| #define | CAN_BTR_BRP 0x000003FFU |
| #define | CAN_BTR_TS1 0x000F0000U |
| #define | CAN_BTR_TS1_0 0x00010000U |
| #define | CAN_BTR_TS1_1 0x00020000U |
| #define | CAN_BTR_TS1_2 0x00040000U |
| #define | CAN_BTR_TS1_3 0x00080000U |
| #define | CAN_BTR_TS2 0x00700000U |
| #define | CAN_BTR_TS2_0 0x00100000U |
| #define | CAN_BTR_TS2_1 0x00200000U |
| #define | CAN_BTR_TS2_2 0x00400000U |
| #define | CAN_BTR_SJW 0x03000000U |
| #define | CAN_BTR_SJW_0 0x01000000U |
| #define | CAN_BTR_SJW_1 0x02000000U |
| #define | CAN_BTR_LBKM 0x40000000U |
| #define | CAN_BTR_SILM 0x80000000U |
| #define | CAN_TI0R_TXRQ 0x00000001U |
| #define | CAN_TI0R_RTR 0x00000002U |
| #define | CAN_TI0R_IDE 0x00000004U |
| #define | CAN_TI0R_EXID 0x001FFFF8U |
| #define | CAN_TI0R_STID 0xFFE00000U |
| #define | CAN_TDT0R_DLC 0x0000000FU |
| #define | CAN_TDT0R_TGT 0x00000100U |
| #define | CAN_TDT0R_TIME 0xFFFF0000U |
| #define | CAN_TDL0R_DATA0 0x000000FFU |
| #define | CAN_TDL0R_DATA1 0x0000FF00U |
| #define | CAN_TDL0R_DATA2 0x00FF0000U |
| #define | CAN_TDL0R_DATA3 0xFF000000U |
| #define | CAN_TDH0R_DATA4 0x000000FFU |
| #define | CAN_TDH0R_DATA5 0x0000FF00U |
| #define | CAN_TDH0R_DATA6 0x00FF0000U |
| #define | CAN_TDH0R_DATA7 0xFF000000U |
| #define | CAN_TI1R_TXRQ 0x00000001U |
| #define | CAN_TI1R_RTR 0x00000002U |
| #define | CAN_TI1R_IDE 0x00000004U |
| #define | CAN_TI1R_EXID 0x001FFFF8U |
| #define | CAN_TI1R_STID 0xFFE00000U |
| #define | CAN_TDT1R_DLC 0x0000000FU |
| #define | CAN_TDT1R_TGT 0x00000100U |
| #define | CAN_TDT1R_TIME 0xFFFF0000U |
| #define | CAN_TDL1R_DATA0 0x000000FFU |
| #define | CAN_TDL1R_DATA1 0x0000FF00U |
| #define | CAN_TDL1R_DATA2 0x00FF0000U |
| #define | CAN_TDL1R_DATA3 0xFF000000U |
| #define | CAN_TDH1R_DATA4 0x000000FFU |
| #define | CAN_TDH1R_DATA5 0x0000FF00U |
| #define | CAN_TDH1R_DATA6 0x00FF0000U |
| #define | CAN_TDH1R_DATA7 0xFF000000U |
| #define | CAN_TI2R_TXRQ 0x00000001U |
| #define | CAN_TI2R_RTR 0x00000002U |
| #define | CAN_TI2R_IDE 0x00000004U |
| #define | CAN_TI2R_EXID 0x001FFFF8U |
| #define | CAN_TI2R_STID 0xFFE00000U |
| #define | CAN_TDT2R_DLC 0x0000000FU |
| #define | CAN_TDT2R_TGT 0x00000100U |
| #define | CAN_TDT2R_TIME 0xFFFF0000U |
| #define | CAN_TDL2R_DATA0 0x000000FFU |
| #define | CAN_TDL2R_DATA1 0x0000FF00U |
| #define | CAN_TDL2R_DATA2 0x00FF0000U |
| #define | CAN_TDL2R_DATA3 0xFF000000U |
| #define | CAN_TDH2R_DATA4 0x000000FFU |
| #define | CAN_TDH2R_DATA5 0x0000FF00U |
| #define | CAN_TDH2R_DATA6 0x00FF0000U |
| #define | CAN_TDH2R_DATA7 0xFF000000U |
| #define | CAN_RI0R_RTR 0x00000002U |
| #define | CAN_RI0R_IDE 0x00000004U |
| #define | CAN_RI0R_EXID 0x001FFFF8U |
| #define | CAN_RI0R_STID 0xFFE00000U |
| #define | CAN_RDT0R_DLC 0x0000000FU |
| #define | CAN_RDT0R_FMI 0x0000FF00U |
| #define | CAN_RDT0R_TIME 0xFFFF0000U |
| #define | CAN_RDL0R_DATA0 0x000000FFU |
| #define | CAN_RDL0R_DATA1 0x0000FF00U |
| #define | CAN_RDL0R_DATA2 0x00FF0000U |
| #define | CAN_RDL0R_DATA3 0xFF000000U |
| #define | CAN_RDH0R_DATA4 0x000000FFU |
| #define | CAN_RDH0R_DATA5 0x0000FF00U |
| #define | CAN_RDH0R_DATA6 0x00FF0000U |
| #define | CAN_RDH0R_DATA7 0xFF000000U |
| #define | CAN_RI1R_RTR 0x00000002U |
| #define | CAN_RI1R_IDE 0x00000004U |
| #define | CAN_RI1R_EXID 0x001FFFF8U |
| #define | CAN_RI1R_STID 0xFFE00000U |
| #define | CAN_RDT1R_DLC 0x0000000FU |
| #define | CAN_RDT1R_FMI 0x0000FF00U |
| #define | CAN_RDT1R_TIME 0xFFFF0000U |
| #define | CAN_RDL1R_DATA0 0x000000FFU |
| #define | CAN_RDL1R_DATA1 0x0000FF00U |
| #define | CAN_RDL1R_DATA2 0x00FF0000U |
| #define | CAN_RDL1R_DATA3 0xFF000000U |
| #define | CAN_RDH1R_DATA4 0x000000FFU |
| #define | CAN_RDH1R_DATA5 0x0000FF00U |
| #define | CAN_RDH1R_DATA6 0x00FF0000U |
| #define | CAN_RDH1R_DATA7 0xFF000000U |
| #define | CAN_FMR_FINIT 0x01U |
| #define | CAN_FMR_CAN2SB 0x00003F00U |
| #define | CAN_FM1R_FBM 0x0FFFFFFFU |
| #define | CAN_FM1R_FBM0 0x00000001U |
| #define | CAN_FM1R_FBM1 0x00000002U |
| #define | CAN_FM1R_FBM2 0x00000004U |
| #define | CAN_FM1R_FBM3 0x00000008U |
| #define | CAN_FM1R_FBM4 0x00000010U |
| #define | CAN_FM1R_FBM5 0x00000020U |
| #define | CAN_FM1R_FBM6 0x00000040U |
| #define | CAN_FM1R_FBM7 0x00000080U |
| #define | CAN_FM1R_FBM8 0x00000100U |
| #define | CAN_FM1R_FBM9 0x00000200U |
| #define | CAN_FM1R_FBM10 0x00000400U |
| #define | CAN_FM1R_FBM11 0x00000800U |
| #define | CAN_FM1R_FBM12 0x00001000U |
| #define | CAN_FM1R_FBM13 0x00002000U |
| #define | CAN_FM1R_FBM14 0x00004000U |
| #define | CAN_FM1R_FBM15 0x00008000U |
| #define | CAN_FM1R_FBM16 0x00010000U |
| #define | CAN_FM1R_FBM17 0x00020000U |
| #define | CAN_FM1R_FBM18 0x00040000U |
| #define | CAN_FM1R_FBM19 0x00080000U |
| #define | CAN_FM1R_FBM20 0x00100000U |
| #define | CAN_FM1R_FBM21 0x00200000U |
| #define | CAN_FM1R_FBM22 0x00400000U |
| #define | CAN_FM1R_FBM23 0x00800000U |
| #define | CAN_FM1R_FBM24 0x01000000U |
| #define | CAN_FM1R_FBM25 0x02000000U |
| #define | CAN_FM1R_FBM26 0x04000000U |
| #define | CAN_FM1R_FBM27 0x08000000U |
| #define | CAN_FS1R_FSC 0x0FFFFFFFU |
| #define | CAN_FS1R_FSC0 0x00000001U |
| #define | CAN_FS1R_FSC1 0x00000002U |
| #define | CAN_FS1R_FSC2 0x00000004U |
| #define | CAN_FS1R_FSC3 0x00000008U |
| #define | CAN_FS1R_FSC4 0x00000010U |
| #define | CAN_FS1R_FSC5 0x00000020U |
| #define | CAN_FS1R_FSC6 0x00000040U |
| #define | CAN_FS1R_FSC7 0x00000080U |
| #define | CAN_FS1R_FSC8 0x00000100U |
| #define | CAN_FS1R_FSC9 0x00000200U |
| #define | CAN_FS1R_FSC10 0x00000400U |
| #define | CAN_FS1R_FSC11 0x00000800U |
| #define | CAN_FS1R_FSC12 0x00001000U |
| #define | CAN_FS1R_FSC13 0x00002000U |
| #define | CAN_FS1R_FSC14 0x00004000U |
| #define | CAN_FS1R_FSC15 0x00008000U |
| #define | CAN_FS1R_FSC16 0x00010000U |
| #define | CAN_FS1R_FSC17 0x00020000U |
| #define | CAN_FS1R_FSC18 0x00040000U |
| #define | CAN_FS1R_FSC19 0x00080000U |
| #define | CAN_FS1R_FSC20 0x00100000U |
| #define | CAN_FS1R_FSC21 0x00200000U |
| #define | CAN_FS1R_FSC22 0x00400000U |
| #define | CAN_FS1R_FSC23 0x00800000U |
| #define | CAN_FS1R_FSC24 0x01000000U |
| #define | CAN_FS1R_FSC25 0x02000000U |
| #define | CAN_FS1R_FSC26 0x04000000U |
| #define | CAN_FS1R_FSC27 0x08000000U |
| #define | CAN_FFA1R_FFA 0x0FFFFFFFU |
| #define | CAN_FFA1R_FFA0 0x00000001U |
| #define | CAN_FFA1R_FFA1 0x00000002U |
| #define | CAN_FFA1R_FFA2 0x00000004U |
| #define | CAN_FFA1R_FFA3 0x00000008U |
| #define | CAN_FFA1R_FFA4 0x00000010U |
| #define | CAN_FFA1R_FFA5 0x00000020U |
| #define | CAN_FFA1R_FFA6 0x00000040U |
| #define | CAN_FFA1R_FFA7 0x00000080U |
| #define | CAN_FFA1R_FFA8 0x00000100U |
| #define | CAN_FFA1R_FFA9 0x00000200U |
| #define | CAN_FFA1R_FFA10 0x00000400U |
| #define | CAN_FFA1R_FFA11 0x00000800U |
| #define | CAN_FFA1R_FFA12 0x00001000U |
| #define | CAN_FFA1R_FFA13 0x00002000U |
| #define | CAN_FFA1R_FFA14 0x00004000U |
| #define | CAN_FFA1R_FFA15 0x00008000U |
| #define | CAN_FFA1R_FFA16 0x00010000U |
| #define | CAN_FFA1R_FFA17 0x00020000U |
| #define | CAN_FFA1R_FFA18 0x00040000U |
| #define | CAN_FFA1R_FFA19 0x00080000U |
| #define | CAN_FFA1R_FFA20 0x00100000U |
| #define | CAN_FFA1R_FFA21 0x00200000U |
| #define | CAN_FFA1R_FFA22 0x00400000U |
| #define | CAN_FFA1R_FFA23 0x00800000U |
| #define | CAN_FFA1R_FFA24 0x01000000U |
| #define | CAN_FFA1R_FFA25 0x02000000U |
| #define | CAN_FFA1R_FFA26 0x04000000U |
| #define | CAN_FFA1R_FFA27 0x08000000U |
| #define | CAN_FA1R_FACT 0x0FFFFFFFU |
| #define | CAN_FA1R_FACT0 0x00000001U |
| #define | CAN_FA1R_FACT1 0x00000002U |
| #define | CAN_FA1R_FACT2 0x00000004U |
| #define | CAN_FA1R_FACT3 0x00000008U |
| #define | CAN_FA1R_FACT4 0x00000010U |
| #define | CAN_FA1R_FACT5 0x00000020U |
| #define | CAN_FA1R_FACT6 0x00000040U |
| #define | CAN_FA1R_FACT7 0x00000080U |
| #define | CAN_FA1R_FACT8 0x00000100U |
| #define | CAN_FA1R_FACT9 0x00000200U |
| #define | CAN_FA1R_FACT10 0x00000400U |
| #define | CAN_FA1R_FACT11 0x00000800U |
| #define | CAN_FA1R_FACT12 0x00001000U |
| #define | CAN_FA1R_FACT13 0x00002000U |
| #define | CAN_FA1R_FACT14 0x00004000U |
| #define | CAN_FA1R_FACT15 0x00008000U |
| #define | CAN_FA1R_FACT16 0x00010000U |
| #define | CAN_FA1R_FACT17 0x00020000U |
| #define | CAN_FA1R_FACT18 0x00040000U |
| #define | CAN_FA1R_FACT19 0x00080000U |
| #define | CAN_FA1R_FACT20 0x00100000U |
| #define | CAN_FA1R_FACT21 0x00200000U |
| #define | CAN_FA1R_FACT22 0x00400000U |
| #define | CAN_FA1R_FACT23 0x00800000U |
| #define | CAN_FA1R_FACT24 0x01000000U |
| #define | CAN_FA1R_FACT25 0x02000000U |
| #define | CAN_FA1R_FACT26 0x04000000U |
| #define | CAN_FA1R_FACT27 0x08000000U |
| #define | CAN_F0R1_FB0 0x00000001U |
| #define | CAN_F0R1_FB1 0x00000002U |
| #define | CAN_F0R1_FB2 0x00000004U |
| #define | CAN_F0R1_FB3 0x00000008U |
| #define | CAN_F0R1_FB4 0x00000010U |
| #define | CAN_F0R1_FB5 0x00000020U |
| #define | CAN_F0R1_FB6 0x00000040U |
| #define | CAN_F0R1_FB7 0x00000080U |
| #define | CAN_F0R1_FB8 0x00000100U |
| #define | CAN_F0R1_FB9 0x00000200U |
| #define | CAN_F0R1_FB10 0x00000400U |
| #define | CAN_F0R1_FB11 0x00000800U |
| #define | CAN_F0R1_FB12 0x00001000U |
| #define | CAN_F0R1_FB13 0x00002000U |
| #define | CAN_F0R1_FB14 0x00004000U |
| #define | CAN_F0R1_FB15 0x00008000U |
| #define | CAN_F0R1_FB16 0x00010000U |
| #define | CAN_F0R1_FB17 0x00020000U |
| #define | CAN_F0R1_FB18 0x00040000U |
| #define | CAN_F0R1_FB19 0x00080000U |
| #define | CAN_F0R1_FB20 0x00100000U |
| #define | CAN_F0R1_FB21 0x00200000U |
| #define | CAN_F0R1_FB22 0x00400000U |
| #define | CAN_F0R1_FB23 0x00800000U |
| #define | CAN_F0R1_FB24 0x01000000U |
| #define | CAN_F0R1_FB25 0x02000000U |
| #define | CAN_F0R1_FB26 0x04000000U |
| #define | CAN_F0R1_FB27 0x08000000U |
| #define | CAN_F0R1_FB28 0x10000000U |
| #define | CAN_F0R1_FB29 0x20000000U |
| #define | CAN_F0R1_FB30 0x40000000U |
| #define | CAN_F0R1_FB31 0x80000000U |
| #define | CAN_F1R1_FB0 0x00000001U |
| #define | CAN_F1R1_FB1 0x00000002U |
| #define | CAN_F1R1_FB2 0x00000004U |
| #define | CAN_F1R1_FB3 0x00000008U |
| #define | CAN_F1R1_FB4 0x00000010U |
| #define | CAN_F1R1_FB5 0x00000020U |
| #define | CAN_F1R1_FB6 0x00000040U |
| #define | CAN_F1R1_FB7 0x00000080U |
| #define | CAN_F1R1_FB8 0x00000100U |
| #define | CAN_F1R1_FB9 0x00000200U |
| #define | CAN_F1R1_FB10 0x00000400U |
| #define | CAN_F1R1_FB11 0x00000800U |
| #define | CAN_F1R1_FB12 0x00001000U |
| #define | CAN_F1R1_FB13 0x00002000U |
| #define | CAN_F1R1_FB14 0x00004000U |
| #define | CAN_F1R1_FB15 0x00008000U |
| #define | CAN_F1R1_FB16 0x00010000U |
| #define | CAN_F1R1_FB17 0x00020000U |
| #define | CAN_F1R1_FB18 0x00040000U |
| #define | CAN_F1R1_FB19 0x00080000U |
| #define | CAN_F1R1_FB20 0x00100000U |
| #define | CAN_F1R1_FB21 0x00200000U |
| #define | CAN_F1R1_FB22 0x00400000U |
| #define | CAN_F1R1_FB23 0x00800000U |
| #define | CAN_F1R1_FB24 0x01000000U |
| #define | CAN_F1R1_FB25 0x02000000U |
| #define | CAN_F1R1_FB26 0x04000000U |
| #define | CAN_F1R1_FB27 0x08000000U |
| #define | CAN_F1R1_FB28 0x10000000U |
| #define | CAN_F1R1_FB29 0x20000000U |
| #define | CAN_F1R1_FB30 0x40000000U |
| #define | CAN_F1R1_FB31 0x80000000U |
| #define | CAN_F2R1_FB0 0x00000001U |
| #define | CAN_F2R1_FB1 0x00000002U |
| #define | CAN_F2R1_FB2 0x00000004U |
| #define | CAN_F2R1_FB3 0x00000008U |
| #define | CAN_F2R1_FB4 0x00000010U |
| #define | CAN_F2R1_FB5 0x00000020U |
| #define | CAN_F2R1_FB6 0x00000040U |
| #define | CAN_F2R1_FB7 0x00000080U |
| #define | CAN_F2R1_FB8 0x00000100U |
| #define | CAN_F2R1_FB9 0x00000200U |
| #define | CAN_F2R1_FB10 0x00000400U |
| #define | CAN_F2R1_FB11 0x00000800U |
| #define | CAN_F2R1_FB12 0x00001000U |
| #define | CAN_F2R1_FB13 0x00002000U |
| #define | CAN_F2R1_FB14 0x00004000U |
| #define | CAN_F2R1_FB15 0x00008000U |
| #define | CAN_F2R1_FB16 0x00010000U |
| #define | CAN_F2R1_FB17 0x00020000U |
| #define | CAN_F2R1_FB18 0x00040000U |
| #define | CAN_F2R1_FB19 0x00080000U |
| #define | CAN_F2R1_FB20 0x00100000U |
| #define | CAN_F2R1_FB21 0x00200000U |
| #define | CAN_F2R1_FB22 0x00400000U |
| #define | CAN_F2R1_FB23 0x00800000U |
| #define | CAN_F2R1_FB24 0x01000000U |
| #define | CAN_F2R1_FB25 0x02000000U |
| #define | CAN_F2R1_FB26 0x04000000U |
| #define | CAN_F2R1_FB27 0x08000000U |
| #define | CAN_F2R1_FB28 0x10000000U |
| #define | CAN_F2R1_FB29 0x20000000U |
| #define | CAN_F2R1_FB30 0x40000000U |
| #define | CAN_F2R1_FB31 0x80000000U |
| #define | CAN_F3R1_FB0 0x00000001U |
| #define | CAN_F3R1_FB1 0x00000002U |
| #define | CAN_F3R1_FB2 0x00000004U |
| #define | CAN_F3R1_FB3 0x00000008U |
| #define | CAN_F3R1_FB4 0x00000010U |
| #define | CAN_F3R1_FB5 0x00000020U |
| #define | CAN_F3R1_FB6 0x00000040U |
| #define | CAN_F3R1_FB7 0x00000080U |
| #define | CAN_F3R1_FB8 0x00000100U |
| #define | CAN_F3R1_FB9 0x00000200U |
| #define | CAN_F3R1_FB10 0x00000400U |
| #define | CAN_F3R1_FB11 0x00000800U |
| #define | CAN_F3R1_FB12 0x00001000U |
| #define | CAN_F3R1_FB13 0x00002000U |
| #define | CAN_F3R1_FB14 0x00004000U |
| #define | CAN_F3R1_FB15 0x00008000U |
| #define | CAN_F3R1_FB16 0x00010000U |
| #define | CAN_F3R1_FB17 0x00020000U |
| #define | CAN_F3R1_FB18 0x00040000U |
| #define | CAN_F3R1_FB19 0x00080000U |
| #define | CAN_F3R1_FB20 0x00100000U |
| #define | CAN_F3R1_FB21 0x00200000U |
| #define | CAN_F3R1_FB22 0x00400000U |
| #define | CAN_F3R1_FB23 0x00800000U |
| #define | CAN_F3R1_FB24 0x01000000U |
| #define | CAN_F3R1_FB25 0x02000000U |
| #define | CAN_F3R1_FB26 0x04000000U |
| #define | CAN_F3R1_FB27 0x08000000U |
| #define | CAN_F3R1_FB28 0x10000000U |
| #define | CAN_F3R1_FB29 0x20000000U |
| #define | CAN_F3R1_FB30 0x40000000U |
| #define | CAN_F3R1_FB31 0x80000000U |
| #define | CAN_F4R1_FB0 0x00000001U |
| #define | CAN_F4R1_FB1 0x00000002U |
| #define | CAN_F4R1_FB2 0x00000004U |
| #define | CAN_F4R1_FB3 0x00000008U |
| #define | CAN_F4R1_FB4 0x00000010U |
| #define | CAN_F4R1_FB5 0x00000020U |
| #define | CAN_F4R1_FB6 0x00000040U |
| #define | CAN_F4R1_FB7 0x00000080U |
| #define | CAN_F4R1_FB8 0x00000100U |
| #define | CAN_F4R1_FB9 0x00000200U |
| #define | CAN_F4R1_FB10 0x00000400U |
| #define | CAN_F4R1_FB11 0x00000800U |
| #define | CAN_F4R1_FB12 0x00001000U |
| #define | CAN_F4R1_FB13 0x00002000U |
| #define | CAN_F4R1_FB14 0x00004000U |
| #define | CAN_F4R1_FB15 0x00008000U |
| #define | CAN_F4R1_FB16 0x00010000U |
| #define | CAN_F4R1_FB17 0x00020000U |
| #define | CAN_F4R1_FB18 0x00040000U |
| #define | CAN_F4R1_FB19 0x00080000U |
| #define | CAN_F4R1_FB20 0x00100000U |
| #define | CAN_F4R1_FB21 0x00200000U |
| #define | CAN_F4R1_FB22 0x00400000U |
| #define | CAN_F4R1_FB23 0x00800000U |
| #define | CAN_F4R1_FB24 0x01000000U |
| #define | CAN_F4R1_FB25 0x02000000U |
| #define | CAN_F4R1_FB26 0x04000000U |
| #define | CAN_F4R1_FB27 0x08000000U |
| #define | CAN_F4R1_FB28 0x10000000U |
| #define | CAN_F4R1_FB29 0x20000000U |
| #define | CAN_F4R1_FB30 0x40000000U |
| #define | CAN_F4R1_FB31 0x80000000U |
| #define | CAN_F5R1_FB0 0x00000001U |
| #define | CAN_F5R1_FB1 0x00000002U |
| #define | CAN_F5R1_FB2 0x00000004U |
| #define | CAN_F5R1_FB3 0x00000008U |
| #define | CAN_F5R1_FB4 0x00000010U |
| #define | CAN_F5R1_FB5 0x00000020U |
| #define | CAN_F5R1_FB6 0x00000040U |
| #define | CAN_F5R1_FB7 0x00000080U |
| #define | CAN_F5R1_FB8 0x00000100U |
| #define | CAN_F5R1_FB9 0x00000200U |
| #define | CAN_F5R1_FB10 0x00000400U |
| #define | CAN_F5R1_FB11 0x00000800U |
| #define | CAN_F5R1_FB12 0x00001000U |
| #define | CAN_F5R1_FB13 0x00002000U |
| #define | CAN_F5R1_FB14 0x00004000U |
| #define | CAN_F5R1_FB15 0x00008000U |
| #define | CAN_F5R1_FB16 0x00010000U |
| #define | CAN_F5R1_FB17 0x00020000U |
| #define | CAN_F5R1_FB18 0x00040000U |
| #define | CAN_F5R1_FB19 0x00080000U |
| #define | CAN_F5R1_FB20 0x00100000U |
| #define | CAN_F5R1_FB21 0x00200000U |
| #define | CAN_F5R1_FB22 0x00400000U |
| #define | CAN_F5R1_FB23 0x00800000U |
| #define | CAN_F5R1_FB24 0x01000000U |
| #define | CAN_F5R1_FB25 0x02000000U |
| #define | CAN_F5R1_FB26 0x04000000U |
| #define | CAN_F5R1_FB27 0x08000000U |
| #define | CAN_F5R1_FB28 0x10000000U |
| #define | CAN_F5R1_FB29 0x20000000U |
| #define | CAN_F5R1_FB30 0x40000000U |
| #define | CAN_F5R1_FB31 0x80000000U |
| #define | CAN_F6R1_FB0 0x00000001U |
| #define | CAN_F6R1_FB1 0x00000002U |
| #define | CAN_F6R1_FB2 0x00000004U |
| #define | CAN_F6R1_FB3 0x00000008U |
| #define | CAN_F6R1_FB4 0x00000010U |
| #define | CAN_F6R1_FB5 0x00000020U |
| #define | CAN_F6R1_FB6 0x00000040U |
| #define | CAN_F6R1_FB7 0x00000080U |
| #define | CAN_F6R1_FB8 0x00000100U |
| #define | CAN_F6R1_FB9 0x00000200U |
| #define | CAN_F6R1_FB10 0x00000400U |
| #define | CAN_F6R1_FB11 0x00000800U |
| #define | CAN_F6R1_FB12 0x00001000U |
| #define | CAN_F6R1_FB13 0x00002000U |
| #define | CAN_F6R1_FB14 0x00004000U |
| #define | CAN_F6R1_FB15 0x00008000U |
| #define | CAN_F6R1_FB16 0x00010000U |
| #define | CAN_F6R1_FB17 0x00020000U |
| #define | CAN_F6R1_FB18 0x00040000U |
| #define | CAN_F6R1_FB19 0x00080000U |
| #define | CAN_F6R1_FB20 0x00100000U |
| #define | CAN_F6R1_FB21 0x00200000U |
| #define | CAN_F6R1_FB22 0x00400000U |
| #define | CAN_F6R1_FB23 0x00800000U |
| #define | CAN_F6R1_FB24 0x01000000U |
| #define | CAN_F6R1_FB25 0x02000000U |
| #define | CAN_F6R1_FB26 0x04000000U |
| #define | CAN_F6R1_FB27 0x08000000U |
| #define | CAN_F6R1_FB28 0x10000000U |
| #define | CAN_F6R1_FB29 0x20000000U |
| #define | CAN_F6R1_FB30 0x40000000U |
| #define | CAN_F6R1_FB31 0x80000000U |
| #define | CAN_F7R1_FB0 0x00000001U |
| #define | CAN_F7R1_FB1 0x00000002U |
| #define | CAN_F7R1_FB2 0x00000004U |
| #define | CAN_F7R1_FB3 0x00000008U |
| #define | CAN_F7R1_FB4 0x00000010U |
| #define | CAN_F7R1_FB5 0x00000020U |
| #define | CAN_F7R1_FB6 0x00000040U |
| #define | CAN_F7R1_FB7 0x00000080U |
| #define | CAN_F7R1_FB8 0x00000100U |
| #define | CAN_F7R1_FB9 0x00000200U |
| #define | CAN_F7R1_FB10 0x00000400U |
| #define | CAN_F7R1_FB11 0x00000800U |
| #define | CAN_F7R1_FB12 0x00001000U |
| #define | CAN_F7R1_FB13 0x00002000U |
| #define | CAN_F7R1_FB14 0x00004000U |
| #define | CAN_F7R1_FB15 0x00008000U |
| #define | CAN_F7R1_FB16 0x00010000U |
| #define | CAN_F7R1_FB17 0x00020000U |
| #define | CAN_F7R1_FB18 0x00040000U |
| #define | CAN_F7R1_FB19 0x00080000U |
| #define | CAN_F7R1_FB20 0x00100000U |
| #define | CAN_F7R1_FB21 0x00200000U |
| #define | CAN_F7R1_FB22 0x00400000U |
| #define | CAN_F7R1_FB23 0x00800000U |
| #define | CAN_F7R1_FB24 0x01000000U |
| #define | CAN_F7R1_FB25 0x02000000U |
| #define | CAN_F7R1_FB26 0x04000000U |
| #define | CAN_F7R1_FB27 0x08000000U |
| #define | CAN_F7R1_FB28 0x10000000U |
| #define | CAN_F7R1_FB29 0x20000000U |
| #define | CAN_F7R1_FB30 0x40000000U |
| #define | CAN_F7R1_FB31 0x80000000U |
| #define | CAN_F8R1_FB0 0x00000001U |
| #define | CAN_F8R1_FB1 0x00000002U |
| #define | CAN_F8R1_FB2 0x00000004U |
| #define | CAN_F8R1_FB3 0x00000008U |
| #define | CAN_F8R1_FB4 0x00000010U |
| #define | CAN_F8R1_FB5 0x00000020U |
| #define | CAN_F8R1_FB6 0x00000040U |
| #define | CAN_F8R1_FB7 0x00000080U |
| #define | CAN_F8R1_FB8 0x00000100U |
| #define | CAN_F8R1_FB9 0x00000200U |
| #define | CAN_F8R1_FB10 0x00000400U |
| #define | CAN_F8R1_FB11 0x00000800U |
| #define | CAN_F8R1_FB12 0x00001000U |
| #define | CAN_F8R1_FB13 0x00002000U |
| #define | CAN_F8R1_FB14 0x00004000U |
| #define | CAN_F8R1_FB15 0x00008000U |
| #define | CAN_F8R1_FB16 0x00010000U |
| #define | CAN_F8R1_FB17 0x00020000U |
| #define | CAN_F8R1_FB18 0x00040000U |
| #define | CAN_F8R1_FB19 0x00080000U |
| #define | CAN_F8R1_FB20 0x00100000U |
| #define | CAN_F8R1_FB21 0x00200000U |
| #define | CAN_F8R1_FB22 0x00400000U |
| #define | CAN_F8R1_FB23 0x00800000U |
| #define | CAN_F8R1_FB24 0x01000000U |
| #define | CAN_F8R1_FB25 0x02000000U |
| #define | CAN_F8R1_FB26 0x04000000U |
| #define | CAN_F8R1_FB27 0x08000000U |
| #define | CAN_F8R1_FB28 0x10000000U |
| #define | CAN_F8R1_FB29 0x20000000U |
| #define | CAN_F8R1_FB30 0x40000000U |
| #define | CAN_F8R1_FB31 0x80000000U |
| #define | CAN_F9R1_FB0 0x00000001U |
| #define | CAN_F9R1_FB1 0x00000002U |
| #define | CAN_F9R1_FB2 0x00000004U |
| #define | CAN_F9R1_FB3 0x00000008U |
| #define | CAN_F9R1_FB4 0x00000010U |
| #define | CAN_F9R1_FB5 0x00000020U |
| #define | CAN_F9R1_FB6 0x00000040U |
| #define | CAN_F9R1_FB7 0x00000080U |
| #define | CAN_F9R1_FB8 0x00000100U |
| #define | CAN_F9R1_FB9 0x00000200U |
| #define | CAN_F9R1_FB10 0x00000400U |
| #define | CAN_F9R1_FB11 0x00000800U |
| #define | CAN_F9R1_FB12 0x00001000U |
| #define | CAN_F9R1_FB13 0x00002000U |
| #define | CAN_F9R1_FB14 0x00004000U |
| #define | CAN_F9R1_FB15 0x00008000U |
| #define | CAN_F9R1_FB16 0x00010000U |
| #define | CAN_F9R1_FB17 0x00020000U |
| #define | CAN_F9R1_FB18 0x00040000U |
| #define | CAN_F9R1_FB19 0x00080000U |
| #define | CAN_F9R1_FB20 0x00100000U |
| #define | CAN_F9R1_FB21 0x00200000U |
| #define | CAN_F9R1_FB22 0x00400000U |
| #define | CAN_F9R1_FB23 0x00800000U |
| #define | CAN_F9R1_FB24 0x01000000U |
| #define | CAN_F9R1_FB25 0x02000000U |
| #define | CAN_F9R1_FB26 0x04000000U |
| #define | CAN_F9R1_FB27 0x08000000U |
| #define | CAN_F9R1_FB28 0x10000000U |
| #define | CAN_F9R1_FB29 0x20000000U |
| #define | CAN_F9R1_FB30 0x40000000U |
| #define | CAN_F9R1_FB31 0x80000000U |
| #define | CAN_F10R1_FB0 0x00000001U |
| #define | CAN_F10R1_FB1 0x00000002U |
| #define | CAN_F10R1_FB2 0x00000004U |
| #define | CAN_F10R1_FB3 0x00000008U |
| #define | CAN_F10R1_FB4 0x00000010U |
| #define | CAN_F10R1_FB5 0x00000020U |
| #define | CAN_F10R1_FB6 0x00000040U |
| #define | CAN_F10R1_FB7 0x00000080U |
| #define | CAN_F10R1_FB8 0x00000100U |
| #define | CAN_F10R1_FB9 0x00000200U |
| #define | CAN_F10R1_FB10 0x00000400U |
| #define | CAN_F10R1_FB11 0x00000800U |
| #define | CAN_F10R1_FB12 0x00001000U |
| #define | CAN_F10R1_FB13 0x00002000U |
| #define | CAN_F10R1_FB14 0x00004000U |
| #define | CAN_F10R1_FB15 0x00008000U |
| #define | CAN_F10R1_FB16 0x00010000U |
| #define | CAN_F10R1_FB17 0x00020000U |
| #define | CAN_F10R1_FB18 0x00040000U |
| #define | CAN_F10R1_FB19 0x00080000U |
| #define | CAN_F10R1_FB20 0x00100000U |
| #define | CAN_F10R1_FB21 0x00200000U |
| #define | CAN_F10R1_FB22 0x00400000U |
| #define | CAN_F10R1_FB23 0x00800000U |
| #define | CAN_F10R1_FB24 0x01000000U |
| #define | CAN_F10R1_FB25 0x02000000U |
| #define | CAN_F10R1_FB26 0x04000000U |
| #define | CAN_F10R1_FB27 0x08000000U |
| #define | CAN_F10R1_FB28 0x10000000U |
| #define | CAN_F10R1_FB29 0x20000000U |
| #define | CAN_F10R1_FB30 0x40000000U |
| #define | CAN_F10R1_FB31 0x80000000U |
| #define | CAN_F11R1_FB0 0x00000001U |
| #define | CAN_F11R1_FB1 0x00000002U |
| #define | CAN_F11R1_FB2 0x00000004U |
| #define | CAN_F11R1_FB3 0x00000008U |
| #define | CAN_F11R1_FB4 0x00000010U |
| #define | CAN_F11R1_FB5 0x00000020U |
| #define | CAN_F11R1_FB6 0x00000040U |
| #define | CAN_F11R1_FB7 0x00000080U |
| #define | CAN_F11R1_FB8 0x00000100U |
| #define | CAN_F11R1_FB9 0x00000200U |
| #define | CAN_F11R1_FB10 0x00000400U |
| #define | CAN_F11R1_FB11 0x00000800U |
| #define | CAN_F11R1_FB12 0x00001000U |
| #define | CAN_F11R1_FB13 0x00002000U |
| #define | CAN_F11R1_FB14 0x00004000U |
| #define | CAN_F11R1_FB15 0x00008000U |
| #define | CAN_F11R1_FB16 0x00010000U |
| #define | CAN_F11R1_FB17 0x00020000U |
| #define | CAN_F11R1_FB18 0x00040000U |
| #define | CAN_F11R1_FB19 0x00080000U |
| #define | CAN_F11R1_FB20 0x00100000U |
| #define | CAN_F11R1_FB21 0x00200000U |
| #define | CAN_F11R1_FB22 0x00400000U |
| #define | CAN_F11R1_FB23 0x00800000U |
| #define | CAN_F11R1_FB24 0x01000000U |
| #define | CAN_F11R1_FB25 0x02000000U |
| #define | CAN_F11R1_FB26 0x04000000U |
| #define | CAN_F11R1_FB27 0x08000000U |
| #define | CAN_F11R1_FB28 0x10000000U |
| #define | CAN_F11R1_FB29 0x20000000U |
| #define | CAN_F11R1_FB30 0x40000000U |
| #define | CAN_F11R1_FB31 0x80000000U |
| #define | CAN_F12R1_FB0 0x00000001U |
| #define | CAN_F12R1_FB1 0x00000002U |
| #define | CAN_F12R1_FB2 0x00000004U |
| #define | CAN_F12R1_FB3 0x00000008U |
| #define | CAN_F12R1_FB4 0x00000010U |
| #define | CAN_F12R1_FB5 0x00000020U |
| #define | CAN_F12R1_FB6 0x00000040U |
| #define | CAN_F12R1_FB7 0x00000080U |
| #define | CAN_F12R1_FB8 0x00000100U |
| #define | CAN_F12R1_FB9 0x00000200U |
| #define | CAN_F12R1_FB10 0x00000400U |
| #define | CAN_F12R1_FB11 0x00000800U |
| #define | CAN_F12R1_FB12 0x00001000U |
| #define | CAN_F12R1_FB13 0x00002000U |
| #define | CAN_F12R1_FB14 0x00004000U |
| #define | CAN_F12R1_FB15 0x00008000U |
| #define | CAN_F12R1_FB16 0x00010000U |
| #define | CAN_F12R1_FB17 0x00020000U |
| #define | CAN_F12R1_FB18 0x00040000U |
| #define | CAN_F12R1_FB19 0x00080000U |
| #define | CAN_F12R1_FB20 0x00100000U |
| #define | CAN_F12R1_FB21 0x00200000U |
| #define | CAN_F12R1_FB22 0x00400000U |
| #define | CAN_F12R1_FB23 0x00800000U |
| #define | CAN_F12R1_FB24 0x01000000U |
| #define | CAN_F12R1_FB25 0x02000000U |
| #define | CAN_F12R1_FB26 0x04000000U |
| #define | CAN_F12R1_FB27 0x08000000U |
| #define | CAN_F12R1_FB28 0x10000000U |
| #define | CAN_F12R1_FB29 0x20000000U |
| #define | CAN_F12R1_FB30 0x40000000U |
| #define | CAN_F12R1_FB31 0x80000000U |
| #define | CAN_F13R1_FB0 0x00000001U |
| #define | CAN_F13R1_FB1 0x00000002U |
| #define | CAN_F13R1_FB2 0x00000004U |
| #define | CAN_F13R1_FB3 0x00000008U |
| #define | CAN_F13R1_FB4 0x00000010U |
| #define | CAN_F13R1_FB5 0x00000020U |
| #define | CAN_F13R1_FB6 0x00000040U |
| #define | CAN_F13R1_FB7 0x00000080U |
| #define | CAN_F13R1_FB8 0x00000100U |
| #define | CAN_F13R1_FB9 0x00000200U |
| #define | CAN_F13R1_FB10 0x00000400U |
| #define | CAN_F13R1_FB11 0x00000800U |
| #define | CAN_F13R1_FB12 0x00001000U |
| #define | CAN_F13R1_FB13 0x00002000U |
| #define | CAN_F13R1_FB14 0x00004000U |
| #define | CAN_F13R1_FB15 0x00008000U |
| #define | CAN_F13R1_FB16 0x00010000U |
| #define | CAN_F13R1_FB17 0x00020000U |
| #define | CAN_F13R1_FB18 0x00040000U |
| #define | CAN_F13R1_FB19 0x00080000U |
| #define | CAN_F13R1_FB20 0x00100000U |
| #define | CAN_F13R1_FB21 0x00200000U |
| #define | CAN_F13R1_FB22 0x00400000U |
| #define | CAN_F13R1_FB23 0x00800000U |
| #define | CAN_F13R1_FB24 0x01000000U |
| #define | CAN_F13R1_FB25 0x02000000U |
| #define | CAN_F13R1_FB26 0x04000000U |
| #define | CAN_F13R1_FB27 0x08000000U |
| #define | CAN_F13R1_FB28 0x10000000U |
| #define | CAN_F13R1_FB29 0x20000000U |
| #define | CAN_F13R1_FB30 0x40000000U |
| #define | CAN_F13R1_FB31 0x80000000U |
| #define | CAN_F0R2_FB0 0x00000001U |
| #define | CAN_F0R2_FB1 0x00000002U |
| #define | CAN_F0R2_FB2 0x00000004U |
| #define | CAN_F0R2_FB3 0x00000008U |
| #define | CAN_F0R2_FB4 0x00000010U |
| #define | CAN_F0R2_FB5 0x00000020U |
| #define | CAN_F0R2_FB6 0x00000040U |
| #define | CAN_F0R2_FB7 0x00000080U |
| #define | CAN_F0R2_FB8 0x00000100U |
| #define | CAN_F0R2_FB9 0x00000200U |
| #define | CAN_F0R2_FB10 0x00000400U |
| #define | CAN_F0R2_FB11 0x00000800U |
| #define | CAN_F0R2_FB12 0x00001000U |
| #define | CAN_F0R2_FB13 0x00002000U |
| #define | CAN_F0R2_FB14 0x00004000U |
| #define | CAN_F0R2_FB15 0x00008000U |
| #define | CAN_F0R2_FB16 0x00010000U |
| #define | CAN_F0R2_FB17 0x00020000U |
| #define | CAN_F0R2_FB18 0x00040000U |
| #define | CAN_F0R2_FB19 0x00080000U |
| #define | CAN_F0R2_FB20 0x00100000U |
| #define | CAN_F0R2_FB21 0x00200000U |
| #define | CAN_F0R2_FB22 0x00400000U |
| #define | CAN_F0R2_FB23 0x00800000U |
| #define | CAN_F0R2_FB24 0x01000000U |
| #define | CAN_F0R2_FB25 0x02000000U |
| #define | CAN_F0R2_FB26 0x04000000U |
| #define | CAN_F0R2_FB27 0x08000000U |
| #define | CAN_F0R2_FB28 0x10000000U |
| #define | CAN_F0R2_FB29 0x20000000U |
| #define | CAN_F0R2_FB30 0x40000000U |
| #define | CAN_F0R2_FB31 0x80000000U |
| #define | CAN_F1R2_FB0 0x00000001U |
| #define | CAN_F1R2_FB1 0x00000002U |
| #define | CAN_F1R2_FB2 0x00000004U |
| #define | CAN_F1R2_FB3 0x00000008U |
| #define | CAN_F1R2_FB4 0x00000010U |
| #define | CAN_F1R2_FB5 0x00000020U |
| #define | CAN_F1R2_FB6 0x00000040U |
| #define | CAN_F1R2_FB7 0x00000080U |
| #define | CAN_F1R2_FB8 0x00000100U |
| #define | CAN_F1R2_FB9 0x00000200U |
| #define | CAN_F1R2_FB10 0x00000400U |
| #define | CAN_F1R2_FB11 0x00000800U |
| #define | CAN_F1R2_FB12 0x00001000U |
| #define | CAN_F1R2_FB13 0x00002000U |
| #define | CAN_F1R2_FB14 0x00004000U |
| #define | CAN_F1R2_FB15 0x00008000U |
| #define | CAN_F1R2_FB16 0x00010000U |
| #define | CAN_F1R2_FB17 0x00020000U |
| #define | CAN_F1R2_FB18 0x00040000U |
| #define | CAN_F1R2_FB19 0x00080000U |
| #define | CAN_F1R2_FB20 0x00100000U |
| #define | CAN_F1R2_FB21 0x00200000U |
| #define | CAN_F1R2_FB22 0x00400000U |
| #define | CAN_F1R2_FB23 0x00800000U |
| #define | CAN_F1R2_FB24 0x01000000U |
| #define | CAN_F1R2_FB25 0x02000000U |
| #define | CAN_F1R2_FB26 0x04000000U |
| #define | CAN_F1R2_FB27 0x08000000U |
| #define | CAN_F1R2_FB28 0x10000000U |
| #define | CAN_F1R2_FB29 0x20000000U |
| #define | CAN_F1R2_FB30 0x40000000U |
| #define | CAN_F1R2_FB31 0x80000000U |
| #define | CAN_F2R2_FB0 0x00000001U |
| #define | CAN_F2R2_FB1 0x00000002U |
| #define | CAN_F2R2_FB2 0x00000004U |
| #define | CAN_F2R2_FB3 0x00000008U |
| #define | CAN_F2R2_FB4 0x00000010U |
| #define | CAN_F2R2_FB5 0x00000020U |
| #define | CAN_F2R2_FB6 0x00000040U |
| #define | CAN_F2R2_FB7 0x00000080U |
| #define | CAN_F2R2_FB8 0x00000100U |
| #define | CAN_F2R2_FB9 0x00000200U |
| #define | CAN_F2R2_FB10 0x00000400U |
| #define | CAN_F2R2_FB11 0x00000800U |
| #define | CAN_F2R2_FB12 0x00001000U |
| #define | CAN_F2R2_FB13 0x00002000U |
| #define | CAN_F2R2_FB14 0x00004000U |
| #define | CAN_F2R2_FB15 0x00008000U |
| #define | CAN_F2R2_FB16 0x00010000U |
| #define | CAN_F2R2_FB17 0x00020000U |
| #define | CAN_F2R2_FB18 0x00040000U |
| #define | CAN_F2R2_FB19 0x00080000U |
| #define | CAN_F2R2_FB20 0x00100000U |
| #define | CAN_F2R2_FB21 0x00200000U |
| #define | CAN_F2R2_FB22 0x00400000U |
| #define | CAN_F2R2_FB23 0x00800000U |
| #define | CAN_F2R2_FB24 0x01000000U |
| #define | CAN_F2R2_FB25 0x02000000U |
| #define | CAN_F2R2_FB26 0x04000000U |
| #define | CAN_F2R2_FB27 0x08000000U |
| #define | CAN_F2R2_FB28 0x10000000U |
| #define | CAN_F2R2_FB29 0x20000000U |
| #define | CAN_F2R2_FB30 0x40000000U |
| #define | CAN_F2R2_FB31 0x80000000U |
| #define | CAN_F3R2_FB0 0x00000001U |
| #define | CAN_F3R2_FB1 0x00000002U |
| #define | CAN_F3R2_FB2 0x00000004U |
| #define | CAN_F3R2_FB3 0x00000008U |
| #define | CAN_F3R2_FB4 0x00000010U |
| #define | CAN_F3R2_FB5 0x00000020U |
| #define | CAN_F3R2_FB6 0x00000040U |
| #define | CAN_F3R2_FB7 0x00000080U |
| #define | CAN_F3R2_FB8 0x00000100U |
| #define | CAN_F3R2_FB9 0x00000200U |
| #define | CAN_F3R2_FB10 0x00000400U |
| #define | CAN_F3R2_FB11 0x00000800U |
| #define | CAN_F3R2_FB12 0x00001000U |
| #define | CAN_F3R2_FB13 0x00002000U |
| #define | CAN_F3R2_FB14 0x00004000U |
| #define | CAN_F3R2_FB15 0x00008000U |
| #define | CAN_F3R2_FB16 0x00010000U |
| #define | CAN_F3R2_FB17 0x00020000U |
| #define | CAN_F3R2_FB18 0x00040000U |
| #define | CAN_F3R2_FB19 0x00080000U |
| #define | CAN_F3R2_FB20 0x00100000U |
| #define | CAN_F3R2_FB21 0x00200000U |
| #define | CAN_F3R2_FB22 0x00400000U |
| #define | CAN_F3R2_FB23 0x00800000U |
| #define | CAN_F3R2_FB24 0x01000000U |
| #define | CAN_F3R2_FB25 0x02000000U |
| #define | CAN_F3R2_FB26 0x04000000U |
| #define | CAN_F3R2_FB27 0x08000000U |
| #define | CAN_F3R2_FB28 0x10000000U |
| #define | CAN_F3R2_FB29 0x20000000U |
| #define | CAN_F3R2_FB30 0x40000000U |
| #define | CAN_F3R2_FB31 0x80000000U |
| #define | CAN_F4R2_FB0 0x00000001U |
| #define | CAN_F4R2_FB1 0x00000002U |
| #define | CAN_F4R2_FB2 0x00000004U |
| #define | CAN_F4R2_FB3 0x00000008U |
| #define | CAN_F4R2_FB4 0x00000010U |
| #define | CAN_F4R2_FB5 0x00000020U |
| #define | CAN_F4R2_FB6 0x00000040U |
| #define | CAN_F4R2_FB7 0x00000080U |
| #define | CAN_F4R2_FB8 0x00000100U |
| #define | CAN_F4R2_FB9 0x00000200U |
| #define | CAN_F4R2_FB10 0x00000400U |
| #define | CAN_F4R2_FB11 0x00000800U |
| #define | CAN_F4R2_FB12 0x00001000U |
| #define | CAN_F4R2_FB13 0x00002000U |
| #define | CAN_F4R2_FB14 0x00004000U |
| #define | CAN_F4R2_FB15 0x00008000U |
| #define | CAN_F4R2_FB16 0x00010000U |
| #define | CAN_F4R2_FB17 0x00020000U |
| #define | CAN_F4R2_FB18 0x00040000U |
| #define | CAN_F4R2_FB19 0x00080000U |
| #define | CAN_F4R2_FB20 0x00100000U |
| #define | CAN_F4R2_FB21 0x00200000U |
| #define | CAN_F4R2_FB22 0x00400000U |
| #define | CAN_F4R2_FB23 0x00800000U |
| #define | CAN_F4R2_FB24 0x01000000U |
| #define | CAN_F4R2_FB25 0x02000000U |
| #define | CAN_F4R2_FB26 0x04000000U |
| #define | CAN_F4R2_FB27 0x08000000U |
| #define | CAN_F4R2_FB28 0x10000000U |
| #define | CAN_F4R2_FB29 0x20000000U |
| #define | CAN_F4R2_FB30 0x40000000U |
| #define | CAN_F4R2_FB31 0x80000000U |
| #define | CAN_F5R2_FB0 0x00000001U |
| #define | CAN_F5R2_FB1 0x00000002U |
| #define | CAN_F5R2_FB2 0x00000004U |
| #define | CAN_F5R2_FB3 0x00000008U |
| #define | CAN_F5R2_FB4 0x00000010U |
| #define | CAN_F5R2_FB5 0x00000020U |
| #define | CAN_F5R2_FB6 0x00000040U |
| #define | CAN_F5R2_FB7 0x00000080U |
| #define | CAN_F5R2_FB8 0x00000100U |
| #define | CAN_F5R2_FB9 0x00000200U |
| #define | CAN_F5R2_FB10 0x00000400U |
| #define | CAN_F5R2_FB11 0x00000800U |
| #define | CAN_F5R2_FB12 0x00001000U |
| #define | CAN_F5R2_FB13 0x00002000U |
| #define | CAN_F5R2_FB14 0x00004000U |
| #define | CAN_F5R2_FB15 0x00008000U |
| #define | CAN_F5R2_FB16 0x00010000U |
| #define | CAN_F5R2_FB17 0x00020000U |
| #define | CAN_F5R2_FB18 0x00040000U |
| #define | CAN_F5R2_FB19 0x00080000U |
| #define | CAN_F5R2_FB20 0x00100000U |
| #define | CAN_F5R2_FB21 0x00200000U |
| #define | CAN_F5R2_FB22 0x00400000U |
| #define | CAN_F5R2_FB23 0x00800000U |
| #define | CAN_F5R2_FB24 0x01000000U |
| #define | CAN_F5R2_FB25 0x02000000U |
| #define | CAN_F5R2_FB26 0x04000000U |
| #define | CAN_F5R2_FB27 0x08000000U |
| #define | CAN_F5R2_FB28 0x10000000U |
| #define | CAN_F5R2_FB29 0x20000000U |
| #define | CAN_F5R2_FB30 0x40000000U |
| #define | CAN_F5R2_FB31 0x80000000U |
| #define | CAN_F6R2_FB0 0x00000001U |
| #define | CAN_F6R2_FB1 0x00000002U |
| #define | CAN_F6R2_FB2 0x00000004U |
| #define | CAN_F6R2_FB3 0x00000008U |
| #define | CAN_F6R2_FB4 0x00000010U |
| #define | CAN_F6R2_FB5 0x00000020U |
| #define | CAN_F6R2_FB6 0x00000040U |
| #define | CAN_F6R2_FB7 0x00000080U |
| #define | CAN_F6R2_FB8 0x00000100U |
| #define | CAN_F6R2_FB9 0x00000200U |
| #define | CAN_F6R2_FB10 0x00000400U |
| #define | CAN_F6R2_FB11 0x00000800U |
| #define | CAN_F6R2_FB12 0x00001000U |
| #define | CAN_F6R2_FB13 0x00002000U |
| #define | CAN_F6R2_FB14 0x00004000U |
| #define | CAN_F6R2_FB15 0x00008000U |
| #define | CAN_F6R2_FB16 0x00010000U |
| #define | CAN_F6R2_FB17 0x00020000U |
| #define | CAN_F6R2_FB18 0x00040000U |
| #define | CAN_F6R2_FB19 0x00080000U |
| #define | CAN_F6R2_FB20 0x00100000U |
| #define | CAN_F6R2_FB21 0x00200000U |
| #define | CAN_F6R2_FB22 0x00400000U |
| #define | CAN_F6R2_FB23 0x00800000U |
| #define | CAN_F6R2_FB24 0x01000000U |
| #define | CAN_F6R2_FB25 0x02000000U |
| #define | CAN_F6R2_FB26 0x04000000U |
| #define | CAN_F6R2_FB27 0x08000000U |
| #define | CAN_F6R2_FB28 0x10000000U |
| #define | CAN_F6R2_FB29 0x20000000U |
| #define | CAN_F6R2_FB30 0x40000000U |
| #define | CAN_F6R2_FB31 0x80000000U |
| #define | CAN_F7R2_FB0 0x00000001U |
| #define | CAN_F7R2_FB1 0x00000002U |
| #define | CAN_F7R2_FB2 0x00000004U |
| #define | CAN_F7R2_FB3 0x00000008U |
| #define | CAN_F7R2_FB4 0x00000010U |
| #define | CAN_F7R2_FB5 0x00000020U |
| #define | CAN_F7R2_FB6 0x00000040U |
| #define | CAN_F7R2_FB7 0x00000080U |
| #define | CAN_F7R2_FB8 0x00000100U |
| #define | CAN_F7R2_FB9 0x00000200U |
| #define | CAN_F7R2_FB10 0x00000400U |
| #define | CAN_F7R2_FB11 0x00000800U |
| #define | CAN_F7R2_FB12 0x00001000U |
| #define | CAN_F7R2_FB13 0x00002000U |
| #define | CAN_F7R2_FB14 0x00004000U |
| #define | CAN_F7R2_FB15 0x00008000U |
| #define | CAN_F7R2_FB16 0x00010000U |
| #define | CAN_F7R2_FB17 0x00020000U |
| #define | CAN_F7R2_FB18 0x00040000U |
| #define | CAN_F7R2_FB19 0x00080000U |
| #define | CAN_F7R2_FB20 0x00100000U |
| #define | CAN_F7R2_FB21 0x00200000U |
| #define | CAN_F7R2_FB22 0x00400000U |
| #define | CAN_F7R2_FB23 0x00800000U |
| #define | CAN_F7R2_FB24 0x01000000U |
| #define | CAN_F7R2_FB25 0x02000000U |
| #define | CAN_F7R2_FB26 0x04000000U |
| #define | CAN_F7R2_FB27 0x08000000U |
| #define | CAN_F7R2_FB28 0x10000000U |
| #define | CAN_F7R2_FB29 0x20000000U |
| #define | CAN_F7R2_FB30 0x40000000U |
| #define | CAN_F7R2_FB31 0x80000000U |
| #define | CAN_F8R2_FB0 0x00000001U |
| #define | CAN_F8R2_FB1 0x00000002U |
| #define | CAN_F8R2_FB2 0x00000004U |
| #define | CAN_F8R2_FB3 0x00000008U |
| #define | CAN_F8R2_FB4 0x00000010U |
| #define | CAN_F8R2_FB5 0x00000020U |
| #define | CAN_F8R2_FB6 0x00000040U |
| #define | CAN_F8R2_FB7 0x00000080U |
| #define | CAN_F8R2_FB8 0x00000100U |
| #define | CAN_F8R2_FB9 0x00000200U |
| #define | CAN_F8R2_FB10 0x00000400U |
| #define | CAN_F8R2_FB11 0x00000800U |
| #define | CAN_F8R2_FB12 0x00001000U |
| #define | CAN_F8R2_FB13 0x00002000U |
| #define | CAN_F8R2_FB14 0x00004000U |
| #define | CAN_F8R2_FB15 0x00008000U |
| #define | CAN_F8R2_FB16 0x00010000U |
| #define | CAN_F8R2_FB17 0x00020000U |
| #define | CAN_F8R2_FB18 0x00040000U |
| #define | CAN_F8R2_FB19 0x00080000U |
| #define | CAN_F8R2_FB20 0x00100000U |
| #define | CAN_F8R2_FB21 0x00200000U |
| #define | CAN_F8R2_FB22 0x00400000U |
| #define | CAN_F8R2_FB23 0x00800000U |
| #define | CAN_F8R2_FB24 0x01000000U |
| #define | CAN_F8R2_FB25 0x02000000U |
| #define | CAN_F8R2_FB26 0x04000000U |
| #define | CAN_F8R2_FB27 0x08000000U |
| #define | CAN_F8R2_FB28 0x10000000U |
| #define | CAN_F8R2_FB29 0x20000000U |
| #define | CAN_F8R2_FB30 0x40000000U |
| #define | CAN_F8R2_FB31 0x80000000U |
| #define | CAN_F9R2_FB0 0x00000001U |
| #define | CAN_F9R2_FB1 0x00000002U |
| #define | CAN_F9R2_FB2 0x00000004U |
| #define | CAN_F9R2_FB3 0x00000008U |
| #define | CAN_F9R2_FB4 0x00000010U |
| #define | CAN_F9R2_FB5 0x00000020U |
| #define | CAN_F9R2_FB6 0x00000040U |
| #define | CAN_F9R2_FB7 0x00000080U |
| #define | CAN_F9R2_FB8 0x00000100U |
| #define | CAN_F9R2_FB9 0x00000200U |
| #define | CAN_F9R2_FB10 0x00000400U |
| #define | CAN_F9R2_FB11 0x00000800U |
| #define | CAN_F9R2_FB12 0x00001000U |
| #define | CAN_F9R2_FB13 0x00002000U |
| #define | CAN_F9R2_FB14 0x00004000U |
| #define | CAN_F9R2_FB15 0x00008000U |
| #define | CAN_F9R2_FB16 0x00010000U |
| #define | CAN_F9R2_FB17 0x00020000U |
| #define | CAN_F9R2_FB18 0x00040000U |
| #define | CAN_F9R2_FB19 0x00080000U |
| #define | CAN_F9R2_FB20 0x00100000U |
| #define | CAN_F9R2_FB21 0x00200000U |
| #define | CAN_F9R2_FB22 0x00400000U |
| #define | CAN_F9R2_FB23 0x00800000U |
| #define | CAN_F9R2_FB24 0x01000000U |
| #define | CAN_F9R2_FB25 0x02000000U |
| #define | CAN_F9R2_FB26 0x04000000U |
| #define | CAN_F9R2_FB27 0x08000000U |
| #define | CAN_F9R2_FB28 0x10000000U |
| #define | CAN_F9R2_FB29 0x20000000U |
| #define | CAN_F9R2_FB30 0x40000000U |
| #define | CAN_F9R2_FB31 0x80000000U |
| #define | CAN_F10R2_FB0 0x00000001U |
| #define | CAN_F10R2_FB1 0x00000002U |
| #define | CAN_F10R2_FB2 0x00000004U |
| #define | CAN_F10R2_FB3 0x00000008U |
| #define | CAN_F10R2_FB4 0x00000010U |
| #define | CAN_F10R2_FB5 0x00000020U |
| #define | CAN_F10R2_FB6 0x00000040U |
| #define | CAN_F10R2_FB7 0x00000080U |
| #define | CAN_F10R2_FB8 0x00000100U |
| #define | CAN_F10R2_FB9 0x00000200U |
| #define | CAN_F10R2_FB10 0x00000400U |
| #define | CAN_F10R2_FB11 0x00000800U |
| #define | CAN_F10R2_FB12 0x00001000U |
| #define | CAN_F10R2_FB13 0x00002000U |
| #define | CAN_F10R2_FB14 0x00004000U |
| #define | CAN_F10R2_FB15 0x00008000U |
| #define | CAN_F10R2_FB16 0x00010000U |
| #define | CAN_F10R2_FB17 0x00020000U |
| #define | CAN_F10R2_FB18 0x00040000U |
| #define | CAN_F10R2_FB19 0x00080000U |
| #define | CAN_F10R2_FB20 0x00100000U |
| #define | CAN_F10R2_FB21 0x00200000U |
| #define | CAN_F10R2_FB22 0x00400000U |
| #define | CAN_F10R2_FB23 0x00800000U |
| #define | CAN_F10R2_FB24 0x01000000U |
| #define | CAN_F10R2_FB25 0x02000000U |
| #define | CAN_F10R2_FB26 0x04000000U |
| #define | CAN_F10R2_FB27 0x08000000U |
| #define | CAN_F10R2_FB28 0x10000000U |
| #define | CAN_F10R2_FB29 0x20000000U |
| #define | CAN_F10R2_FB30 0x40000000U |
| #define | CAN_F10R2_FB31 0x80000000U |
| #define | CAN_F11R2_FB0 0x00000001U |
| #define | CAN_F11R2_FB1 0x00000002U |
| #define | CAN_F11R2_FB2 0x00000004U |
| #define | CAN_F11R2_FB3 0x00000008U |
| #define | CAN_F11R2_FB4 0x00000010U |
| #define | CAN_F11R2_FB5 0x00000020U |
| #define | CAN_F11R2_FB6 0x00000040U |
| #define | CAN_F11R2_FB7 0x00000080U |
| #define | CAN_F11R2_FB8 0x00000100U |
| #define | CAN_F11R2_FB9 0x00000200U |
| #define | CAN_F11R2_FB10 0x00000400U |
| #define | CAN_F11R2_FB11 0x00000800U |
| #define | CAN_F11R2_FB12 0x00001000U |
| #define | CAN_F11R2_FB13 0x00002000U |
| #define | CAN_F11R2_FB14 0x00004000U |
| #define | CAN_F11R2_FB15 0x00008000U |
| #define | CAN_F11R2_FB16 0x00010000U |
| #define | CAN_F11R2_FB17 0x00020000U |
| #define | CAN_F11R2_FB18 0x00040000U |
| #define | CAN_F11R2_FB19 0x00080000U |
| #define | CAN_F11R2_FB20 0x00100000U |
| #define | CAN_F11R2_FB21 0x00200000U |
| #define | CAN_F11R2_FB22 0x00400000U |
| #define | CAN_F11R2_FB23 0x00800000U |
| #define | CAN_F11R2_FB24 0x01000000U |
| #define | CAN_F11R2_FB25 0x02000000U |
| #define | CAN_F11R2_FB26 0x04000000U |
| #define | CAN_F11R2_FB27 0x08000000U |
| #define | CAN_F11R2_FB28 0x10000000U |
| #define | CAN_F11R2_FB29 0x20000000U |
| #define | CAN_F11R2_FB30 0x40000000U |
| #define | CAN_F11R2_FB31 0x80000000U |
| #define | CAN_F12R2_FB0 0x00000001U |
| #define | CAN_F12R2_FB1 0x00000002U |
| #define | CAN_F12R2_FB2 0x00000004U |
| #define | CAN_F12R2_FB3 0x00000008U |
| #define | CAN_F12R2_FB4 0x00000010U |
| #define | CAN_F12R2_FB5 0x00000020U |
| #define | CAN_F12R2_FB6 0x00000040U |
| #define | CAN_F12R2_FB7 0x00000080U |
| #define | CAN_F12R2_FB8 0x00000100U |
| #define | CAN_F12R2_FB9 0x00000200U |
| #define | CAN_F12R2_FB10 0x00000400U |
| #define | CAN_F12R2_FB11 0x00000800U |
| #define | CAN_F12R2_FB12 0x00001000U |
| #define | CAN_F12R2_FB13 0x00002000U |
| #define | CAN_F12R2_FB14 0x00004000U |
| #define | CAN_F12R2_FB15 0x00008000U |
| #define | CAN_F12R2_FB16 0x00010000U |
| #define | CAN_F12R2_FB17 0x00020000U |
| #define | CAN_F12R2_FB18 0x00040000U |
| #define | CAN_F12R2_FB19 0x00080000U |
| #define | CAN_F12R2_FB20 0x00100000U |
| #define | CAN_F12R2_FB21 0x00200000U |
| #define | CAN_F12R2_FB22 0x00400000U |
| #define | CAN_F12R2_FB23 0x00800000U |
| #define | CAN_F12R2_FB24 0x01000000U |
| #define | CAN_F12R2_FB25 0x02000000U |
| #define | CAN_F12R2_FB26 0x04000000U |
| #define | CAN_F12R2_FB27 0x08000000U |
| #define | CAN_F12R2_FB28 0x10000000U |
| #define | CAN_F12R2_FB29 0x20000000U |
| #define | CAN_F12R2_FB30 0x40000000U |
| #define | CAN_F12R2_FB31 0x80000000U |
| #define | CAN_F13R2_FB0 0x00000001U |
| #define | CAN_F13R2_FB1 0x00000002U |
| #define | CAN_F13R2_FB2 0x00000004U |
| #define | CAN_F13R2_FB3 0x00000008U |
| #define | CAN_F13R2_FB4 0x00000010U |
| #define | CAN_F13R2_FB5 0x00000020U |
| #define | CAN_F13R2_FB6 0x00000040U |
| #define | CAN_F13R2_FB7 0x00000080U |
| #define | CAN_F13R2_FB8 0x00000100U |
| #define | CAN_F13R2_FB9 0x00000200U |
| #define | CAN_F13R2_FB10 0x00000400U |
| #define | CAN_F13R2_FB11 0x00000800U |
| #define | CAN_F13R2_FB12 0x00001000U |
| #define | CAN_F13R2_FB13 0x00002000U |
| #define | CAN_F13R2_FB14 0x00004000U |
| #define | CAN_F13R2_FB15 0x00008000U |
| #define | CAN_F13R2_FB16 0x00010000U |
| #define | CAN_F13R2_FB17 0x00020000U |
| #define | CAN_F13R2_FB18 0x00040000U |
| #define | CAN_F13R2_FB19 0x00080000U |
| #define | CAN_F13R2_FB20 0x00100000U |
| #define | CAN_F13R2_FB21 0x00200000U |
| #define | CAN_F13R2_FB22 0x00400000U |
| #define | CAN_F13R2_FB23 0x00800000U |
| #define | CAN_F13R2_FB24 0x01000000U |
| #define | CAN_F13R2_FB25 0x02000000U |
| #define | CAN_F13R2_FB26 0x04000000U |
| #define | CAN_F13R2_FB27 0x08000000U |
| #define | CAN_F13R2_FB28 0x10000000U |
| #define | CAN_F13R2_FB29 0x20000000U |
| #define | CAN_F13R2_FB30 0x40000000U |
| #define | CAN_F13R2_FB31 0x80000000U |
| #define | CRC_DR_DR 0xFFFFFFFFU |
| #define | CRC_IDR_IDR 0xFFU |
| #define | CRC_CR_RESET 0x01U |
| #define | DAC_CR_EN1 0x00000001U |
| #define | DAC_CR_BOFF1 0x00000002U |
| #define | DAC_CR_TEN1 0x00000004U |
| #define | DAC_CR_TSEL1 0x00000038U |
| #define | DAC_CR_TSEL1_0 0x00000008U |
| #define | DAC_CR_TSEL1_1 0x00000010U |
| #define | DAC_CR_TSEL1_2 0x00000020U |
| #define | DAC_CR_WAVE1 0x000000C0U |
| #define | DAC_CR_WAVE1_0 0x00000040U |
| #define | DAC_CR_WAVE1_1 0x00000080U |
| #define | DAC_CR_MAMP1 0x00000F00U |
| #define | DAC_CR_MAMP1_0 0x00000100U |
| #define | DAC_CR_MAMP1_1 0x00000200U |
| #define | DAC_CR_MAMP1_2 0x00000400U |
| #define | DAC_CR_MAMP1_3 0x00000800U |
| #define | DAC_CR_DMAEN1 0x00001000U |
| #define | DAC_CR_DMAUDRIE1 0x00002000U |
| #define | DAC_CR_EN2 0x00010000U |
| #define | DAC_CR_BOFF2 0x00020000U |
| #define | DAC_CR_TEN2 0x00040000U |
| #define | DAC_CR_TSEL2 0x00380000U |
| #define | DAC_CR_TSEL2_0 0x00080000U |
| #define | DAC_CR_TSEL2_1 0x00100000U |
| #define | DAC_CR_TSEL2_2 0x00200000U |
| #define | DAC_CR_WAVE2 0x00C00000U |
| #define | DAC_CR_WAVE2_0 0x00400000U |
| #define | DAC_CR_WAVE2_1 0x00800000U |
| #define | DAC_CR_MAMP2 0x0F000000U |
| #define | DAC_CR_MAMP2_0 0x01000000U |
| #define | DAC_CR_MAMP2_1 0x02000000U |
| #define | DAC_CR_MAMP2_2 0x04000000U |
| #define | DAC_CR_MAMP2_3 0x08000000U |
| #define | DAC_CR_DMAEN2 0x10000000U |
| #define | DAC_CR_DMAUDRIE2 0x20000000U |
| #define | DAC_SWTRIGR_SWTRIG1 0x01U |
| #define | DAC_SWTRIGR_SWTRIG2 0x02U |
| #define | DAC_DHR12R1_DACC1DHR 0x0FFFU |
| #define | DAC_DHR12L1_DACC1DHR 0xFFF0U |
| #define | DAC_DHR8R1_DACC1DHR 0xFFU |
| #define | DAC_DHR12R2_DACC2DHR 0x0FFFU |
| #define | DAC_DHR12L2_DACC2DHR 0xFFF0U |
| #define | DAC_DHR8R2_DACC2DHR 0xFFU |
| #define | DAC_DHR12RD_DACC1DHR 0x00000FFFU |
| #define | DAC_DHR12RD_DACC2DHR 0x0FFF0000U |
| #define | DAC_DHR12LD_DACC1DHR 0x0000FFF0U |
| #define | DAC_DHR12LD_DACC2DHR 0xFFF00000U |
| #define | DAC_DHR8RD_DACC1DHR 0x00FFU |
| #define | DAC_DHR8RD_DACC2DHR 0xFF00U |
| #define | DAC_DOR1_DACC1DOR 0x0FFFU |
| #define | DAC_DOR2_DACC2DOR 0x0FFFU |
| #define | DAC_SR_DMAUDR1 0x00002000U |
| #define | DAC_SR_DMAUDR2 0x20000000U |
| #define | DCMI_CR_CAPTURE 0x00000001U |
| #define | DCMI_CR_CM 0x00000002U |
| #define | DCMI_CR_CROP 0x00000004U |
| #define | DCMI_CR_JPEG 0x00000008U |
| #define | DCMI_CR_ESS 0x00000010U |
| #define | DCMI_CR_PCKPOL 0x00000020U |
| #define | DCMI_CR_HSPOL 0x00000040U |
| #define | DCMI_CR_VSPOL 0x00000080U |
| #define | DCMI_CR_FCRC_0 0x00000100U |
| #define | DCMI_CR_FCRC_1 0x00000200U |
| #define | DCMI_CR_EDM_0 0x00000400U |
| #define | DCMI_CR_EDM_1 0x00000800U |
| #define | DCMI_CR_CRE 0x00001000U |
| #define | DCMI_CR_ENABLE 0x00004000U |
| #define | DCMI_SR_HSYNC 0x00000001U |
| #define | DCMI_SR_VSYNC 0x00000002U |
| #define | DCMI_SR_FNE 0x00000004U |
| #define | DCMI_RIS_FRAME_RIS 0x00000001U |
| #define | DCMI_RIS_OVR_RIS 0x00000002U |
| #define | DCMI_RIS_ERR_RIS 0x00000004U |
| #define | DCMI_RIS_VSYNC_RIS 0x00000008U |
| #define | DCMI_RIS_LINE_RIS 0x00000010U |
| #define | DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS |
| #define | DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS |
| #define | DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS |
| #define | DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS |
| #define | DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS |
| #define | DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS |
| #define | DCMI_IER_FRAME_IE 0x00000001U |
| #define | DCMI_IER_OVR_IE 0x00000002U |
| #define | DCMI_IER_ERR_IE 0x00000004U |
| #define | DCMI_IER_VSYNC_IE 0x00000008U |
| #define | DCMI_IER_LINE_IE 0x00000010U |
| #define | DCMI_IER_OVF_IE DCMI_IER_OVR_IE |
| #define | DCMI_MIS_FRAME_MIS 0x00000001U |
| #define | DCMI_MIS_OVR_MIS 0x00000002U |
| #define | DCMI_MIS_ERR_MIS 0x00000004U |
| #define | DCMI_MIS_VSYNC_MIS 0x00000008U |
| #define | DCMI_MIS_LINE_MIS 0x00000010U |
| #define | DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS |
| #define | DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS |
| #define | DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS |
| #define | DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS |
| #define | DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS |
| #define | DCMI_ICR_FRAME_ISC 0x00000001U |
| #define | DCMI_ICR_OVR_ISC 0x00000002U |
| #define | DCMI_ICR_ERR_ISC 0x00000004U |
| #define | DCMI_ICR_VSYNC_ISC 0x00000008U |
| #define | DCMI_ICR_LINE_ISC 0x00000010U |
| #define | DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC |
| #define | DCMI_ESCR_FSC 0x000000FFU |
| #define | DCMI_ESCR_LSC 0x0000FF00U |
| #define | DCMI_ESCR_LEC 0x00FF0000U |
| #define | DCMI_ESCR_FEC 0xFF000000U |
| #define | DCMI_ESUR_FSU 0x000000FFU |
| #define | DCMI_ESUR_LSU 0x0000FF00U |
| #define | DCMI_ESUR_LEU 0x00FF0000U |
| #define | DCMI_ESUR_FEU 0xFF000000U |
| #define | DCMI_CWSTRT_HOFFCNT 0x00003FFFU |
| #define | DCMI_CWSTRT_VST 0x1FFF0000U |
| #define | DCMI_CWSIZE_CAPCNT 0x00003FFFU |
| #define | DCMI_CWSIZE_VLINE 0x3FFF0000U |
| #define | DCMI_DR_BYTE0 0x000000FFU |
| #define | DCMI_DR_BYTE1 0x0000FF00U |
| #define | DCMI_DR_BYTE2 0x00FF0000U |
| #define | DCMI_DR_BYTE3 0xFF000000U |
| #define | DMA_SxCR_CHSEL 0x0E000000U |
| #define | DMA_SxCR_CHSEL_0 0x02000000U |
| #define | DMA_SxCR_CHSEL_1 0x04000000U |
| #define | DMA_SxCR_CHSEL_2 0x08000000U |
| #define | DMA_SxCR_MBURST 0x01800000U |
| #define | DMA_SxCR_MBURST_0 0x00800000U |
| #define | DMA_SxCR_MBURST_1 0x01000000U |
| #define | DMA_SxCR_PBURST 0x00600000U |
| #define | DMA_SxCR_PBURST_0 0x00200000U |
| #define | DMA_SxCR_PBURST_1 0x00400000U |
| #define | DMA_SxCR_CT 0x00080000U |
| #define | DMA_SxCR_DBM 0x00040000U |
| #define | DMA_SxCR_PL 0x00030000U |
| #define | DMA_SxCR_PL_0 0x00010000U |
| #define | DMA_SxCR_PL_1 0x00020000U |
| #define | DMA_SxCR_PINCOS 0x00008000U |
| #define | DMA_SxCR_MSIZE 0x00006000U |
| #define | DMA_SxCR_MSIZE_0 0x00002000U |
| #define | DMA_SxCR_MSIZE_1 0x00004000U |
| #define | DMA_SxCR_PSIZE 0x00001800U |
| #define | DMA_SxCR_PSIZE_0 0x00000800U |
| #define | DMA_SxCR_PSIZE_1 0x00001000U |
| #define | DMA_SxCR_MINC 0x00000400U |
| #define | DMA_SxCR_PINC 0x00000200U |
| #define | DMA_SxCR_CIRC 0x00000100U |
| #define | DMA_SxCR_DIR 0x000000C0U |
| #define | DMA_SxCR_DIR_0 0x00000040U |
| #define | DMA_SxCR_DIR_1 0x00000080U |
| #define | DMA_SxCR_PFCTRL 0x00000020U |
| #define | DMA_SxCR_TCIE 0x00000010U |
| #define | DMA_SxCR_HTIE 0x00000008U |
| #define | DMA_SxCR_TEIE 0x00000004U |
| #define | DMA_SxCR_DMEIE 0x00000002U |
| #define | DMA_SxCR_EN 0x00000001U |
| #define | DMA_SxCR_ACK 0x00100000U |
| #define | DMA_SxNDT 0x0000FFFFU |
| #define | DMA_SxNDT_0 0x00000001U |
| #define | DMA_SxNDT_1 0x00000002U |
| #define | DMA_SxNDT_2 0x00000004U |
| #define | DMA_SxNDT_3 0x00000008U |
| #define | DMA_SxNDT_4 0x00000010U |
| #define | DMA_SxNDT_5 0x00000020U |
| #define | DMA_SxNDT_6 0x00000040U |
| #define | DMA_SxNDT_7 0x00000080U |
| #define | DMA_SxNDT_8 0x00000100U |
| #define | DMA_SxNDT_9 0x00000200U |
| #define | DMA_SxNDT_10 0x00000400U |
| #define | DMA_SxNDT_11 0x00000800U |
| #define | DMA_SxNDT_12 0x00001000U |
| #define | DMA_SxNDT_13 0x00002000U |
| #define | DMA_SxNDT_14 0x00004000U |
| #define | DMA_SxNDT_15 0x00008000U |
| #define | DMA_SxFCR_FEIE 0x00000080U |
| #define | DMA_SxFCR_FS 0x00000038U |
| #define | DMA_SxFCR_FS_0 0x00000008U |
| #define | DMA_SxFCR_FS_1 0x00000010U |
| #define | DMA_SxFCR_FS_2 0x00000020U |
| #define | DMA_SxFCR_DMDIS 0x00000004U |
| #define | DMA_SxFCR_FTH 0x00000003U |
| #define | DMA_SxFCR_FTH_0 0x00000001U |
| #define | DMA_SxFCR_FTH_1 0x00000002U |
| #define | DMA_LISR_TCIF3 0x08000000U |
| #define | DMA_LISR_HTIF3 0x04000000U |
| #define | DMA_LISR_TEIF3 0x02000000U |
| #define | DMA_LISR_DMEIF3 0x01000000U |
| #define | DMA_LISR_FEIF3 0x00400000U |
| #define | DMA_LISR_TCIF2 0x00200000U |
| #define | DMA_LISR_HTIF2 0x00100000U |
| #define | DMA_LISR_TEIF2 0x00080000U |
| #define | DMA_LISR_DMEIF2 0x00040000U |
| #define | DMA_LISR_FEIF2 0x00010000U |
| #define | DMA_LISR_TCIF1 0x00000800U |
| #define | DMA_LISR_HTIF1 0x00000400U |
| #define | DMA_LISR_TEIF1 0x00000200U |
| #define | DMA_LISR_DMEIF1 0x00000100U |
| #define | DMA_LISR_FEIF1 0x00000040U |
| #define | DMA_LISR_TCIF0 0x00000020U |
| #define | DMA_LISR_HTIF0 0x00000010U |
| #define | DMA_LISR_TEIF0 0x00000008U |
| #define | DMA_LISR_DMEIF0 0x00000004U |
| #define | DMA_LISR_FEIF0 0x00000001U |
| #define | DMA_HISR_TCIF7 0x08000000U |
| #define | DMA_HISR_HTIF7 0x04000000U |
| #define | DMA_HISR_TEIF7 0x02000000U |
| #define | DMA_HISR_DMEIF7 0x01000000U |
| #define | DMA_HISR_FEIF7 0x00400000U |
| #define | DMA_HISR_TCIF6 0x00200000U |
| #define | DMA_HISR_HTIF6 0x00100000U |
| #define | DMA_HISR_TEIF6 0x00080000U |
| #define | DMA_HISR_DMEIF6 0x00040000U |
| #define | DMA_HISR_FEIF6 0x00010000U |
| #define | DMA_HISR_TCIF5 0x00000800U |
| #define | DMA_HISR_HTIF5 0x00000400U |
| #define | DMA_HISR_TEIF5 0x00000200U |
| #define | DMA_HISR_DMEIF5 0x00000100U |
| #define | DMA_HISR_FEIF5 0x00000040U |
| #define | DMA_HISR_TCIF4 0x00000020U |
| #define | DMA_HISR_HTIF4 0x00000010U |
| #define | DMA_HISR_TEIF4 0x00000008U |
| #define | DMA_HISR_DMEIF4 0x00000004U |
| #define | DMA_HISR_FEIF4 0x00000001U |
| #define | DMA_LIFCR_CTCIF3 0x08000000U |
| #define | DMA_LIFCR_CHTIF3 0x04000000U |
| #define | DMA_LIFCR_CTEIF3 0x02000000U |
| #define | DMA_LIFCR_CDMEIF3 0x01000000U |
| #define | DMA_LIFCR_CFEIF3 0x00400000U |
| #define | DMA_LIFCR_CTCIF2 0x00200000U |
| #define | DMA_LIFCR_CHTIF2 0x00100000U |
| #define | DMA_LIFCR_CTEIF2 0x00080000U |
| #define | DMA_LIFCR_CDMEIF2 0x00040000U |
| #define | DMA_LIFCR_CFEIF2 0x00010000U |
| #define | DMA_LIFCR_CTCIF1 0x00000800U |
| #define | DMA_LIFCR_CHTIF1 0x00000400U |
| #define | DMA_LIFCR_CTEIF1 0x00000200U |
| #define | DMA_LIFCR_CDMEIF1 0x00000100U |
| #define | DMA_LIFCR_CFEIF1 0x00000040U |
| #define | DMA_LIFCR_CTCIF0 0x00000020U |
| #define | DMA_LIFCR_CHTIF0 0x00000010U |
| #define | DMA_LIFCR_CTEIF0 0x00000008U |
| #define | DMA_LIFCR_CDMEIF0 0x00000004U |
| #define | DMA_LIFCR_CFEIF0 0x00000001U |
| #define | DMA_HIFCR_CTCIF7 0x08000000U |
| #define | DMA_HIFCR_CHTIF7 0x04000000U |
| #define | DMA_HIFCR_CTEIF7 0x02000000U |
| #define | DMA_HIFCR_CDMEIF7 0x01000000U |
| #define | DMA_HIFCR_CFEIF7 0x00400000U |
| #define | DMA_HIFCR_CTCIF6 0x00200000U |
| #define | DMA_HIFCR_CHTIF6 0x00100000U |
| #define | DMA_HIFCR_CTEIF6 0x00080000U |
| #define | DMA_HIFCR_CDMEIF6 0x00040000U |
| #define | DMA_HIFCR_CFEIF6 0x00010000U |
| #define | DMA_HIFCR_CTCIF5 0x00000800U |
| #define | DMA_HIFCR_CHTIF5 0x00000400U |
| #define | DMA_HIFCR_CTEIF5 0x00000200U |
| #define | DMA_HIFCR_CDMEIF5 0x00000100U |
| #define | DMA_HIFCR_CFEIF5 0x00000040U |
| #define | DMA_HIFCR_CTCIF4 0x00000020U |
| #define | DMA_HIFCR_CHTIF4 0x00000010U |
| #define | DMA_HIFCR_CTEIF4 0x00000008U |
| #define | DMA_HIFCR_CDMEIF4 0x00000004U |
| #define | DMA_HIFCR_CFEIF4 0x00000001U |
| #define | EXTI_IMR_MR0 0x00000001U |
| #define | EXTI_IMR_MR1 0x00000002U |
| #define | EXTI_IMR_MR2 0x00000004U |
| #define | EXTI_IMR_MR3 0x00000008U |
| #define | EXTI_IMR_MR4 0x00000010U |
| #define | EXTI_IMR_MR5 0x00000020U |
| #define | EXTI_IMR_MR6 0x00000040U |
| #define | EXTI_IMR_MR7 0x00000080U |
| #define | EXTI_IMR_MR8 0x00000100U |
| #define | EXTI_IMR_MR9 0x00000200U |
| #define | EXTI_IMR_MR10 0x00000400U |
| #define | EXTI_IMR_MR11 0x00000800U |
| #define | EXTI_IMR_MR12 0x00001000U |
| #define | EXTI_IMR_MR13 0x00002000U |
| #define | EXTI_IMR_MR14 0x00004000U |
| #define | EXTI_IMR_MR15 0x00008000U |
| #define | EXTI_IMR_MR16 0x00010000U |
| #define | EXTI_IMR_MR17 0x00020000U |
| #define | EXTI_IMR_MR18 0x00040000U |
| #define | EXTI_IMR_MR19 0x00080000U |
| #define | EXTI_IMR_MR20 0x00100000U |
| #define | EXTI_IMR_MR21 0x00200000U |
| #define | EXTI_IMR_MR22 0x00400000U |
| #define | EXTI_EMR_MR0 0x00000001U |
| #define | EXTI_EMR_MR1 0x00000002U |
| #define | EXTI_EMR_MR2 0x00000004U |
| #define | EXTI_EMR_MR3 0x00000008U |
| #define | EXTI_EMR_MR4 0x00000010U |
| #define | EXTI_EMR_MR5 0x00000020U |
| #define | EXTI_EMR_MR6 0x00000040U |
| #define | EXTI_EMR_MR7 0x00000080U |
| #define | EXTI_EMR_MR8 0x00000100U |
| #define | EXTI_EMR_MR9 0x00000200U |
| #define | EXTI_EMR_MR10 0x00000400U |
| #define | EXTI_EMR_MR11 0x00000800U |
| #define | EXTI_EMR_MR12 0x00001000U |
| #define | EXTI_EMR_MR13 0x00002000U |
| #define | EXTI_EMR_MR14 0x00004000U |
| #define | EXTI_EMR_MR15 0x00008000U |
| #define | EXTI_EMR_MR16 0x00010000U |
| #define | EXTI_EMR_MR17 0x00020000U |
| #define | EXTI_EMR_MR18 0x00040000U |
| #define | EXTI_EMR_MR19 0x00080000U |
| #define | EXTI_EMR_MR20 0x00100000U |
| #define | EXTI_EMR_MR21 0x00200000U |
| #define | EXTI_EMR_MR22 0x00400000U |
| #define | EXTI_RTSR_TR0 0x00000001U |
| #define | EXTI_RTSR_TR1 0x00000002U |
| #define | EXTI_RTSR_TR2 0x00000004U |
| #define | EXTI_RTSR_TR3 0x00000008U |
| #define | EXTI_RTSR_TR4 0x00000010U |
| #define | EXTI_RTSR_TR5 0x00000020U |
| #define | EXTI_RTSR_TR6 0x00000040U |
| #define | EXTI_RTSR_TR7 0x00000080U |
| #define | EXTI_RTSR_TR8 0x00000100U |
| #define | EXTI_RTSR_TR9 0x00000200U |
| #define | EXTI_RTSR_TR10 0x00000400U |
| #define | EXTI_RTSR_TR11 0x00000800U |
| #define | EXTI_RTSR_TR12 0x00001000U |
| #define | EXTI_RTSR_TR13 0x00002000U |
| #define | EXTI_RTSR_TR14 0x00004000U |
| #define | EXTI_RTSR_TR15 0x00008000U |
| #define | EXTI_RTSR_TR16 0x00010000U |
| #define | EXTI_RTSR_TR17 0x00020000U |
| #define | EXTI_RTSR_TR18 0x00040000U |
| #define | EXTI_RTSR_TR19 0x00080000U |
| #define | EXTI_RTSR_TR20 0x00100000U |
| #define | EXTI_RTSR_TR21 0x00200000U |
| #define | EXTI_RTSR_TR22 0x00400000U |
| #define | EXTI_FTSR_TR0 0x00000001U |
| #define | EXTI_FTSR_TR1 0x00000002U |
| #define | EXTI_FTSR_TR2 0x00000004U |
| #define | EXTI_FTSR_TR3 0x00000008U |
| #define | EXTI_FTSR_TR4 0x00000010U |
| #define | EXTI_FTSR_TR5 0x00000020U |
| #define | EXTI_FTSR_TR6 0x00000040U |
| #define | EXTI_FTSR_TR7 0x00000080U |
| #define | EXTI_FTSR_TR8 0x00000100U |
| #define | EXTI_FTSR_TR9 0x00000200U |
| #define | EXTI_FTSR_TR10 0x00000400U |
| #define | EXTI_FTSR_TR11 0x00000800U |
| #define | EXTI_FTSR_TR12 0x00001000U |
| #define | EXTI_FTSR_TR13 0x00002000U |
| #define | EXTI_FTSR_TR14 0x00004000U |
| #define | EXTI_FTSR_TR15 0x00008000U |
| #define | EXTI_FTSR_TR16 0x00010000U |
| #define | EXTI_FTSR_TR17 0x00020000U |
| #define | EXTI_FTSR_TR18 0x00040000U |
| #define | EXTI_FTSR_TR19 0x00080000U |
| #define | EXTI_FTSR_TR20 0x00100000U |
| #define | EXTI_FTSR_TR21 0x00200000U |
| #define | EXTI_FTSR_TR22 0x00400000U |
| #define | EXTI_SWIER_SWIER0 0x00000001U |
| #define | EXTI_SWIER_SWIER1 0x00000002U |
| #define | EXTI_SWIER_SWIER2 0x00000004U |
| #define | EXTI_SWIER_SWIER3 0x00000008U |
| #define | EXTI_SWIER_SWIER4 0x00000010U |
| #define | EXTI_SWIER_SWIER5 0x00000020U |
| #define | EXTI_SWIER_SWIER6 0x00000040U |
| #define | EXTI_SWIER_SWIER7 0x00000080U |
| #define | EXTI_SWIER_SWIER8 0x00000100U |
| #define | EXTI_SWIER_SWIER9 0x00000200U |
| #define | EXTI_SWIER_SWIER10 0x00000400U |
| #define | EXTI_SWIER_SWIER11 0x00000800U |
| #define | EXTI_SWIER_SWIER12 0x00001000U |
| #define | EXTI_SWIER_SWIER13 0x00002000U |
| #define | EXTI_SWIER_SWIER14 0x00004000U |
| #define | EXTI_SWIER_SWIER15 0x00008000U |
| #define | EXTI_SWIER_SWIER16 0x00010000U |
| #define | EXTI_SWIER_SWIER17 0x00020000U |
| #define | EXTI_SWIER_SWIER18 0x00040000U |
| #define | EXTI_SWIER_SWIER19 0x00080000U |
| #define | EXTI_SWIER_SWIER20 0x00100000U |
| #define | EXTI_SWIER_SWIER21 0x00200000U |
| #define | EXTI_SWIER_SWIER22 0x00400000U |
| #define | EXTI_PR_PR0 0x00000001U |
| #define | EXTI_PR_PR1 0x00000002U |
| #define | EXTI_PR_PR2 0x00000004U |
| #define | EXTI_PR_PR3 0x00000008U |
| #define | EXTI_PR_PR4 0x00000010U |
| #define | EXTI_PR_PR5 0x00000020U |
| #define | EXTI_PR_PR6 0x00000040U |
| #define | EXTI_PR_PR7 0x00000080U |
| #define | EXTI_PR_PR8 0x00000100U |
| #define | EXTI_PR_PR9 0x00000200U |
| #define | EXTI_PR_PR10 0x00000400U |
| #define | EXTI_PR_PR11 0x00000800U |
| #define | EXTI_PR_PR12 0x00001000U |
| #define | EXTI_PR_PR13 0x00002000U |
| #define | EXTI_PR_PR14 0x00004000U |
| #define | EXTI_PR_PR15 0x00008000U |
| #define | EXTI_PR_PR16 0x00010000U |
| #define | EXTI_PR_PR17 0x00020000U |
| #define | EXTI_PR_PR18 0x00040000U |
| #define | EXTI_PR_PR19 0x00080000U |
| #define | EXTI_PR_PR20 0x00100000U |
| #define | EXTI_PR_PR21 0x00200000U |
| #define | EXTI_PR_PR22 0x00400000U |
| #define | FLASH_ACR_LATENCY 0x0000000FU |
| #define | FLASH_ACR_LATENCY_0WS 0x00000000U |
| #define | FLASH_ACR_LATENCY_1WS 0x00000001U |
| #define | FLASH_ACR_LATENCY_2WS 0x00000002U |
| #define | FLASH_ACR_LATENCY_3WS 0x00000003U |
| #define | FLASH_ACR_LATENCY_4WS 0x00000004U |
| #define | FLASH_ACR_LATENCY_5WS 0x00000005U |
| #define | FLASH_ACR_LATENCY_6WS 0x00000006U |
| #define | FLASH_ACR_LATENCY_7WS 0x00000007U |
| #define | FLASH_ACR_PRFTEN 0x00000100U |
| #define | FLASH_ACR_ICEN 0x00000200U |
| #define | FLASH_ACR_DCEN 0x00000400U |
| #define | FLASH_ACR_ICRST 0x00000800U |
| #define | FLASH_ACR_DCRST 0x00001000U |
| #define | FLASH_ACR_BYTE0_ADDRESS 0x40023C00U |
| #define | FLASH_ACR_BYTE2_ADDRESS 0x40023C03U |
| #define | FLASH_SR_EOP 0x00000001U |
| #define | FLASH_SR_SOP 0x00000002U |
| #define | FLASH_SR_WRPERR 0x00000010U |
| #define | FLASH_SR_PGAERR 0x00000020U |
| #define | FLASH_SR_PGPERR 0x00000040U |
| #define | FLASH_SR_PGSERR 0x00000080U |
| #define | FLASH_SR_BSY 0x00010000U |
| #define | FLASH_CR_PG 0x00000001U |
| #define | FLASH_CR_SER 0x00000002U |
| #define | FLASH_CR_MER 0x00000004U |
| #define | FLASH_CR_SNB 0x000000F8U |
| #define | FLASH_CR_SNB_0 0x00000008U |
| #define | FLASH_CR_SNB_1 0x00000010U |
| #define | FLASH_CR_SNB_2 0x00000020U |
| #define | FLASH_CR_SNB_3 0x00000040U |
| #define | FLASH_CR_SNB_4 0x00000080U |
| #define | FLASH_CR_PSIZE 0x00000300U |
| #define | FLASH_CR_PSIZE_0 0x00000100U |
| #define | FLASH_CR_PSIZE_1 0x00000200U |
| #define | FLASH_CR_STRT 0x00010000U |
| #define | FLASH_CR_EOPIE 0x01000000U |
| #define | FLASH_CR_LOCK 0x80000000U |
| #define | FLASH_OPTCR_OPTLOCK 0x00000001U |
| #define | FLASH_OPTCR_OPTSTRT 0x00000002U |
| #define | FLASH_OPTCR_BOR_LEV_0 0x00000004U |
| #define | FLASH_OPTCR_BOR_LEV_1 0x00000008U |
| #define | FLASH_OPTCR_BOR_LEV 0x0000000CU |
| #define | FLASH_OPTCR_WDG_SW 0x00000020U |
| #define | FLASH_OPTCR_nRST_STOP 0x00000040U |
| #define | FLASH_OPTCR_nRST_STDBY 0x00000080U |
| #define | FLASH_OPTCR_RDP 0x0000FF00U |
| #define | FLASH_OPTCR_RDP_0 0x00000100U |
| #define | FLASH_OPTCR_RDP_1 0x00000200U |
| #define | FLASH_OPTCR_RDP_2 0x00000400U |
| #define | FLASH_OPTCR_RDP_3 0x00000800U |
| #define | FLASH_OPTCR_RDP_4 0x00001000U |
| #define | FLASH_OPTCR_RDP_5 0x00002000U |
| #define | FLASH_OPTCR_RDP_6 0x00004000U |
| #define | FLASH_OPTCR_RDP_7 0x00008000U |
| #define | FLASH_OPTCR_nWRP 0x0FFF0000U |
| #define | FLASH_OPTCR_nWRP_0 0x00010000U |
| #define | FLASH_OPTCR_nWRP_1 0x00020000U |
| #define | FLASH_OPTCR_nWRP_2 0x00040000U |
| #define | FLASH_OPTCR_nWRP_3 0x00080000U |
| #define | FLASH_OPTCR_nWRP_4 0x00100000U |
| #define | FLASH_OPTCR_nWRP_5 0x00200000U |
| #define | FLASH_OPTCR_nWRP_6 0x00400000U |
| #define | FLASH_OPTCR_nWRP_7 0x00800000U |
| #define | FLASH_OPTCR_nWRP_8 0x01000000U |
| #define | FLASH_OPTCR_nWRP_9 0x02000000U |
| #define | FLASH_OPTCR_nWRP_10 0x04000000U |
| #define | FLASH_OPTCR_nWRP_11 0x08000000U |
| #define | FLASH_OPTCR1_nWRP 0x0FFF0000U |
| #define | FLASH_OPTCR1_nWRP_0 0x00010000U |
| #define | FLASH_OPTCR1_nWRP_1 0x00020000U |
| #define | FLASH_OPTCR1_nWRP_2 0x00040000U |
| #define | FLASH_OPTCR1_nWRP_3 0x00080000U |
| #define | FLASH_OPTCR1_nWRP_4 0x00100000U |
| #define | FLASH_OPTCR1_nWRP_5 0x00200000U |
| #define | FLASH_OPTCR1_nWRP_6 0x00400000U |
| #define | FLASH_OPTCR1_nWRP_7 0x00800000U |
| #define | FLASH_OPTCR1_nWRP_8 0x01000000U |
| #define | FLASH_OPTCR1_nWRP_9 0x02000000U |
| #define | FLASH_OPTCR1_nWRP_10 0x04000000U |
| #define | FLASH_OPTCR1_nWRP_11 0x08000000U |
| #define | FSMC_BCR1_MBKEN 0x00000001U |
| #define | FSMC_BCR1_MUXEN 0x00000002U |
| #define | FSMC_BCR1_MTYP 0x0000000CU |
| #define | FSMC_BCR1_MTYP_0 0x00000004U |
| #define | FSMC_BCR1_MTYP_1 0x00000008U |
| #define | FSMC_BCR1_MWID 0x00000030U |
| #define | FSMC_BCR1_MWID_0 0x00000010U |
| #define | FSMC_BCR1_MWID_1 0x00000020U |
| #define | FSMC_BCR1_FACCEN 0x00000040U |
| #define | FSMC_BCR1_BURSTEN 0x00000100U |
| #define | FSMC_BCR1_WAITPOL 0x00000200U |
| #define | FSMC_BCR1_WRAPMOD 0x00000400U |
| #define | FSMC_BCR1_WAITCFG 0x00000800U |
| #define | FSMC_BCR1_WREN 0x00001000U |
| #define | FSMC_BCR1_WAITEN 0x00002000U |
| #define | FSMC_BCR1_EXTMOD 0x00004000U |
| #define | FSMC_BCR1_ASYNCWAIT 0x00008000U |
| #define | FSMC_BCR1_CPSIZE 0x00070000U |
| #define | FSMC_BCR1_CPSIZE_0 0x00010000U |
| #define | FSMC_BCR1_CPSIZE_1 0x00020000U |
| #define | FSMC_BCR1_CPSIZE_2 0x00040000U |
| #define | FSMC_BCR1_CBURSTRW 0x00080000U |
| #define | FSMC_BCR2_MBKEN 0x00000001U |
| #define | FSMC_BCR2_MUXEN 0x00000002U |
| #define | FSMC_BCR2_MTYP 0x0000000CU |
| #define | FSMC_BCR2_MTYP_0 0x00000004U |
| #define | FSMC_BCR2_MTYP_1 0x00000008U |
| #define | FSMC_BCR2_MWID 0x00000030U |
| #define | FSMC_BCR2_MWID_0 0x00000010U |
| #define | FSMC_BCR2_MWID_1 0x00000020U |
| #define | FSMC_BCR2_FACCEN 0x00000040U |
| #define | FSMC_BCR2_BURSTEN 0x00000100U |
| #define | FSMC_BCR2_WAITPOL 0x00000200U |
| #define | FSMC_BCR2_WRAPMOD 0x00000400U |
| #define | FSMC_BCR2_WAITCFG 0x00000800U |
| #define | FSMC_BCR2_WREN 0x00001000U |
| #define | FSMC_BCR2_WAITEN 0x00002000U |
| #define | FSMC_BCR2_EXTMOD 0x00004000U |
| #define | FSMC_BCR2_ASYNCWAIT 0x00008000U |
| #define | FSMC_BCR2_CPSIZE 0x00070000U |
| #define | FSMC_BCR2_CPSIZE_0 0x00010000U |
| #define | FSMC_BCR2_CPSIZE_1 0x00020000U |
| #define | FSMC_BCR2_CPSIZE_2 0x00040000U |
| #define | FSMC_BCR2_CBURSTRW 0x00080000U |
| #define | FSMC_BCR3_MBKEN 0x00000001U |
| #define | FSMC_BCR3_MUXEN 0x00000002U |
| #define | FSMC_BCR3_MTYP 0x0000000CU |
| #define | FSMC_BCR3_MTYP_0 0x00000004U |
| #define | FSMC_BCR3_MTYP_1 0x00000008U |
| #define | FSMC_BCR3_MWID 0x00000030U |
| #define | FSMC_BCR3_MWID_0 0x00000010U |
| #define | FSMC_BCR3_MWID_1 0x00000020U |
| #define | FSMC_BCR3_FACCEN 0x00000040U |
| #define | FSMC_BCR3_BURSTEN 0x00000100U |
| #define | FSMC_BCR3_WAITPOL 0x00000200U |
| #define | FSMC_BCR3_WRAPMOD 0x00000400U |
| #define | FSMC_BCR3_WAITCFG 0x00000800U |
| #define | FSMC_BCR3_WREN 0x00001000U |
| #define | FSMC_BCR3_WAITEN 0x00002000U |
| #define | FSMC_BCR3_EXTMOD 0x00004000U |
| #define | FSMC_BCR3_ASYNCWAIT 0x00008000U |
| #define | FSMC_BCR3_CPSIZE 0x00070000U |
| #define | FSMC_BCR3_CPSIZE_0 0x00010000U |
| #define | FSMC_BCR3_CPSIZE_1 0x00020000U |
| #define | FSMC_BCR3_CPSIZE_2 0x00040000U |
| #define | FSMC_BCR3_CBURSTRW 0x00080000U |
| #define | FSMC_BCR4_MBKEN 0x00000001U |
| #define | FSMC_BCR4_MUXEN 0x00000002U |
| #define | FSMC_BCR4_MTYP 0x0000000CU |
| #define | FSMC_BCR4_MTYP_0 0x00000004U |
| #define | FSMC_BCR4_MTYP_1 0x00000008U |
| #define | FSMC_BCR4_MWID 0x00000030U |
| #define | FSMC_BCR4_MWID_0 0x00000010U |
| #define | FSMC_BCR4_MWID_1 0x00000020U |
| #define | FSMC_BCR4_FACCEN 0x00000040U |
| #define | FSMC_BCR4_BURSTEN 0x00000100U |
| #define | FSMC_BCR4_WAITPOL 0x00000200U |
| #define | FSMC_BCR4_WRAPMOD 0x00000400U |
| #define | FSMC_BCR4_WAITCFG 0x00000800U |
| #define | FSMC_BCR4_WREN 0x00001000U |
| #define | FSMC_BCR4_WAITEN 0x00002000U |
| #define | FSMC_BCR4_EXTMOD 0x00004000U |
| #define | FSMC_BCR4_ASYNCWAIT 0x00008000U |
| #define | FSMC_BCR4_CPSIZE 0x00070000U |
| #define | FSMC_BCR4_CPSIZE_0 0x00010000U |
| #define | FSMC_BCR4_CPSIZE_1 0x00020000U |
| #define | FSMC_BCR4_CPSIZE_2 0x00040000U |
| #define | FSMC_BCR4_CBURSTRW 0x00080000U |
| #define | FSMC_BTR1_ADDSET 0x0000000FU |
| #define | FSMC_BTR1_ADDSET_0 0x00000001U |
| #define | FSMC_BTR1_ADDSET_1 0x00000002U |
| #define | FSMC_BTR1_ADDSET_2 0x00000004U |
| #define | FSMC_BTR1_ADDSET_3 0x00000008U |
| #define | FSMC_BTR1_ADDHLD 0x000000F0U |
| #define | FSMC_BTR1_ADDHLD_0 0x00000010U |
| #define | FSMC_BTR1_ADDHLD_1 0x00000020U |
| #define | FSMC_BTR1_ADDHLD_2 0x00000040U |
| #define | FSMC_BTR1_ADDHLD_3 0x00000080U |
| #define | FSMC_BTR1_DATAST 0x0000FF00U |
| #define | FSMC_BTR1_DATAST_0 0x00000100U |
| #define | FSMC_BTR1_DATAST_1 0x00000200U |
| #define | FSMC_BTR1_DATAST_2 0x00000400U |
| #define | FSMC_BTR1_DATAST_3 0x00000800U |
| #define | FSMC_BTR1_DATAST_4 0x00001000U |
| #define | FSMC_BTR1_DATAST_5 0x00002000U |
| #define | FSMC_BTR1_DATAST_6 0x00004000U |
| #define | FSMC_BTR1_DATAST_7 0x00008000U |
| #define | FSMC_BTR1_BUSTURN 0x000F0000U |
| #define | FSMC_BTR1_BUSTURN_0 0x00010000U |
| #define | FSMC_BTR1_BUSTURN_1 0x00020000U |
| #define | FSMC_BTR1_BUSTURN_2 0x00040000U |
| #define | FSMC_BTR1_BUSTURN_3 0x00080000U |
| #define | FSMC_BTR1_CLKDIV 0x00F00000U |
| #define | FSMC_BTR1_CLKDIV_0 0x00100000U |
| #define | FSMC_BTR1_CLKDIV_1 0x00200000U |
| #define | FSMC_BTR1_CLKDIV_2 0x00400000U |
| #define | FSMC_BTR1_CLKDIV_3 0x00800000U |
| #define | FSMC_BTR1_DATLAT 0x0F000000U |
| #define | FSMC_BTR1_DATLAT_0 0x01000000U |
| #define | FSMC_BTR1_DATLAT_1 0x02000000U |
| #define | FSMC_BTR1_DATLAT_2 0x04000000U |
| #define | FSMC_BTR1_DATLAT_3 0x08000000U |
| #define | FSMC_BTR1_ACCMOD 0x30000000U |
| #define | FSMC_BTR1_ACCMOD_0 0x10000000U |
| #define | FSMC_BTR1_ACCMOD_1 0x20000000U |
| #define | FSMC_BTR2_ADDSET 0x0000000FU |
| #define | FSMC_BTR2_ADDSET_0 0x00000001U |
| #define | FSMC_BTR2_ADDSET_1 0x00000002U |
| #define | FSMC_BTR2_ADDSET_2 0x00000004U |
| #define | FSMC_BTR2_ADDSET_3 0x00000008U |
| #define | FSMC_BTR2_ADDHLD 0x000000F0U |
| #define | FSMC_BTR2_ADDHLD_0 0x00000010U |
| #define | FSMC_BTR2_ADDHLD_1 0x00000020U |
| #define | FSMC_BTR2_ADDHLD_2 0x00000040U |
| #define | FSMC_BTR2_ADDHLD_3 0x00000080U |
| #define | FSMC_BTR2_DATAST 0x0000FF00U |
| #define | FSMC_BTR2_DATAST_0 0x00000100U |
| #define | FSMC_BTR2_DATAST_1 0x00000200U |
| #define | FSMC_BTR2_DATAST_2 0x00000400U |
| #define | FSMC_BTR2_DATAST_3 0x00000800U |
| #define | FSMC_BTR2_DATAST_4 0x00001000U |
| #define | FSMC_BTR2_DATAST_5 0x00002000U |
| #define | FSMC_BTR2_DATAST_6 0x00004000U |
| #define | FSMC_BTR2_DATAST_7 0x00008000U |
| #define | FSMC_BTR2_BUSTURN 0x000F0000U |
| #define | FSMC_BTR2_BUSTURN_0 0x00010000U |
| #define | FSMC_BTR2_BUSTURN_1 0x00020000U |
| #define | FSMC_BTR2_BUSTURN_2 0x00040000U |
| #define | FSMC_BTR2_BUSTURN_3 0x00080000U |
| #define | FSMC_BTR2_CLKDIV 0x00F00000U |
| #define | FSMC_BTR2_CLKDIV_0 0x00100000U |
| #define | FSMC_BTR2_CLKDIV_1 0x00200000U |
| #define | FSMC_BTR2_CLKDIV_2 0x00400000U |
| #define | FSMC_BTR2_CLKDIV_3 0x00800000U |
| #define | FSMC_BTR2_DATLAT 0x0F000000U |
| #define | FSMC_BTR2_DATLAT_0 0x01000000U |
| #define | FSMC_BTR2_DATLAT_1 0x02000000U |
| #define | FSMC_BTR2_DATLAT_2 0x04000000U |
| #define | FSMC_BTR2_DATLAT_3 0x08000000U |
| #define | FSMC_BTR2_ACCMOD 0x30000000U |
| #define | FSMC_BTR2_ACCMOD_0 0x10000000U |
| #define | FSMC_BTR2_ACCMOD_1 0x20000000U |
| #define | FSMC_BTR3_ADDSET 0x0000000FU |
| #define | FSMC_BTR3_ADDSET_0 0x00000001U |
| #define | FSMC_BTR3_ADDSET_1 0x00000002U |
| #define | FSMC_BTR3_ADDSET_2 0x00000004U |
| #define | FSMC_BTR3_ADDSET_3 0x00000008U |
| #define | FSMC_BTR3_ADDHLD 0x000000F0U |
| #define | FSMC_BTR3_ADDHLD_0 0x00000010U |
| #define | FSMC_BTR3_ADDHLD_1 0x00000020U |
| #define | FSMC_BTR3_ADDHLD_2 0x00000040U |
| #define | FSMC_BTR3_ADDHLD_3 0x00000080U |
| #define | FSMC_BTR3_DATAST 0x0000FF00U |
| #define | FSMC_BTR3_DATAST_0 0x00000100U |
| #define | FSMC_BTR3_DATAST_1 0x00000200U |
| #define | FSMC_BTR3_DATAST_2 0x00000400U |
| #define | FSMC_BTR3_DATAST_3 0x00000800U |
| #define | FSMC_BTR3_DATAST_4 0x00001000U |
| #define | FSMC_BTR3_DATAST_5 0x00002000U |
| #define | FSMC_BTR3_DATAST_6 0x00004000U |
| #define | FSMC_BTR3_DATAST_7 0x00008000U |
| #define | FSMC_BTR3_BUSTURN 0x000F0000U |
| #define | FSMC_BTR3_BUSTURN_0 0x00010000U |
| #define | FSMC_BTR3_BUSTURN_1 0x00020000U |
| #define | FSMC_BTR3_BUSTURN_2 0x00040000U |
| #define | FSMC_BTR3_BUSTURN_3 0x00080000U |
| #define | FSMC_BTR3_CLKDIV 0x00F00000U |
| #define | FSMC_BTR3_CLKDIV_0 0x00100000U |
| #define | FSMC_BTR3_CLKDIV_1 0x00200000U |
| #define | FSMC_BTR3_CLKDIV_2 0x00400000U |
| #define | FSMC_BTR3_CLKDIV_3 0x00800000U |
| #define | FSMC_BTR3_DATLAT 0x0F000000U |
| #define | FSMC_BTR3_DATLAT_0 0x01000000U |
| #define | FSMC_BTR3_DATLAT_1 0x02000000U |
| #define | FSMC_BTR3_DATLAT_2 0x04000000U |
| #define | FSMC_BTR3_DATLAT_3 0x08000000U |
| #define | FSMC_BTR3_ACCMOD 0x30000000U |
| #define | FSMC_BTR3_ACCMOD_0 0x10000000U |
| #define | FSMC_BTR3_ACCMOD_1 0x20000000U |
| #define | FSMC_BTR4_ADDSET 0x0000000FU |
| #define | FSMC_BTR4_ADDSET_0 0x00000001U |
| #define | FSMC_BTR4_ADDSET_1 0x00000002U |
| #define | FSMC_BTR4_ADDSET_2 0x00000004U |
| #define | FSMC_BTR4_ADDSET_3 0x00000008U |
| #define | FSMC_BTR4_ADDHLD 0x000000F0U |
| #define | FSMC_BTR4_ADDHLD_0 0x00000010U |
| #define | FSMC_BTR4_ADDHLD_1 0x00000020U |
| #define | FSMC_BTR4_ADDHLD_2 0x00000040U |
| #define | FSMC_BTR4_ADDHLD_3 0x00000080U |
| #define | FSMC_BTR4_DATAST 0x0000FF00U |
| #define | FSMC_BTR4_DATAST_0 0x00000100U |
| #define | FSMC_BTR4_DATAST_1 0x00000200U |
| #define | FSMC_BTR4_DATAST_2 0x00000400U |
| #define | FSMC_BTR4_DATAST_3 0x00000800U |
| #define | FSMC_BTR4_DATAST_4 0x00001000U |
| #define | FSMC_BTR4_DATAST_5 0x00002000U |
| #define | FSMC_BTR4_DATAST_6 0x00004000U |
| #define | FSMC_BTR4_DATAST_7 0x00008000U |
| #define | FSMC_BTR4_BUSTURN 0x000F0000U |
| #define | FSMC_BTR4_BUSTURN_0 0x00010000U |
| #define | FSMC_BTR4_BUSTURN_1 0x00020000U |
| #define | FSMC_BTR4_BUSTURN_2 0x00040000U |
| #define | FSMC_BTR4_BUSTURN_3 0x00080000U |
| #define | FSMC_BTR4_CLKDIV 0x00F00000U |
| #define | FSMC_BTR4_CLKDIV_0 0x00100000U |
| #define | FSMC_BTR4_CLKDIV_1 0x00200000U |
| #define | FSMC_BTR4_CLKDIV_2 0x00400000U |
| #define | FSMC_BTR4_CLKDIV_3 0x00800000U |
| #define | FSMC_BTR4_DATLAT 0x0F000000U |
| #define | FSMC_BTR4_DATLAT_0 0x01000000U |
| #define | FSMC_BTR4_DATLAT_1 0x02000000U |
| #define | FSMC_BTR4_DATLAT_2 0x04000000U |
| #define | FSMC_BTR4_DATLAT_3 0x08000000U |
| #define | FSMC_BTR4_ACCMOD 0x30000000U |
| #define | FSMC_BTR4_ACCMOD_0 0x10000000U |
| #define | FSMC_BTR4_ACCMOD_1 0x20000000U |
| #define | FSMC_BWTR1_ADDSET 0x0000000FU |
| #define | FSMC_BWTR1_ADDSET_0 0x00000001U |
| #define | FSMC_BWTR1_ADDSET_1 0x00000002U |
| #define | FSMC_BWTR1_ADDSET_2 0x00000004U |
| #define | FSMC_BWTR1_ADDSET_3 0x00000008U |
| #define | FSMC_BWTR1_ADDHLD 0x000000F0U |
| #define | FSMC_BWTR1_ADDHLD_0 0x00000010U |
| #define | FSMC_BWTR1_ADDHLD_1 0x00000020U |
| #define | FSMC_BWTR1_ADDHLD_2 0x00000040U |
| #define | FSMC_BWTR1_ADDHLD_3 0x00000080U |
| #define | FSMC_BWTR1_DATAST 0x0000FF00U |
| #define | FSMC_BWTR1_DATAST_0 0x00000100U |
| #define | FSMC_BWTR1_DATAST_1 0x00000200U |
| #define | FSMC_BWTR1_DATAST_2 0x00000400U |
| #define | FSMC_BWTR1_DATAST_3 0x00000800U |
| #define | FSMC_BWTR1_DATAST_4 0x00001000U |
| #define | FSMC_BWTR1_DATAST_5 0x00002000U |
| #define | FSMC_BWTR1_DATAST_6 0x00004000U |
| #define | FSMC_BWTR1_DATAST_7 0x00008000U |
| #define | FSMC_BWTR1_BUSTURN 0x000F0000U |
| #define | FSMC_BWTR1_BUSTURN_0 0x00010000U |
| #define | FSMC_BWTR1_BUSTURN_1 0x00020000U |
| #define | FSMC_BWTR1_BUSTURN_2 0x00040000U |
| #define | FSMC_BWTR1_BUSTURN_3 0x00080000U |
| #define | FSMC_BWTR1_ACCMOD 0x30000000U |
| #define | FSMC_BWTR1_ACCMOD_0 0x10000000U |
| #define | FSMC_BWTR1_ACCMOD_1 0x20000000U |
| #define | FSMC_BWTR2_ADDSET 0x0000000FU |
| #define | FSMC_BWTR2_ADDSET_0 0x00000001U |
| #define | FSMC_BWTR2_ADDSET_1 0x00000002U |
| #define | FSMC_BWTR2_ADDSET_2 0x00000004U |
| #define | FSMC_BWTR2_ADDSET_3 0x00000008U |
| #define | FSMC_BWTR2_ADDHLD 0x000000F0U |
| #define | FSMC_BWTR2_ADDHLD_0 0x00000010U |
| #define | FSMC_BWTR2_ADDHLD_1 0x00000020U |
| #define | FSMC_BWTR2_ADDHLD_2 0x00000040U |
| #define | FSMC_BWTR2_ADDHLD_3 0x00000080U |
| #define | FSMC_BWTR2_DATAST 0x0000FF00U |
| #define | FSMC_BWTR2_DATAST_0 0x00000100U |
| #define | FSMC_BWTR2_DATAST_1 0x00000200U |
| #define | FSMC_BWTR2_DATAST_2 0x00000400U |
| #define | FSMC_BWTR2_DATAST_3 0x00000800U |
| #define | FSMC_BWTR2_DATAST_4 0x00001000U |
| #define | FSMC_BWTR2_DATAST_5 0x00002000U |
| #define | FSMC_BWTR2_DATAST_6 0x00004000U |
| #define | FSMC_BWTR2_DATAST_7 0x00008000U |
| #define | FSMC_BWTR2_BUSTURN 0x000F0000U |
| #define | FSMC_BWTR2_BUSTURN_0 0x00010000U |
| #define | FSMC_BWTR2_BUSTURN_1 0x00020000U |
| #define | FSMC_BWTR2_BUSTURN_2 0x00040000U |
| #define | FSMC_BWTR2_BUSTURN_3 0x00080000U |
| #define | FSMC_BWTR2_ACCMOD 0x30000000U |
| #define | FSMC_BWTR2_ACCMOD_0 0x10000000U |
| #define | FSMC_BWTR2_ACCMOD_1 0x20000000U |
| #define | FSMC_BWTR3_ADDSET 0x0000000FU |
| #define | FSMC_BWTR3_ADDSET_0 0x00000001U |
| #define | FSMC_BWTR3_ADDSET_1 0x00000002U |
| #define | FSMC_BWTR3_ADDSET_2 0x00000004U |
| #define | FSMC_BWTR3_ADDSET_3 0x00000008U |
| #define | FSMC_BWTR3_ADDHLD 0x000000F0U |
| #define | FSMC_BWTR3_ADDHLD_0 0x00000010U |
| #define | FSMC_BWTR3_ADDHLD_1 0x00000020U |
| #define | FSMC_BWTR3_ADDHLD_2 0x00000040U |
| #define | FSMC_BWTR3_ADDHLD_3 0x00000080U |
| #define | FSMC_BWTR3_DATAST 0x0000FF00U |
| #define | FSMC_BWTR3_DATAST_0 0x00000100U |
| #define | FSMC_BWTR3_DATAST_1 0x00000200U |
| #define | FSMC_BWTR3_DATAST_2 0x00000400U |
| #define | FSMC_BWTR3_DATAST_3 0x00000800U |
| #define | FSMC_BWTR3_DATAST_4 0x00001000U |
| #define | FSMC_BWTR3_DATAST_5 0x00002000U |
| #define | FSMC_BWTR3_DATAST_6 0x00004000U |
| #define | FSMC_BWTR3_DATAST_7 0x00008000U |
| #define | FSMC_BWTR3_BUSTURN 0x000F0000U |
| #define | FSMC_BWTR3_BUSTURN_0 0x00010000U |
| #define | FSMC_BWTR3_BUSTURN_1 0x00020000U |
| #define | FSMC_BWTR3_BUSTURN_2 0x00040000U |
| #define | FSMC_BWTR3_BUSTURN_3 0x00080000U |
| #define | FSMC_BWTR3_ACCMOD 0x30000000U |
| #define | FSMC_BWTR3_ACCMOD_0 0x10000000U |
| #define | FSMC_BWTR3_ACCMOD_1 0x20000000U |
| #define | FSMC_BWTR4_ADDSET 0x0000000FU |
| #define | FSMC_BWTR4_ADDSET_0 0x00000001U |
| #define | FSMC_BWTR4_ADDSET_1 0x00000002U |
| #define | FSMC_BWTR4_ADDSET_2 0x00000004U |
| #define | FSMC_BWTR4_ADDSET_3 0x00000008U |
| #define | FSMC_BWTR4_ADDHLD 0x000000F0U |
| #define | FSMC_BWTR4_ADDHLD_0 0x00000010U |
| #define | FSMC_BWTR4_ADDHLD_1 0x00000020U |
| #define | FSMC_BWTR4_ADDHLD_2 0x00000040U |
| #define | FSMC_BWTR4_ADDHLD_3 0x00000080U |
| #define | FSMC_BWTR4_DATAST 0x0000FF00U |
| #define | FSMC_BWTR4_DATAST_0 0x00000100U |
| #define | FSMC_BWTR4_DATAST_1 0x00000200U |
| #define | FSMC_BWTR4_DATAST_2 0x00000400U |
| #define | FSMC_BWTR4_DATAST_3 0x00000800U |
| #define | FSMC_BWTR4_DATAST_4 0x00001000U |
| #define | FSMC_BWTR4_DATAST_5 0x00002000U |
| #define | FSMC_BWTR4_DATAST_6 0x00004000U |
| #define | FSMC_BWTR4_DATAST_7 0x00008000U |
| #define | FSMC_BWTR4_BUSTURN 0x000F0000U |
| #define | FSMC_BWTR4_BUSTURN_0 0x00010000U |
| #define | FSMC_BWTR4_BUSTURN_1 0x00020000U |
| #define | FSMC_BWTR4_BUSTURN_2 0x00040000U |
| #define | FSMC_BWTR4_BUSTURN_3 0x00080000U |
| #define | FSMC_BWTR4_ACCMOD 0x30000000U |
| #define | FSMC_BWTR4_ACCMOD_0 0x10000000U |
| #define | FSMC_BWTR4_ACCMOD_1 0x20000000U |
| #define | FSMC_PCR2_PWAITEN 0x00000002U |
| #define | FSMC_PCR2_PBKEN 0x00000004U |
| #define | FSMC_PCR2_PTYP 0x00000008U |
| #define | FSMC_PCR2_PWID 0x00000030U |
| #define | FSMC_PCR2_PWID_0 0x00000010U |
| #define | FSMC_PCR2_PWID_1 0x00000020U |
| #define | FSMC_PCR2_ECCEN 0x00000040U |
| #define | FSMC_PCR2_TCLR 0x00001E00U |
| #define | FSMC_PCR2_TCLR_0 0x00000200U |
| #define | FSMC_PCR2_TCLR_1 0x00000400U |
| #define | FSMC_PCR2_TCLR_2 0x00000800U |
| #define | FSMC_PCR2_TCLR_3 0x00001000U |
| #define | FSMC_PCR2_TAR 0x0001E000U |
| #define | FSMC_PCR2_TAR_0 0x00002000U |
| #define | FSMC_PCR2_TAR_1 0x00004000U |
| #define | FSMC_PCR2_TAR_2 0x00008000U |
| #define | FSMC_PCR2_TAR_3 0x00010000U |
| #define | FSMC_PCR2_ECCPS 0x000E0000U |
| #define | FSMC_PCR2_ECCPS_0 0x00020000U |
| #define | FSMC_PCR2_ECCPS_1 0x00040000U |
| #define | FSMC_PCR2_ECCPS_2 0x00080000U |
| #define | FSMC_PCR3_PWAITEN 0x00000002U |
| #define | FSMC_PCR3_PBKEN 0x00000004U |
| #define | FSMC_PCR3_PTYP 0x00000008U |
| #define | FSMC_PCR3_PWID 0x00000030U |
| #define | FSMC_PCR3_PWID_0 0x00000010U |
| #define | FSMC_PCR3_PWID_1 0x00000020U |
| #define | FSMC_PCR3_ECCEN 0x00000040U |
| #define | FSMC_PCR3_TCLR 0x00001E00U |
| #define | FSMC_PCR3_TCLR_0 0x00000200U |
| #define | FSMC_PCR3_TCLR_1 0x00000400U |
| #define | FSMC_PCR3_TCLR_2 0x00000800U |
| #define | FSMC_PCR3_TCLR_3 0x00001000U |
| #define | FSMC_PCR3_TAR 0x0001E000U |
| #define | FSMC_PCR3_TAR_0 0x00002000U |
| #define | FSMC_PCR3_TAR_1 0x00004000U |
| #define | FSMC_PCR3_TAR_2 0x00008000U |
| #define | FSMC_PCR3_TAR_3 0x00010000U |
| #define | FSMC_PCR3_ECCPS 0x000E0000U |
| #define | FSMC_PCR3_ECCPS_0 0x00020000U |
| #define | FSMC_PCR3_ECCPS_1 0x00040000U |
| #define | FSMC_PCR3_ECCPS_2 0x00080000U |
| #define | FSMC_PCR4_PWAITEN 0x00000002U |
| #define | FSMC_PCR4_PBKEN 0x00000004U |
| #define | FSMC_PCR4_PTYP 0x00000008U |
| #define | FSMC_PCR4_PWID 0x00000030U |
| #define | FSMC_PCR4_PWID_0 0x00000010U |
| #define | FSMC_PCR4_PWID_1 0x00000020U |
| #define | FSMC_PCR4_ECCEN 0x00000040U |
| #define | FSMC_PCR4_TCLR 0x00001E00U |
| #define | FSMC_PCR4_TCLR_0 0x00000200U |
| #define | FSMC_PCR4_TCLR_1 0x00000400U |
| #define | FSMC_PCR4_TCLR_2 0x00000800U |
| #define | FSMC_PCR4_TCLR_3 0x00001000U |
| #define | FSMC_PCR4_TAR 0x0001E000U |
| #define | FSMC_PCR4_TAR_0 0x00002000U |
| #define | FSMC_PCR4_TAR_1 0x00004000U |
| #define | FSMC_PCR4_TAR_2 0x00008000U |
| #define | FSMC_PCR4_TAR_3 0x00010000U |
| #define | FSMC_PCR4_ECCPS 0x000E0000U |
| #define | FSMC_PCR4_ECCPS_0 0x00020000U |
| #define | FSMC_PCR4_ECCPS_1 0x00040000U |
| #define | FSMC_PCR4_ECCPS_2 0x00080000U |
| #define | FSMC_SR2_IRS 0x01U |
| #define | FSMC_SR2_ILS 0x02U |
| #define | FSMC_SR2_IFS 0x04U |
| #define | FSMC_SR2_IREN 0x08U |
| #define | FSMC_SR2_ILEN 0x10U |
| #define | FSMC_SR2_IFEN 0x20U |
| #define | FSMC_SR2_FEMPT 0x40U |
| #define | FSMC_SR3_IRS 0x01U |
| #define | FSMC_SR3_ILS 0x02U |
| #define | FSMC_SR3_IFS 0x04U |
| #define | FSMC_SR3_IREN 0x08U |
| #define | FSMC_SR3_ILEN 0x10U |
| #define | FSMC_SR3_IFEN 0x20U |
| #define | FSMC_SR3_FEMPT 0x40U |
| #define | FSMC_SR4_IRS 0x01U |
| #define | FSMC_SR4_ILS 0x02U |
| #define | FSMC_SR4_IFS 0x04U |
| #define | FSMC_SR4_IREN 0x08U |
| #define | FSMC_SR4_ILEN 0x10U |
| #define | FSMC_SR4_IFEN 0x20U |
| #define | FSMC_SR4_FEMPT 0x40U |
| #define | FSMC_PMEM2_MEMSET2 0x000000FFU |
| #define | FSMC_PMEM2_MEMSET2_0 0x00000001U |
| #define | FSMC_PMEM2_MEMSET2_1 0x00000002U |
| #define | FSMC_PMEM2_MEMSET2_2 0x00000004U |
| #define | FSMC_PMEM2_MEMSET2_3 0x00000008U |
| #define | FSMC_PMEM2_MEMSET2_4 0x00000010U |
| #define | FSMC_PMEM2_MEMSET2_5 0x00000020U |
| #define | FSMC_PMEM2_MEMSET2_6 0x00000040U |
| #define | FSMC_PMEM2_MEMSET2_7 0x00000080U |
| #define | FSMC_PMEM2_MEMWAIT2 0x0000FF00U |
| #define | FSMC_PMEM2_MEMWAIT2_0 0x00000100U |
| #define | FSMC_PMEM2_MEMWAIT2_1 0x00000200U |
| #define | FSMC_PMEM2_MEMWAIT2_2 0x00000400U |
| #define | FSMC_PMEM2_MEMWAIT2_3 0x00000800U |
| #define | FSMC_PMEM2_MEMWAIT2_4 0x00001000U |
| #define | FSMC_PMEM2_MEMWAIT2_5 0x00002000U |
| #define | FSMC_PMEM2_MEMWAIT2_6 0x00004000U |
| #define | FSMC_PMEM2_MEMWAIT2_7 0x00008000U |
| #define | FSMC_PMEM2_MEMHOLD2 0x00FF0000U |
| #define | FSMC_PMEM2_MEMHOLD2_0 0x00010000U |
| #define | FSMC_PMEM2_MEMHOLD2_1 0x00020000U |
| #define | FSMC_PMEM2_MEMHOLD2_2 0x00040000U |
| #define | FSMC_PMEM2_MEMHOLD2_3 0x00080000U |
| #define | FSMC_PMEM2_MEMHOLD2_4 0x00100000U |
| #define | FSMC_PMEM2_MEMHOLD2_5 0x00200000U |
| #define | FSMC_PMEM2_MEMHOLD2_6 0x00400000U |
| #define | FSMC_PMEM2_MEMHOLD2_7 0x00800000U |
| #define | FSMC_PMEM2_MEMHIZ2 0xFF000000U |
| #define | FSMC_PMEM2_MEMHIZ2_0 0x01000000U |
| #define | FSMC_PMEM2_MEMHIZ2_1 0x02000000U |
| #define | FSMC_PMEM2_MEMHIZ2_2 0x04000000U |
| #define | FSMC_PMEM2_MEMHIZ2_3 0x08000000U |
| #define | FSMC_PMEM2_MEMHIZ2_4 0x10000000U |
| #define | FSMC_PMEM2_MEMHIZ2_5 0x20000000U |
| #define | FSMC_PMEM2_MEMHIZ2_6 0x40000000U |
| #define | FSMC_PMEM2_MEMHIZ2_7 0x80000000U |
| #define | FSMC_PMEM3_MEMSET3 0x000000FFU |
| #define | FSMC_PMEM3_MEMSET3_0 0x00000001U |
| #define | FSMC_PMEM3_MEMSET3_1 0x00000002U |
| #define | FSMC_PMEM3_MEMSET3_2 0x00000004U |
| #define | FSMC_PMEM3_MEMSET3_3 0x00000008U |
| #define | FSMC_PMEM3_MEMSET3_4 0x00000010U |
| #define | FSMC_PMEM3_MEMSET3_5 0x00000020U |
| #define | FSMC_PMEM3_MEMSET3_6 0x00000040U |
| #define | FSMC_PMEM3_MEMSET3_7 0x00000080U |
| #define | FSMC_PMEM3_MEMWAIT3 0x0000FF00U |
| #define | FSMC_PMEM3_MEMWAIT3_0 0x00000100U |
| #define | FSMC_PMEM3_MEMWAIT3_1 0x00000200U |
| #define | FSMC_PMEM3_MEMWAIT3_2 0x00000400U |
| #define | FSMC_PMEM3_MEMWAIT3_3 0x00000800U |
| #define | FSMC_PMEM3_MEMWAIT3_4 0x00001000U |
| #define | FSMC_PMEM3_MEMWAIT3_5 0x00002000U |
| #define | FSMC_PMEM3_MEMWAIT3_6 0x00004000U |
| #define | FSMC_PMEM3_MEMWAIT3_7 0x00008000U |
| #define | FSMC_PMEM3_MEMHOLD3 0x00FF0000U |
| #define | FSMC_PMEM3_MEMHOLD3_0 0x00010000U |
| #define | FSMC_PMEM3_MEMHOLD3_1 0x00020000U |
| #define | FSMC_PMEM3_MEMHOLD3_2 0x00040000U |
| #define | FSMC_PMEM3_MEMHOLD3_3 0x00080000U |
| #define | FSMC_PMEM3_MEMHOLD3_4 0x00100000U |
| #define | FSMC_PMEM3_MEMHOLD3_5 0x00200000U |
| #define | FSMC_PMEM3_MEMHOLD3_6 0x00400000U |
| #define | FSMC_PMEM3_MEMHOLD3_7 0x00800000U |
| #define | FSMC_PMEM3_MEMHIZ3 0xFF000000U |
| #define | FSMC_PMEM3_MEMHIZ3_0 0x01000000U |
| #define | FSMC_PMEM3_MEMHIZ3_1 0x02000000U |
| #define | FSMC_PMEM3_MEMHIZ3_2 0x04000000U |
| #define | FSMC_PMEM3_MEMHIZ3_3 0x08000000U |
| #define | FSMC_PMEM3_MEMHIZ3_4 0x10000000U |
| #define | FSMC_PMEM3_MEMHIZ3_5 0x20000000U |
| #define | FSMC_PMEM3_MEMHIZ3_6 0x40000000U |
| #define | FSMC_PMEM3_MEMHIZ3_7 0x80000000U |
| #define | FSMC_PMEM4_MEMSET4 0x000000FFU |
| #define | FSMC_PMEM4_MEMSET4_0 0x00000001U |
| #define | FSMC_PMEM4_MEMSET4_1 0x00000002U |
| #define | FSMC_PMEM4_MEMSET4_2 0x00000004U |
| #define | FSMC_PMEM4_MEMSET4_3 0x00000008U |
| #define | FSMC_PMEM4_MEMSET4_4 0x00000010U |
| #define | FSMC_PMEM4_MEMSET4_5 0x00000020U |
| #define | FSMC_PMEM4_MEMSET4_6 0x00000040U |
| #define | FSMC_PMEM4_MEMSET4_7 0x00000080U |
| #define | FSMC_PMEM4_MEMWAIT4 0x0000FF00U |
| #define | FSMC_PMEM4_MEMWAIT4_0 0x00000100U |
| #define | FSMC_PMEM4_MEMWAIT4_1 0x00000200U |
| #define | FSMC_PMEM4_MEMWAIT4_2 0x00000400U |
| #define | FSMC_PMEM4_MEMWAIT4_3 0x00000800U |
| #define | FSMC_PMEM4_MEMWAIT4_4 0x00001000U |
| #define | FSMC_PMEM4_MEMWAIT4_5 0x00002000U |
| #define | FSMC_PMEM4_MEMWAIT4_6 0x00004000U |
| #define | FSMC_PMEM4_MEMWAIT4_7 0x00008000U |
| #define | FSMC_PMEM4_MEMHOLD4 0x00FF0000U |
| #define | FSMC_PMEM4_MEMHOLD4_0 0x00010000U |
| #define | FSMC_PMEM4_MEMHOLD4_1 0x00020000U |
| #define | FSMC_PMEM4_MEMHOLD4_2 0x00040000U |
| #define | FSMC_PMEM4_MEMHOLD4_3 0x00080000U |
| #define | FSMC_PMEM4_MEMHOLD4_4 0x00100000U |
| #define | FSMC_PMEM4_MEMHOLD4_5 0x00200000U |
| #define | FSMC_PMEM4_MEMHOLD4_6 0x00400000U |
| #define | FSMC_PMEM4_MEMHOLD4_7 0x00800000U |
| #define | FSMC_PMEM4_MEMHIZ4 0xFF000000U |
| #define | FSMC_PMEM4_MEMHIZ4_0 0x01000000U |
| #define | FSMC_PMEM4_MEMHIZ4_1 0x02000000U |
| #define | FSMC_PMEM4_MEMHIZ4_2 0x04000000U |
| #define | FSMC_PMEM4_MEMHIZ4_3 0x08000000U |
| #define | FSMC_PMEM4_MEMHIZ4_4 0x10000000U |
| #define | FSMC_PMEM4_MEMHIZ4_5 0x20000000U |
| #define | FSMC_PMEM4_MEMHIZ4_6 0x40000000U |
| #define | FSMC_PMEM4_MEMHIZ4_7 0x80000000U |
| #define | FSMC_PATT2_ATTSET2 0x000000FFU |
| #define | FSMC_PATT2_ATTSET2_0 0x00000001U |
| #define | FSMC_PATT2_ATTSET2_1 0x00000002U |
| #define | FSMC_PATT2_ATTSET2_2 0x00000004U |
| #define | FSMC_PATT2_ATTSET2_3 0x00000008U |
| #define | FSMC_PATT2_ATTSET2_4 0x00000010U |
| #define | FSMC_PATT2_ATTSET2_5 0x00000020U |
| #define | FSMC_PATT2_ATTSET2_6 0x00000040U |
| #define | FSMC_PATT2_ATTSET2_7 0x00000080U |
| #define | FSMC_PATT2_ATTWAIT2 0x0000FF00U |
| #define | FSMC_PATT2_ATTWAIT2_0 0x00000100U |
| #define | FSMC_PATT2_ATTWAIT2_1 0x00000200U |
| #define | FSMC_PATT2_ATTWAIT2_2 0x00000400U |
| #define | FSMC_PATT2_ATTWAIT2_3 0x00000800U |
| #define | FSMC_PATT2_ATTWAIT2_4 0x00001000U |
| #define | FSMC_PATT2_ATTWAIT2_5 0x00002000U |
| #define | FSMC_PATT2_ATTWAIT2_6 0x00004000U |
| #define | FSMC_PATT2_ATTWAIT2_7 0x00008000U |
| #define | FSMC_PATT2_ATTHOLD2 0x00FF0000U |
| #define | FSMC_PATT2_ATTHOLD2_0 0x00010000U |
| #define | FSMC_PATT2_ATTHOLD2_1 0x00020000U |
| #define | FSMC_PATT2_ATTHOLD2_2 0x00040000U |
| #define | FSMC_PATT2_ATTHOLD2_3 0x00080000U |
| #define | FSMC_PATT2_ATTHOLD2_4 0x00100000U |
| #define | FSMC_PATT2_ATTHOLD2_5 0x00200000U |
| #define | FSMC_PATT2_ATTHOLD2_6 0x00400000U |
| #define | FSMC_PATT2_ATTHOLD2_7 0x00800000U |
| #define | FSMC_PATT2_ATTHIZ2 0xFF000000U |
| #define | FSMC_PATT2_ATTHIZ2_0 0x01000000U |
| #define | FSMC_PATT2_ATTHIZ2_1 0x02000000U |
| #define | FSMC_PATT2_ATTHIZ2_2 0x04000000U |
| #define | FSMC_PATT2_ATTHIZ2_3 0x08000000U |
| #define | FSMC_PATT2_ATTHIZ2_4 0x10000000U |
| #define | FSMC_PATT2_ATTHIZ2_5 0x20000000U |
| #define | FSMC_PATT2_ATTHIZ2_6 0x40000000U |
| #define | FSMC_PATT2_ATTHIZ2_7 0x80000000U |
| #define | FSMC_PATT3_ATTSET3 0x000000FFU |
| #define | FSMC_PATT3_ATTSET3_0 0x00000001U |
| #define | FSMC_PATT3_ATTSET3_1 0x00000002U |
| #define | FSMC_PATT3_ATTSET3_2 0x00000004U |
| #define | FSMC_PATT3_ATTSET3_3 0x00000008U |
| #define | FSMC_PATT3_ATTSET3_4 0x00000010U |
| #define | FSMC_PATT3_ATTSET3_5 0x00000020U |
| #define | FSMC_PATT3_ATTSET3_6 0x00000040U |
| #define | FSMC_PATT3_ATTSET3_7 0x00000080U |
| #define | FSMC_PATT3_ATTWAIT3 0x0000FF00U |
| #define | FSMC_PATT3_ATTWAIT3_0 0x00000100U |
| #define | FSMC_PATT3_ATTWAIT3_1 0x00000200U |
| #define | FSMC_PATT3_ATTWAIT3_2 0x00000400U |
| #define | FSMC_PATT3_ATTWAIT3_3 0x00000800U |
| #define | FSMC_PATT3_ATTWAIT3_4 0x00001000U |
| #define | FSMC_PATT3_ATTWAIT3_5 0x00002000U |
| #define | FSMC_PATT3_ATTWAIT3_6 0x00004000U |
| #define | FSMC_PATT3_ATTWAIT3_7 0x00008000U |
| #define | FSMC_PATT3_ATTHOLD3 0x00FF0000U |
| #define | FSMC_PATT3_ATTHOLD3_0 0x00010000U |
| #define | FSMC_PATT3_ATTHOLD3_1 0x00020000U |
| #define | FSMC_PATT3_ATTHOLD3_2 0x00040000U |
| #define | FSMC_PATT3_ATTHOLD3_3 0x00080000U |
| #define | FSMC_PATT3_ATTHOLD3_4 0x00100000U |
| #define | FSMC_PATT3_ATTHOLD3_5 0x00200000U |
| #define | FSMC_PATT3_ATTHOLD3_6 0x00400000U |
| #define | FSMC_PATT3_ATTHOLD3_7 0x00800000U |
| #define | FSMC_PATT3_ATTHIZ3 0xFF000000U |
| #define | FSMC_PATT3_ATTHIZ3_0 0x01000000U |
| #define | FSMC_PATT3_ATTHIZ3_1 0x02000000U |
| #define | FSMC_PATT3_ATTHIZ3_2 0x04000000U |
| #define | FSMC_PATT3_ATTHIZ3_3 0x08000000U |
| #define | FSMC_PATT3_ATTHIZ3_4 0x10000000U |
| #define | FSMC_PATT3_ATTHIZ3_5 0x20000000U |
| #define | FSMC_PATT3_ATTHIZ3_6 0x40000000U |
| #define | FSMC_PATT3_ATTHIZ3_7 0x80000000U |
| #define | FSMC_PATT4_ATTSET4 0x000000FFU |
| #define | FSMC_PATT4_ATTSET4_0 0x00000001U |
| #define | FSMC_PATT4_ATTSET4_1 0x00000002U |
| #define | FSMC_PATT4_ATTSET4_2 0x00000004U |
| #define | FSMC_PATT4_ATTSET4_3 0x00000008U |
| #define | FSMC_PATT4_ATTSET4_4 0x00000010U |
| #define | FSMC_PATT4_ATTSET4_5 0x00000020U |
| #define | FSMC_PATT4_ATTSET4_6 0x00000040U |
| #define | FSMC_PATT4_ATTSET4_7 0x00000080U |
| #define | FSMC_PATT4_ATTWAIT4 0x0000FF00U |
| #define | FSMC_PATT4_ATTWAIT4_0 0x00000100U |
| #define | FSMC_PATT4_ATTWAIT4_1 0x00000200U |
| #define | FSMC_PATT4_ATTWAIT4_2 0x00000400U |
| #define | FSMC_PATT4_ATTWAIT4_3 0x00000800U |
| #define | FSMC_PATT4_ATTWAIT4_4 0x00001000U |
| #define | FSMC_PATT4_ATTWAIT4_5 0x00002000U |
| #define | FSMC_PATT4_ATTWAIT4_6 0x00004000U |
| #define | FSMC_PATT4_ATTWAIT4_7 0x00008000U |
| #define | FSMC_PATT4_ATTHOLD4 0x00FF0000U |
| #define | FSMC_PATT4_ATTHOLD4_0 0x00010000U |
| #define | FSMC_PATT4_ATTHOLD4_1 0x00020000U |
| #define | FSMC_PATT4_ATTHOLD4_2 0x00040000U |
| #define | FSMC_PATT4_ATTHOLD4_3 0x00080000U |
| #define | FSMC_PATT4_ATTHOLD4_4 0x00100000U |
| #define | FSMC_PATT4_ATTHOLD4_5 0x00200000U |
| #define | FSMC_PATT4_ATTHOLD4_6 0x00400000U |
| #define | FSMC_PATT4_ATTHOLD4_7 0x00800000U |
| #define | FSMC_PATT4_ATTHIZ4 0xFF000000U |
| #define | FSMC_PATT4_ATTHIZ4_0 0x01000000U |
| #define | FSMC_PATT4_ATTHIZ4_1 0x02000000U |
| #define | FSMC_PATT4_ATTHIZ4_2 0x04000000U |
| #define | FSMC_PATT4_ATTHIZ4_3 0x08000000U |
| #define | FSMC_PATT4_ATTHIZ4_4 0x10000000U |
| #define | FSMC_PATT4_ATTHIZ4_5 0x20000000U |
| #define | FSMC_PATT4_ATTHIZ4_6 0x40000000U |
| #define | FSMC_PATT4_ATTHIZ4_7 0x80000000U |
| #define | FSMC_PIO4_IOSET4 0x000000FFU |
| #define | FSMC_PIO4_IOSET4_0 0x00000001U |
| #define | FSMC_PIO4_IOSET4_1 0x00000002U |
| #define | FSMC_PIO4_IOSET4_2 0x00000004U |
| #define | FSMC_PIO4_IOSET4_3 0x00000008U |
| #define | FSMC_PIO4_IOSET4_4 0x00000010U |
| #define | FSMC_PIO4_IOSET4_5 0x00000020U |
| #define | FSMC_PIO4_IOSET4_6 0x00000040U |
| #define | FSMC_PIO4_IOSET4_7 0x00000080U |
| #define | FSMC_PIO4_IOWAIT4 0x0000FF00U |
| #define | FSMC_PIO4_IOWAIT4_0 0x00000100U |
| #define | FSMC_PIO4_IOWAIT4_1 0x00000200U |
| #define | FSMC_PIO4_IOWAIT4_2 0x00000400U |
| #define | FSMC_PIO4_IOWAIT4_3 0x00000800U |
| #define | FSMC_PIO4_IOWAIT4_4 0x00001000U |
| #define | FSMC_PIO4_IOWAIT4_5 0x00002000U |
| #define | FSMC_PIO4_IOWAIT4_6 0x00004000U |
| #define | FSMC_PIO4_IOWAIT4_7 0x00008000U |
| #define | FSMC_PIO4_IOHOLD4 0x00FF0000U |
| #define | FSMC_PIO4_IOHOLD4_0 0x00010000U |
| #define | FSMC_PIO4_IOHOLD4_1 0x00020000U |
| #define | FSMC_PIO4_IOHOLD4_2 0x00040000U |
| #define | FSMC_PIO4_IOHOLD4_3 0x00080000U |
| #define | FSMC_PIO4_IOHOLD4_4 0x00100000U |
| #define | FSMC_PIO4_IOHOLD4_5 0x00200000U |
| #define | FSMC_PIO4_IOHOLD4_6 0x00400000U |
| #define | FSMC_PIO4_IOHOLD4_7 0x00800000U |
| #define | FSMC_PIO4_IOHIZ4 0xFF000000U |
| #define | FSMC_PIO4_IOHIZ4_0 0x01000000U |
| #define | FSMC_PIO4_IOHIZ4_1 0x02000000U |
| #define | FSMC_PIO4_IOHIZ4_2 0x04000000U |
| #define | FSMC_PIO4_IOHIZ4_3 0x08000000U |
| #define | FSMC_PIO4_IOHIZ4_4 0x10000000U |
| #define | FSMC_PIO4_IOHIZ4_5 0x20000000U |
| #define | FSMC_PIO4_IOHIZ4_6 0x40000000U |
| #define | FSMC_PIO4_IOHIZ4_7 0x80000000U |
| #define | FSMC_ECCR2_ECC2 0xFFFFFFFFU |
| #define | FSMC_ECCR3_ECC3 0xFFFFFFFFU |
| #define | GPIO_MODER_MODER0 0x00000003U |
| #define | GPIO_MODER_MODER0_0 0x00000001U |
| #define | GPIO_MODER_MODER0_1 0x00000002U |
| #define | GPIO_MODER_MODER1 0x0000000CU |
| #define | GPIO_MODER_MODER1_0 0x00000004U |
| #define | GPIO_MODER_MODER1_1 0x00000008U |
| #define | GPIO_MODER_MODER2 0x00000030U |
| #define | GPIO_MODER_MODER2_0 0x00000010U |
| #define | GPIO_MODER_MODER2_1 0x00000020U |
| #define | GPIO_MODER_MODER3 0x000000C0U |
| #define | GPIO_MODER_MODER3_0 0x00000040U |
| #define | GPIO_MODER_MODER3_1 0x00000080U |
| #define | GPIO_MODER_MODER4 0x00000300U |
| #define | GPIO_MODER_MODER4_0 0x00000100U |
| #define | GPIO_MODER_MODER4_1 0x00000200U |
| #define | GPIO_MODER_MODER5 0x00000C00U |
| #define | GPIO_MODER_MODER5_0 0x00000400U |
| #define | GPIO_MODER_MODER5_1 0x00000800U |
| #define | GPIO_MODER_MODER6 0x00003000U |
| #define | GPIO_MODER_MODER6_0 0x00001000U |
| #define | GPIO_MODER_MODER6_1 0x00002000U |
| #define | GPIO_MODER_MODER7 0x0000C000U |
| #define | GPIO_MODER_MODER7_0 0x00004000U |
| #define | GPIO_MODER_MODER7_1 0x00008000U |
| #define | GPIO_MODER_MODER8 0x00030000U |
| #define | GPIO_MODER_MODER8_0 0x00010000U |
| #define | GPIO_MODER_MODER8_1 0x00020000U |
| #define | GPIO_MODER_MODER9 0x000C0000U |
| #define | GPIO_MODER_MODER9_0 0x00040000U |
| #define | GPIO_MODER_MODER9_1 0x00080000U |
| #define | GPIO_MODER_MODER10 0x00300000U |
| #define | GPIO_MODER_MODER10_0 0x00100000U |
| #define | GPIO_MODER_MODER10_1 0x00200000U |
| #define | GPIO_MODER_MODER11 0x00C00000U |
| #define | GPIO_MODER_MODER11_0 0x00400000U |
| #define | GPIO_MODER_MODER11_1 0x00800000U |
| #define | GPIO_MODER_MODER12 0x03000000U |
| #define | GPIO_MODER_MODER12_0 0x01000000U |
| #define | GPIO_MODER_MODER12_1 0x02000000U |
| #define | GPIO_MODER_MODER13 0x0C000000U |
| #define | GPIO_MODER_MODER13_0 0x04000000U |
| #define | GPIO_MODER_MODER13_1 0x08000000U |
| #define | GPIO_MODER_MODER14 0x30000000U |
| #define | GPIO_MODER_MODER14_0 0x10000000U |
| #define | GPIO_MODER_MODER14_1 0x20000000U |
| #define | GPIO_MODER_MODER15 0xC0000000U |
| #define | GPIO_MODER_MODER15_0 0x40000000U |
| #define | GPIO_MODER_MODER15_1 0x80000000U |
| #define | GPIO_OTYPER_OT_0 0x00000001U |
| #define | GPIO_OTYPER_OT_1 0x00000002U |
| #define | GPIO_OTYPER_OT_2 0x00000004U |
| #define | GPIO_OTYPER_OT_3 0x00000008U |
| #define | GPIO_OTYPER_OT_4 0x00000010U |
| #define | GPIO_OTYPER_OT_5 0x00000020U |
| #define | GPIO_OTYPER_OT_6 0x00000040U |
| #define | GPIO_OTYPER_OT_7 0x00000080U |
| #define | GPIO_OTYPER_OT_8 0x00000100U |
| #define | GPIO_OTYPER_OT_9 0x00000200U |
| #define | GPIO_OTYPER_OT_10 0x00000400U |
| #define | GPIO_OTYPER_OT_11 0x00000800U |
| #define | GPIO_OTYPER_OT_12 0x00001000U |
| #define | GPIO_OTYPER_OT_13 0x00002000U |
| #define | GPIO_OTYPER_OT_14 0x00004000U |
| #define | GPIO_OTYPER_OT_15 0x00008000U |
| #define | GPIO_OSPEEDER_OSPEEDR0 0x00000003U |
| #define | GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U |
| #define | GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U |
| #define | GPIO_OSPEEDER_OSPEEDR1 0x0000000CU |
| #define | GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U |
| #define | GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U |
| #define | GPIO_OSPEEDER_OSPEEDR2 0x00000030U |
| #define | GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U |
| #define | GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U |
| #define | GPIO_OSPEEDER_OSPEEDR3 0x000000C0U |
| #define | GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U |
| #define | GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U |
| #define | GPIO_OSPEEDER_OSPEEDR4 0x00000300U |
| #define | GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U |
| #define | GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U |
| #define | GPIO_OSPEEDER_OSPEEDR5 0x00000C00U |
| #define | GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U |
| #define | GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U |
| #define | GPIO_OSPEEDER_OSPEEDR6 0x00003000U |
| #define | GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U |
| #define | GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U |
| #define | GPIO_OSPEEDER_OSPEEDR7 0x0000C000U |
| #define | GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U |
| #define | GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U |
| #define | GPIO_OSPEEDER_OSPEEDR8 0x00030000U |
| #define | GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U |
| #define | GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U |
| #define | GPIO_OSPEEDER_OSPEEDR9 0x000C0000U |
| #define | GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U |
| #define | GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U |
| #define | GPIO_OSPEEDER_OSPEEDR10 0x00300000U |
| #define | GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U |
| #define | GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U |
| #define | GPIO_OSPEEDER_OSPEEDR11 0x00C00000U |
| #define | GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U |
| #define | GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U |
| #define | GPIO_OSPEEDER_OSPEEDR12 0x03000000U |
| #define | GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U |
| #define | GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U |
| #define | GPIO_OSPEEDER_OSPEEDR13 0x0C000000U |
| #define | GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U |
| #define | GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U |
| #define | GPIO_OSPEEDER_OSPEEDR14 0x30000000U |
| #define | GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U |
| #define | GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U |
| #define | GPIO_OSPEEDER_OSPEEDR15 0xC0000000U |
| #define | GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U |
| #define | GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U |
| #define | GPIO_PUPDR_PUPDR0 0x00000003U |
| #define | GPIO_PUPDR_PUPDR0_0 0x00000001U |
| #define | GPIO_PUPDR_PUPDR0_1 0x00000002U |
| #define | GPIO_PUPDR_PUPDR1 0x0000000CU |
| #define | GPIO_PUPDR_PUPDR1_0 0x00000004U |
| #define | GPIO_PUPDR_PUPDR1_1 0x00000008U |
| #define | GPIO_PUPDR_PUPDR2 0x00000030U |
| #define | GPIO_PUPDR_PUPDR2_0 0x00000010U |
| #define | GPIO_PUPDR_PUPDR2_1 0x00000020U |
| #define | GPIO_PUPDR_PUPDR3 0x000000C0U |
| #define | GPIO_PUPDR_PUPDR3_0 0x00000040U |
| #define | GPIO_PUPDR_PUPDR3_1 0x00000080U |
| #define | GPIO_PUPDR_PUPDR4 0x00000300U |
| #define | GPIO_PUPDR_PUPDR4_0 0x00000100U |
| #define | GPIO_PUPDR_PUPDR4_1 0x00000200U |
| #define | GPIO_PUPDR_PUPDR5 0x00000C00U |
| #define | GPIO_PUPDR_PUPDR5_0 0x00000400U |
| #define | GPIO_PUPDR_PUPDR5_1 0x00000800U |
| #define | GPIO_PUPDR_PUPDR6 0x00003000U |
| #define | GPIO_PUPDR_PUPDR6_0 0x00001000U |
| #define | GPIO_PUPDR_PUPDR6_1 0x00002000U |
| #define | GPIO_PUPDR_PUPDR7 0x0000C000U |
| #define | GPIO_PUPDR_PUPDR7_0 0x00004000U |
| #define | GPIO_PUPDR_PUPDR7_1 0x00008000U |
| #define | GPIO_PUPDR_PUPDR8 0x00030000U |
| #define | GPIO_PUPDR_PUPDR8_0 0x00010000U |
| #define | GPIO_PUPDR_PUPDR8_1 0x00020000U |
| #define | GPIO_PUPDR_PUPDR9 0x000C0000U |
| #define | GPIO_PUPDR_PUPDR9_0 0x00040000U |
| #define | GPIO_PUPDR_PUPDR9_1 0x00080000U |
| #define | GPIO_PUPDR_PUPDR10 0x00300000U |
| #define | GPIO_PUPDR_PUPDR10_0 0x00100000U |
| #define | GPIO_PUPDR_PUPDR10_1 0x00200000U |
| #define | GPIO_PUPDR_PUPDR11 0x00C00000U |
| #define | GPIO_PUPDR_PUPDR11_0 0x00400000U |
| #define | GPIO_PUPDR_PUPDR11_1 0x00800000U |
| #define | GPIO_PUPDR_PUPDR12 0x03000000U |
| #define | GPIO_PUPDR_PUPDR12_0 0x01000000U |
| #define | GPIO_PUPDR_PUPDR12_1 0x02000000U |
| #define | GPIO_PUPDR_PUPDR13 0x0C000000U |
| #define | GPIO_PUPDR_PUPDR13_0 0x04000000U |
| #define | GPIO_PUPDR_PUPDR13_1 0x08000000U |
| #define | GPIO_PUPDR_PUPDR14 0x30000000U |
| #define | GPIO_PUPDR_PUPDR14_0 0x10000000U |
| #define | GPIO_PUPDR_PUPDR14_1 0x20000000U |
| #define | GPIO_PUPDR_PUPDR15 0xC0000000U |
| #define | GPIO_PUPDR_PUPDR15_0 0x40000000U |
| #define | GPIO_PUPDR_PUPDR15_1 0x80000000U |
| #define | GPIO_IDR_IDR_0 0x00000001U |
| #define | GPIO_IDR_IDR_1 0x00000002U |
| #define | GPIO_IDR_IDR_2 0x00000004U |
| #define | GPIO_IDR_IDR_3 0x00000008U |
| #define | GPIO_IDR_IDR_4 0x00000010U |
| #define | GPIO_IDR_IDR_5 0x00000020U |
| #define | GPIO_IDR_IDR_6 0x00000040U |
| #define | GPIO_IDR_IDR_7 0x00000080U |
| #define | GPIO_IDR_IDR_8 0x00000100U |
| #define | GPIO_IDR_IDR_9 0x00000200U |
| #define | GPIO_IDR_IDR_10 0x00000400U |
| #define | GPIO_IDR_IDR_11 0x00000800U |
| #define | GPIO_IDR_IDR_12 0x00001000U |
| #define | GPIO_IDR_IDR_13 0x00002000U |
| #define | GPIO_IDR_IDR_14 0x00004000U |
| #define | GPIO_IDR_IDR_15 0x00008000U |
| #define | GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 |
| #define | GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 |
| #define | GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 |
| #define | GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 |
| #define | GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 |
| #define | GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 |
| #define | GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 |
| #define | GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 |
| #define | GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 |
| #define | GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 |
| #define | GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 |
| #define | GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 |
| #define | GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 |
| #define | GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 |
| #define | GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 |
| #define | GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 |
| #define | GPIO_ODR_ODR_0 0x00000001U |
| #define | GPIO_ODR_ODR_1 0x00000002U |
| #define | GPIO_ODR_ODR_2 0x00000004U |
| #define | GPIO_ODR_ODR_3 0x00000008U |
| #define | GPIO_ODR_ODR_4 0x00000010U |
| #define | GPIO_ODR_ODR_5 0x00000020U |
| #define | GPIO_ODR_ODR_6 0x00000040U |
| #define | GPIO_ODR_ODR_7 0x00000080U |
| #define | GPIO_ODR_ODR_8 0x00000100U |
| #define | GPIO_ODR_ODR_9 0x00000200U |
| #define | GPIO_ODR_ODR_10 0x00000400U |
| #define | GPIO_ODR_ODR_11 0x00000800U |
| #define | GPIO_ODR_ODR_12 0x00001000U |
| #define | GPIO_ODR_ODR_13 0x00002000U |
| #define | GPIO_ODR_ODR_14 0x00004000U |
| #define | GPIO_ODR_ODR_15 0x00008000U |
| #define | GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 |
| #define | GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 |
| #define | GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 |
| #define | GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 |
| #define | GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 |
| #define | GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 |
| #define | GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 |
| #define | GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 |
| #define | GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 |
| #define | GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 |
| #define | GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 |
| #define | GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 |
| #define | GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 |
| #define | GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 |
| #define | GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 |
| #define | GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 |
| #define | GPIO_BSRR_BS_0 0x00000001U |
| #define | GPIO_BSRR_BS_1 0x00000002U |
| #define | GPIO_BSRR_BS_2 0x00000004U |
| #define | GPIO_BSRR_BS_3 0x00000008U |
| #define | GPIO_BSRR_BS_4 0x00000010U |
| #define | GPIO_BSRR_BS_5 0x00000020U |
| #define | GPIO_BSRR_BS_6 0x00000040U |
| #define | GPIO_BSRR_BS_7 0x00000080U |
| #define | GPIO_BSRR_BS_8 0x00000100U |
| #define | GPIO_BSRR_BS_9 0x00000200U |
| #define | GPIO_BSRR_BS_10 0x00000400U |
| #define | GPIO_BSRR_BS_11 0x00000800U |
| #define | GPIO_BSRR_BS_12 0x00001000U |
| #define | GPIO_BSRR_BS_13 0x00002000U |
| #define | GPIO_BSRR_BS_14 0x00004000U |
| #define | GPIO_BSRR_BS_15 0x00008000U |
| #define | GPIO_BSRR_BR_0 0x00010000U |
| #define | GPIO_BSRR_BR_1 0x00020000U |
| #define | GPIO_BSRR_BR_2 0x00040000U |
| #define | GPIO_BSRR_BR_3 0x00080000U |
| #define | GPIO_BSRR_BR_4 0x00100000U |
| #define | GPIO_BSRR_BR_5 0x00200000U |
| #define | GPIO_BSRR_BR_6 0x00400000U |
| #define | GPIO_BSRR_BR_7 0x00800000U |
| #define | GPIO_BSRR_BR_8 0x01000000U |
| #define | GPIO_BSRR_BR_9 0x02000000U |
| #define | GPIO_BSRR_BR_10 0x04000000U |
| #define | GPIO_BSRR_BR_11 0x08000000U |
| #define | GPIO_BSRR_BR_12 0x10000000U |
| #define | GPIO_BSRR_BR_13 0x20000000U |
| #define | GPIO_BSRR_BR_14 0x40000000U |
| #define | GPIO_BSRR_BR_15 0x80000000U |
| #define | GPIO_LCKR_LCK0 0x00000001U |
| #define | GPIO_LCKR_LCK1 0x00000002U |
| #define | GPIO_LCKR_LCK2 0x00000004U |
| #define | GPIO_LCKR_LCK3 0x00000008U |
| #define | GPIO_LCKR_LCK4 0x00000010U |
| #define | GPIO_LCKR_LCK5 0x00000020U |
| #define | GPIO_LCKR_LCK6 0x00000040U |
| #define | GPIO_LCKR_LCK7 0x00000080U |
| #define | GPIO_LCKR_LCK8 0x00000100U |
| #define | GPIO_LCKR_LCK9 0x00000200U |
| #define | GPIO_LCKR_LCK10 0x00000400U |
| #define | GPIO_LCKR_LCK11 0x00000800U |
| #define | GPIO_LCKR_LCK12 0x00001000U |
| #define | GPIO_LCKR_LCK13 0x00002000U |
| #define | GPIO_LCKR_LCK14 0x00004000U |
| #define | GPIO_LCKR_LCK15 0x00008000U |
| #define | GPIO_LCKR_LCKK 0x00010000U |
| #define | I2C_CR1_PE 0x00000001U |
| #define | I2C_CR1_SMBUS 0x00000002U |
| #define | I2C_CR1_SMBTYPE 0x00000008U |
| #define | I2C_CR1_ENARP 0x00000010U |
| #define | I2C_CR1_ENPEC 0x00000020U |
| #define | I2C_CR1_ENGC 0x00000040U |
| #define | I2C_CR1_NOSTRETCH 0x00000080U |
| #define | I2C_CR1_START 0x00000100U |
| #define | I2C_CR1_STOP 0x00000200U |
| #define | I2C_CR1_ACK 0x00000400U |
| #define | I2C_CR1_POS 0x00000800U |
| #define | I2C_CR1_PEC 0x00001000U |
| #define | I2C_CR1_ALERT 0x00002000U |
| #define | I2C_CR1_SWRST 0x00008000U |
| #define | I2C_CR2_FREQ 0x0000003FU |
| #define | I2C_CR2_FREQ_0 0x00000001U |
| #define | I2C_CR2_FREQ_1 0x00000002U |
| #define | I2C_CR2_FREQ_2 0x00000004U |
| #define | I2C_CR2_FREQ_3 0x00000008U |
| #define | I2C_CR2_FREQ_4 0x00000010U |
| #define | I2C_CR2_FREQ_5 0x00000020U |
| #define | I2C_CR2_ITERREN 0x00000100U |
| #define | I2C_CR2_ITEVTEN 0x00000200U |
| #define | I2C_CR2_ITBUFEN 0x00000400U |
| #define | I2C_CR2_DMAEN 0x00000800U |
| #define | I2C_CR2_LAST 0x00001000U |
| #define | I2C_OAR1_ADD1_7 0x000000FEU |
| #define | I2C_OAR1_ADD8_9 0x00000300U |
| #define | I2C_OAR1_ADD0 0x00000001U |
| #define | I2C_OAR1_ADD1 0x00000002U |
| #define | I2C_OAR1_ADD2 0x00000004U |
| #define | I2C_OAR1_ADD3 0x00000008U |
| #define | I2C_OAR1_ADD4 0x00000010U |
| #define | I2C_OAR1_ADD5 0x00000020U |
| #define | I2C_OAR1_ADD6 0x00000040U |
| #define | I2C_OAR1_ADD7 0x00000080U |
| #define | I2C_OAR1_ADD8 0x00000100U |
| #define | I2C_OAR1_ADD9 0x00000200U |
| #define | I2C_OAR1_ADDMODE 0x00008000U |
| #define | I2C_OAR2_ENDUAL 0x00000001U |
| #define | I2C_OAR2_ADD2 0x000000FEU |
| #define | I2C_DR_DR 0x000000FFU |
| #define | I2C_SR1_SB 0x00000001U |
| #define | I2C_SR1_ADDR 0x00000002U |
| #define | I2C_SR1_BTF 0x00000004U |
| #define | I2C_SR1_ADD10 0x00000008U |
| #define | I2C_SR1_STOPF 0x00000010U |
| #define | I2C_SR1_RXNE 0x00000040U |
| #define | I2C_SR1_TXE 0x00000080U |
| #define | I2C_SR1_BERR 0x00000100U |
| #define | I2C_SR1_ARLO 0x00000200U |
| #define | I2C_SR1_AF 0x00000400U |
| #define | I2C_SR1_OVR 0x00000800U |
| #define | I2C_SR1_PECERR 0x00001000U |
| #define | I2C_SR1_TIMEOUT 0x00004000U |
| #define | I2C_SR1_SMBALERT 0x00008000U |
| #define | I2C_SR2_MSL 0x00000001U |
| #define | I2C_SR2_BUSY 0x00000002U |
| #define | I2C_SR2_TRA 0x00000004U |
| #define | I2C_SR2_GENCALL 0x00000010U |
| #define | I2C_SR2_SMBDEFAULT 0x00000020U |
| #define | I2C_SR2_SMBHOST 0x00000040U |
| #define | I2C_SR2_DUALF 0x00000080U |
| #define | I2C_SR2_PEC 0x0000FF00U |
| #define | I2C_CCR_CCR 0x00000FFFU |
| #define | I2C_CCR_DUTY 0x00004000U |
| #define | I2C_CCR_FS 0x00008000U |
| #define | I2C_TRISE_TRISE 0x0000003FU |
| #define | I2C_FLTR_DNF 0x0000000FU |
| #define | I2C_FLTR_ANOFF 0x00000010U |
| #define | IWDG_KR_KEY 0xFFFFU |
| #define | IWDG_PR_PR 0x07U |
| #define | IWDG_PR_PR_0 0x01U |
| #define | IWDG_PR_PR_1 0x02U |
| #define | IWDG_PR_PR_2 0x04U |
| #define | IWDG_RLR_RL 0x0FFFU |
| #define | IWDG_SR_PVU 0x01U |
| #define | IWDG_SR_RVU 0x02U |
| #define | PWR_CR_LPDS 0x00000001U |
| #define | PWR_CR_PDDS 0x00000002U |
| #define | PWR_CR_CWUF 0x00000004U |
| #define | PWR_CR_CSBF 0x00000008U |
| #define | PWR_CR_PVDE 0x00000010U |
| #define | PWR_CR_PLS 0x000000E0U |
| #define | PWR_CR_PLS_0 0x00000020U |
| #define | PWR_CR_PLS_1 0x00000040U |
| #define | PWR_CR_PLS_2 0x00000080U |
| #define | PWR_CR_PLS_LEV0 0x00000000U |
| #define | PWR_CR_PLS_LEV1 0x00000020U |
| #define | PWR_CR_PLS_LEV2 0x00000040U |
| #define | PWR_CR_PLS_LEV3 0x00000060U |
| #define | PWR_CR_PLS_LEV4 0x00000080U |
| #define | PWR_CR_PLS_LEV5 0x000000A0U |
| #define | PWR_CR_PLS_LEV6 0x000000C0U |
| #define | PWR_CR_PLS_LEV7 0x000000E0U |
| #define | PWR_CR_DBP 0x00000100U |
| #define | PWR_CR_FPDS 0x00000200U |
| #define | PWR_CR_VOS 0x00004000U |
| #define | PWR_CR_PMODE PWR_CR_VOS |
| #define | PWR_CSR_WUF 0x00000001U |
| #define | PWR_CSR_SBF 0x00000002U |
| #define | PWR_CSR_PVDO 0x00000004U |
| #define | PWR_CSR_BRR 0x00000008U |
| #define | PWR_CSR_EWUP 0x00000100U |
| #define | PWR_CSR_BRE 0x00000200U |
| #define | PWR_CSR_VOSRDY 0x00004000U |
| #define | PWR_CSR_REGRDY PWR_CSR_VOSRDY |
| #define | RCC_CR_HSION 0x00000001U |
| #define | RCC_CR_HSIRDY 0x00000002U |
| #define | RCC_CR_HSITRIM 0x000000F8U |
| #define | RCC_CR_HSITRIM_0 0x00000008U |
| #define | RCC_CR_HSITRIM_1 0x00000010U |
| #define | RCC_CR_HSITRIM_2 0x00000020U |
| #define | RCC_CR_HSITRIM_3 0x00000040U |
| #define | RCC_CR_HSITRIM_4 0x00000080U |
| #define | RCC_CR_HSICAL 0x0000FF00U |
| #define | RCC_CR_HSICAL_0 0x00000100U |
| #define | RCC_CR_HSICAL_1 0x00000200U |
| #define | RCC_CR_HSICAL_2 0x00000400U |
| #define | RCC_CR_HSICAL_3 0x00000800U |
| #define | RCC_CR_HSICAL_4 0x00001000U |
| #define | RCC_CR_HSICAL_5 0x00002000U |
| #define | RCC_CR_HSICAL_6 0x00004000U |
| #define | RCC_CR_HSICAL_7 0x00008000U |
| #define | RCC_CR_HSEON 0x00010000U |
| #define | RCC_CR_HSERDY 0x00020000U |
| #define | RCC_CR_HSEBYP 0x00040000U |
| #define | RCC_CR_CSSON 0x00080000U |
| #define | RCC_CR_PLLON 0x01000000U |
| #define | RCC_CR_PLLRDY 0x02000000U |
| #define | RCC_CR_PLLI2SON 0x04000000U |
| #define | RCC_CR_PLLI2SRDY 0x08000000U |
| #define | RCC_PLLCFGR_PLLM 0x0000003FU |
| #define | RCC_PLLCFGR_PLLM_0 0x00000001U |
| #define | RCC_PLLCFGR_PLLM_1 0x00000002U |
| #define | RCC_PLLCFGR_PLLM_2 0x00000004U |
| #define | RCC_PLLCFGR_PLLM_3 0x00000008U |
| #define | RCC_PLLCFGR_PLLM_4 0x00000010U |
| #define | RCC_PLLCFGR_PLLM_5 0x00000020U |
| #define | RCC_PLLCFGR_PLLN 0x00007FC0U |
| #define | RCC_PLLCFGR_PLLN_0 0x00000040U |
| #define | RCC_PLLCFGR_PLLN_1 0x00000080U |
| #define | RCC_PLLCFGR_PLLN_2 0x00000100U |
| #define | RCC_PLLCFGR_PLLN_3 0x00000200U |
| #define | RCC_PLLCFGR_PLLN_4 0x00000400U |
| #define | RCC_PLLCFGR_PLLN_5 0x00000800U |
| #define | RCC_PLLCFGR_PLLN_6 0x00001000U |
| #define | RCC_PLLCFGR_PLLN_7 0x00002000U |
| #define | RCC_PLLCFGR_PLLN_8 0x00004000U |
| #define | RCC_PLLCFGR_PLLP 0x00030000U |
| #define | RCC_PLLCFGR_PLLP_0 0x00010000U |
| #define | RCC_PLLCFGR_PLLP_1 0x00020000U |
| #define | RCC_PLLCFGR_PLLSRC 0x00400000U |
| #define | RCC_PLLCFGR_PLLSRC_HSE 0x00400000U |
| #define | RCC_PLLCFGR_PLLSRC_HSI 0x00000000U |
| #define | RCC_PLLCFGR_PLLQ 0x0F000000U |
| #define | RCC_PLLCFGR_PLLQ_0 0x01000000U |
| #define | RCC_PLLCFGR_PLLQ_1 0x02000000U |
| #define | RCC_PLLCFGR_PLLQ_2 0x04000000U |
| #define | RCC_PLLCFGR_PLLQ_3 0x08000000U |
| #define | RCC_CFGR_SW 0x00000003U |
| #define | RCC_CFGR_SW_0 0x00000001U |
| #define | RCC_CFGR_SW_1 0x00000002U |
| #define | RCC_CFGR_SW_HSI 0x00000000U |
| #define | RCC_CFGR_SW_HSE 0x00000001U |
| #define | RCC_CFGR_SW_PLL 0x00000002U |
| #define | RCC_CFGR_SWS 0x0000000CU |
| #define | RCC_CFGR_SWS_0 0x00000004U |
| #define | RCC_CFGR_SWS_1 0x00000008U |
| #define | RCC_CFGR_SWS_HSI 0x00000000U |
| #define | RCC_CFGR_SWS_HSE 0x00000004U |
| #define | RCC_CFGR_SWS_PLL 0x00000008U |
| #define | RCC_CFGR_HPRE 0x000000F0U |
| #define | RCC_CFGR_HPRE_0 0x00000010U |
| #define | RCC_CFGR_HPRE_1 0x00000020U |
| #define | RCC_CFGR_HPRE_2 0x00000040U |
| #define | RCC_CFGR_HPRE_3 0x00000080U |
| #define | RCC_CFGR_HPRE_DIV1 0x00000000U |
| #define | RCC_CFGR_HPRE_DIV2 0x00000080U |
| #define | RCC_CFGR_HPRE_DIV4 0x00000090U |
| #define | RCC_CFGR_HPRE_DIV8 0x000000A0U |
| #define | RCC_CFGR_HPRE_DIV16 0x000000B0U |
| #define | RCC_CFGR_HPRE_DIV64 0x000000C0U |
| #define | RCC_CFGR_HPRE_DIV128 0x000000D0U |
| #define | RCC_CFGR_HPRE_DIV256 0x000000E0U |
| #define | RCC_CFGR_HPRE_DIV512 0x000000F0U |
| #define | RCC_CFGR_PPRE1 0x00001C00U |
| #define | RCC_CFGR_PPRE1_0 0x00000400U |
| #define | RCC_CFGR_PPRE1_1 0x00000800U |
| #define | RCC_CFGR_PPRE1_2 0x00001000U |
| #define | RCC_CFGR_PPRE1_DIV1 0x00000000U |
| #define | RCC_CFGR_PPRE1_DIV2 0x00001000U |
| #define | RCC_CFGR_PPRE1_DIV4 0x00001400U |
| #define | RCC_CFGR_PPRE1_DIV8 0x00001800U |
| #define | RCC_CFGR_PPRE1_DIV16 0x00001C00U |
| #define | RCC_CFGR_PPRE2 0x0000E000U |
| #define | RCC_CFGR_PPRE2_0 0x00002000U |
| #define | RCC_CFGR_PPRE2_1 0x00004000U |
| #define | RCC_CFGR_PPRE2_2 0x00008000U |
| #define | RCC_CFGR_PPRE2_DIV1 0x00000000U |
| #define | RCC_CFGR_PPRE2_DIV2 0x00008000U |
| #define | RCC_CFGR_PPRE2_DIV4 0x0000A000U |
| #define | RCC_CFGR_PPRE2_DIV8 0x0000C000U |
| #define | RCC_CFGR_PPRE2_DIV16 0x0000E000U |
| #define | RCC_CFGR_RTCPRE 0x001F0000U |
| #define | RCC_CFGR_RTCPRE_0 0x00010000U |
| #define | RCC_CFGR_RTCPRE_1 0x00020000U |
| #define | RCC_CFGR_RTCPRE_2 0x00040000U |
| #define | RCC_CFGR_RTCPRE_3 0x00080000U |
| #define | RCC_CFGR_RTCPRE_4 0x00100000U |
| #define | RCC_CFGR_MCO1 0x00600000U |
| #define | RCC_CFGR_MCO1_0 0x00200000U |
| #define | RCC_CFGR_MCO1_1 0x00400000U |
| #define | RCC_CFGR_I2SSRC 0x00800000U |
| #define | RCC_CFGR_MCO1PRE 0x07000000U |
| #define | RCC_CFGR_MCO1PRE_0 0x01000000U |
| #define | RCC_CFGR_MCO1PRE_1 0x02000000U |
| #define | RCC_CFGR_MCO1PRE_2 0x04000000U |
| #define | RCC_CFGR_MCO2PRE 0x38000000U |
| #define | RCC_CFGR_MCO2PRE_0 0x08000000U |
| #define | RCC_CFGR_MCO2PRE_1 0x10000000U |
| #define | RCC_CFGR_MCO2PRE_2 0x20000000U |
| #define | RCC_CFGR_MCO2 0xC0000000U |
| #define | RCC_CFGR_MCO2_0 0x40000000U |
| #define | RCC_CFGR_MCO2_1 0x80000000U |
| #define | RCC_CIR_LSIRDYF 0x00000001U |
| #define | RCC_CIR_LSERDYF 0x00000002U |
| #define | RCC_CIR_HSIRDYF 0x00000004U |
| #define | RCC_CIR_HSERDYF 0x00000008U |
| #define | RCC_CIR_PLLRDYF 0x00000010U |
| #define | RCC_CIR_PLLI2SRDYF 0x00000020U |
| #define | RCC_CIR_CSSF 0x00000080U |
| #define | RCC_CIR_LSIRDYIE 0x00000100U |
| #define | RCC_CIR_LSERDYIE 0x00000200U |
| #define | RCC_CIR_HSIRDYIE 0x00000400U |
| #define | RCC_CIR_HSERDYIE 0x00000800U |
| #define | RCC_CIR_PLLRDYIE 0x00001000U |
| #define | RCC_CIR_PLLI2SRDYIE 0x00002000U |
| #define | RCC_CIR_LSIRDYC 0x00010000U |
| #define | RCC_CIR_LSERDYC 0x00020000U |
| #define | RCC_CIR_HSIRDYC 0x00040000U |
| #define | RCC_CIR_HSERDYC 0x00080000U |
| #define | RCC_CIR_PLLRDYC 0x00100000U |
| #define | RCC_CIR_PLLI2SRDYC 0x00200000U |
| #define | RCC_CIR_CSSC 0x00800000U |
| #define | RCC_AHB1RSTR_GPIOARST 0x00000001U |
| #define | RCC_AHB1RSTR_GPIOBRST 0x00000002U |
| #define | RCC_AHB1RSTR_GPIOCRST 0x00000004U |
| #define | RCC_AHB1RSTR_GPIODRST 0x00000008U |
| #define | RCC_AHB1RSTR_GPIOERST 0x00000010U |
| #define | RCC_AHB1RSTR_GPIOFRST 0x00000020U |
| #define | RCC_AHB1RSTR_GPIOGRST 0x00000040U |
| #define | RCC_AHB1RSTR_GPIOHRST 0x00000080U |
| #define | RCC_AHB1RSTR_GPIOIRST 0x00000100U |
| #define | RCC_AHB1RSTR_CRCRST 0x00001000U |
| #define | RCC_AHB1RSTR_DMA1RST 0x00200000U |
| #define | RCC_AHB1RSTR_DMA2RST 0x00400000U |
| #define | RCC_AHB1RSTR_ETHMACRST 0x02000000U |
| #define | RCC_AHB1RSTR_OTGHRST 0x20000000U |
| #define | RCC_AHB2RSTR_DCMIRST 0x00000001U |
| #define | RCC_AHB2RSTR_RNGRST 0x00000040U |
| #define | RCC_AHB2RSTR_OTGFSRST 0x00000080U |
| #define | RCC_AHB3RSTR_FSMCRST 0x00000001U |
| #define | RCC_APB1RSTR_TIM2RST 0x00000001U |
| #define | RCC_APB1RSTR_TIM3RST 0x00000002U |
| #define | RCC_APB1RSTR_TIM4RST 0x00000004U |
| #define | RCC_APB1RSTR_TIM5RST 0x00000008U |
| #define | RCC_APB1RSTR_TIM6RST 0x00000010U |
| #define | RCC_APB1RSTR_TIM7RST 0x00000020U |
| #define | RCC_APB1RSTR_TIM12RST 0x00000040U |
| #define | RCC_APB1RSTR_TIM13RST 0x00000080U |
| #define | RCC_APB1RSTR_TIM14RST 0x00000100U |
| #define | RCC_APB1RSTR_WWDGRST 0x00000800U |
| #define | RCC_APB1RSTR_SPI2RST 0x00004000U |
| #define | RCC_APB1RSTR_SPI3RST 0x00008000U |
| #define | RCC_APB1RSTR_USART2RST 0x00020000U |
| #define | RCC_APB1RSTR_USART3RST 0x00040000U |
| #define | RCC_APB1RSTR_UART4RST 0x00080000U |
| #define | RCC_APB1RSTR_UART5RST 0x00100000U |
| #define | RCC_APB1RSTR_I2C1RST 0x00200000U |
| #define | RCC_APB1RSTR_I2C2RST 0x00400000U |
| #define | RCC_APB1RSTR_I2C3RST 0x00800000U |
| #define | RCC_APB1RSTR_CAN1RST 0x02000000U |
| #define | RCC_APB1RSTR_CAN2RST 0x04000000U |
| #define | RCC_APB1RSTR_PWRRST 0x10000000U |
| #define | RCC_APB1RSTR_DACRST 0x20000000U |
| #define | RCC_APB2RSTR_TIM1RST 0x00000001U |
| #define | RCC_APB2RSTR_TIM8RST 0x00000002U |
| #define | RCC_APB2RSTR_USART1RST 0x00000010U |
| #define | RCC_APB2RSTR_USART6RST 0x00000020U |
| #define | RCC_APB2RSTR_ADCRST 0x00000100U |
| #define | RCC_APB2RSTR_SDIORST 0x00000800U |
| #define | RCC_APB2RSTR_SPI1RST 0x00001000U |
| #define | RCC_APB2RSTR_SYSCFGRST 0x00004000U |
| #define | RCC_APB2RSTR_TIM9RST 0x00010000U |
| #define | RCC_APB2RSTR_TIM10RST 0x00020000U |
| #define | RCC_APB2RSTR_TIM11RST 0x00040000U |
| #define | RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST |
| #define | RCC_AHB1ENR_GPIOAEN 0x00000001U |
| #define | RCC_AHB1ENR_GPIOBEN 0x00000002U |
| #define | RCC_AHB1ENR_GPIOCEN 0x00000004U |
| #define | RCC_AHB1ENR_GPIODEN 0x00000008U |
| #define | RCC_AHB1ENR_GPIOEEN 0x00000010U |
| #define | RCC_AHB1ENR_GPIOFEN 0x00000020U |
| #define | RCC_AHB1ENR_GPIOGEN 0x00000040U |
| #define | RCC_AHB1ENR_GPIOHEN 0x00000080U |
| #define | RCC_AHB1ENR_GPIOIEN 0x00000100U |
| #define | RCC_AHB1ENR_CRCEN 0x00001000U |
| #define | RCC_AHB1ENR_BKPSRAMEN 0x00040000U |
| #define | RCC_AHB1ENR_CCMDATARAMEN 0x00100000U |
| #define | RCC_AHB1ENR_DMA1EN 0x00200000U |
| #define | RCC_AHB1ENR_DMA2EN 0x00400000U |
| #define | RCC_AHB1ENR_ETHMACEN 0x02000000U |
| #define | RCC_AHB1ENR_ETHMACTXEN 0x04000000U |
| #define | RCC_AHB1ENR_ETHMACRXEN 0x08000000U |
| #define | RCC_AHB1ENR_ETHMACPTPEN 0x10000000U |
| #define | RCC_AHB1ENR_OTGHSEN 0x20000000U |
| #define | RCC_AHB1ENR_OTGHSULPIEN 0x40000000U |
| #define | RCC_AHB2ENR_DCMIEN 0x00000001U |
| #define | RCC_AHB2ENR_RNGEN 0x00000040U |
| #define | RCC_AHB2ENR_OTGFSEN 0x00000080U |
| #define | RCC_AHB3ENR_FSMCEN 0x00000001U |
| #define | RCC_APB1ENR_TIM2EN 0x00000001U |
| #define | RCC_APB1ENR_TIM3EN 0x00000002U |
| #define | RCC_APB1ENR_TIM4EN 0x00000004U |
| #define | RCC_APB1ENR_TIM5EN 0x00000008U |
| #define | RCC_APB1ENR_TIM6EN 0x00000010U |
| #define | RCC_APB1ENR_TIM7EN 0x00000020U |
| #define | RCC_APB1ENR_TIM12EN 0x00000040U |
| #define | RCC_APB1ENR_TIM13EN 0x00000080U |
| #define | RCC_APB1ENR_TIM14EN 0x00000100U |
| #define | RCC_APB1ENR_WWDGEN 0x00000800U |
| #define | RCC_APB1ENR_SPI2EN 0x00004000U |
| #define | RCC_APB1ENR_SPI3EN 0x00008000U |
| #define | RCC_APB1ENR_USART2EN 0x00020000U |
| #define | RCC_APB1ENR_USART3EN 0x00040000U |
| #define | RCC_APB1ENR_UART4EN 0x00080000U |
| #define | RCC_APB1ENR_UART5EN 0x00100000U |
| #define | RCC_APB1ENR_I2C1EN 0x00200000U |
| #define | RCC_APB1ENR_I2C2EN 0x00400000U |
| #define | RCC_APB1ENR_I2C3EN 0x00800000U |
| #define | RCC_APB1ENR_CAN1EN 0x02000000U |
| #define | RCC_APB1ENR_CAN2EN 0x04000000U |
| #define | RCC_APB1ENR_PWREN 0x10000000U |
| #define | RCC_APB1ENR_DACEN 0x20000000U |
| #define | RCC_APB2ENR_TIM1EN 0x00000001U |
| #define | RCC_APB2ENR_TIM8EN 0x00000002U |
| #define | RCC_APB2ENR_USART1EN 0x00000010U |
| #define | RCC_APB2ENR_USART6EN 0x00000020U |
| #define | RCC_APB2ENR_ADC1EN 0x00000100U |
| #define | RCC_APB2ENR_ADC2EN 0x00000200U |
| #define | RCC_APB2ENR_ADC3EN 0x00000400U |
| #define | RCC_APB2ENR_SDIOEN 0x00000800U |
| #define | RCC_APB2ENR_SPI1EN 0x00001000U |
| #define | RCC_APB2ENR_SYSCFGEN 0x00004000U |
| #define | RCC_APB2ENR_TIM9EN 0x00010000U |
| #define | RCC_APB2ENR_TIM10EN 0x00020000U |
| #define | RCC_APB2ENR_TIM11EN 0x00040000U |
| #define | RCC_APB2ENR_SPI5EN 0x00100000U |
| #define | RCC_APB2ENR_SPI6EN 0x00200000U |
| #define | RCC_AHB1LPENR_GPIOALPEN 0x00000001U |
| #define | RCC_AHB1LPENR_GPIOBLPEN 0x00000002U |
| #define | RCC_AHB1LPENR_GPIOCLPEN 0x00000004U |
| #define | RCC_AHB1LPENR_GPIODLPEN 0x00000008U |
| #define | RCC_AHB1LPENR_GPIOELPEN 0x00000010U |
| #define | RCC_AHB1LPENR_GPIOFLPEN 0x00000020U |
| #define | RCC_AHB1LPENR_GPIOGLPEN 0x00000040U |
| #define | RCC_AHB1LPENR_GPIOHLPEN 0x00000080U |
| #define | RCC_AHB1LPENR_GPIOILPEN 0x00000100U |
| #define | RCC_AHB1LPENR_CRCLPEN 0x00001000U |
| #define | RCC_AHB1LPENR_FLITFLPEN 0x00008000U |
| #define | RCC_AHB1LPENR_SRAM1LPEN 0x00010000U |
| #define | RCC_AHB1LPENR_SRAM2LPEN 0x00020000U |
| #define | RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U |
| #define | RCC_AHB1LPENR_DMA1LPEN 0x00200000U |
| #define | RCC_AHB1LPENR_DMA2LPEN 0x00400000U |
| #define | RCC_AHB1LPENR_ETHMACLPEN 0x02000000U |
| #define | RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U |
| #define | RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U |
| #define | RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U |
| #define | RCC_AHB1LPENR_OTGHSLPEN 0x20000000U |
| #define | RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U |
| #define | RCC_AHB2LPENR_DCMILPEN 0x00000001U |
| #define | RCC_AHB2LPENR_RNGLPEN 0x00000040U |
| #define | RCC_AHB2LPENR_OTGFSLPEN 0x00000080U |
| #define | RCC_AHB3LPENR_FSMCLPEN 0x00000001U |
| #define | RCC_APB1LPENR_TIM2LPEN 0x00000001U |
| #define | RCC_APB1LPENR_TIM3LPEN 0x00000002U |
| #define | RCC_APB1LPENR_TIM4LPEN 0x00000004U |
| #define | RCC_APB1LPENR_TIM5LPEN 0x00000008U |
| #define | RCC_APB1LPENR_TIM6LPEN 0x00000010U |
| #define | RCC_APB1LPENR_TIM7LPEN 0x00000020U |
| #define | RCC_APB1LPENR_TIM12LPEN 0x00000040U |
| #define | RCC_APB1LPENR_TIM13LPEN 0x00000080U |
| #define | RCC_APB1LPENR_TIM14LPEN 0x00000100U |
| #define | RCC_APB1LPENR_WWDGLPEN 0x00000800U |
| #define | RCC_APB1LPENR_SPI2LPEN 0x00004000U |
| #define | RCC_APB1LPENR_SPI3LPEN 0x00008000U |
| #define | RCC_APB1LPENR_USART2LPEN 0x00020000U |
| #define | RCC_APB1LPENR_USART3LPEN 0x00040000U |
| #define | RCC_APB1LPENR_UART4LPEN 0x00080000U |
| #define | RCC_APB1LPENR_UART5LPEN 0x00100000U |
| #define | RCC_APB1LPENR_I2C1LPEN 0x00200000U |
| #define | RCC_APB1LPENR_I2C2LPEN 0x00400000U |
| #define | RCC_APB1LPENR_I2C3LPEN 0x00800000U |
| #define | RCC_APB1LPENR_CAN1LPEN 0x02000000U |
| #define | RCC_APB1LPENR_CAN2LPEN 0x04000000U |
| #define | RCC_APB1LPENR_PWRLPEN 0x10000000U |
| #define | RCC_APB1LPENR_DACLPEN 0x20000000U |
| #define | RCC_APB2LPENR_TIM1LPEN 0x00000001U |
| #define | RCC_APB2LPENR_TIM8LPEN 0x00000002U |
| #define | RCC_APB2LPENR_USART1LPEN 0x00000010U |
| #define | RCC_APB2LPENR_USART6LPEN 0x00000020U |
| #define | RCC_APB2LPENR_ADC1LPEN 0x00000100U |
| #define | RCC_APB2LPENR_ADC2LPEN 0x00000200U |
| #define | RCC_APB2LPENR_ADC3LPEN 0x00000400U |
| #define | RCC_APB2LPENR_SDIOLPEN 0x00000800U |
| #define | RCC_APB2LPENR_SPI1LPEN 0x00001000U |
| #define | RCC_APB2LPENR_SYSCFGLPEN 0x00004000U |
| #define | RCC_APB2LPENR_TIM9LPEN 0x00010000U |
| #define | RCC_APB2LPENR_TIM10LPEN 0x00020000U |
| #define | RCC_APB2LPENR_TIM11LPEN 0x00040000U |
| #define | RCC_BDCR_LSEON 0x00000001U |
| #define | RCC_BDCR_LSERDY 0x00000002U |
| #define | RCC_BDCR_LSEBYP 0x00000004U |
| #define | RCC_BDCR_RTCSEL 0x00000300U |
| #define | RCC_BDCR_RTCSEL_0 0x00000100U |
| #define | RCC_BDCR_RTCSEL_1 0x00000200U |
| #define | RCC_BDCR_RTCEN 0x00008000U |
| #define | RCC_BDCR_BDRST 0x00010000U |
| #define | RCC_CSR_LSION 0x00000001U |
| #define | RCC_CSR_LSIRDY 0x00000002U |
| #define | RCC_CSR_RMVF 0x01000000U |
| #define | RCC_CSR_BORRSTF 0x02000000U |
| #define | RCC_CSR_PADRSTF 0x04000000U |
| #define | RCC_CSR_PORRSTF 0x08000000U |
| #define | RCC_CSR_SFTRSTF 0x10000000U |
| #define | RCC_CSR_WDGRSTF 0x20000000U |
| #define | RCC_CSR_WWDGRSTF 0x40000000U |
| #define | RCC_CSR_LPWRRSTF 0x80000000U |
| #define | RCC_SSCGR_MODPER 0x00001FFFU |
| #define | RCC_SSCGR_INCSTEP 0x0FFFE000U |
| #define | RCC_SSCGR_SPREADSEL 0x40000000U |
| #define | RCC_SSCGR_SSCGEN 0x80000000U |
| #define | RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U |
| #define | RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U |
| #define | RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U |
| #define | RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U |
| #define | RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U |
| #define | RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U |
| #define | RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U |
| #define | RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U |
| #define | RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U |
| #define | RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U |
| #define | RCC_PLLI2SCFGR_PLLI2SR 0x70000000U |
| #define | RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U |
| #define | RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U |
| #define | RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U |
| #define | RNG_CR_RNGEN 0x00000004U |
| #define | RNG_CR_IE 0x00000008U |
| #define | RNG_SR_DRDY 0x00000001U |
| #define | RNG_SR_CECS 0x00000002U |
| #define | RNG_SR_SECS 0x00000004U |
| #define | RNG_SR_CEIS 0x00000020U |
| #define | RNG_SR_SEIS 0x00000040U |
| #define | RTC_TR_PM 0x00400000U |
| #define | RTC_TR_HT 0x00300000U |
| #define | RTC_TR_HT_0 0x00100000U |
| #define | RTC_TR_HT_1 0x00200000U |
| #define | RTC_TR_HU 0x000F0000U |
| #define | RTC_TR_HU_0 0x00010000U |
| #define | RTC_TR_HU_1 0x00020000U |
| #define | RTC_TR_HU_2 0x00040000U |
| #define | RTC_TR_HU_3 0x00080000U |
| #define | RTC_TR_MNT 0x00007000U |
| #define | RTC_TR_MNT_0 0x00001000U |
| #define | RTC_TR_MNT_1 0x00002000U |
| #define | RTC_TR_MNT_2 0x00004000U |
| #define | RTC_TR_MNU 0x00000F00U |
| #define | RTC_TR_MNU_0 0x00000100U |
| #define | RTC_TR_MNU_1 0x00000200U |
| #define | RTC_TR_MNU_2 0x00000400U |
| #define | RTC_TR_MNU_3 0x00000800U |
| #define | RTC_TR_ST 0x00000070U |
| #define | RTC_TR_ST_0 0x00000010U |
| #define | RTC_TR_ST_1 0x00000020U |
| #define | RTC_TR_ST_2 0x00000040U |
| #define | RTC_TR_SU 0x0000000FU |
| #define | RTC_TR_SU_0 0x00000001U |
| #define | RTC_TR_SU_1 0x00000002U |
| #define | RTC_TR_SU_2 0x00000004U |
| #define | RTC_TR_SU_3 0x00000008U |
| #define | RTC_DR_YT 0x00F00000U |
| #define | RTC_DR_YT_0 0x00100000U |
| #define | RTC_DR_YT_1 0x00200000U |
| #define | RTC_DR_YT_2 0x00400000U |
| #define | RTC_DR_YT_3 0x00800000U |
| #define | RTC_DR_YU 0x000F0000U |
| #define | RTC_DR_YU_0 0x00010000U |
| #define | RTC_DR_YU_1 0x00020000U |
| #define | RTC_DR_YU_2 0x00040000U |
| #define | RTC_DR_YU_3 0x00080000U |
| #define | RTC_DR_WDU 0x0000E000U |
| #define | RTC_DR_WDU_0 0x00002000U |
| #define | RTC_DR_WDU_1 0x00004000U |
| #define | RTC_DR_WDU_2 0x00008000U |
| #define | RTC_DR_MT 0x00001000U |
| #define | RTC_DR_MU 0x00000F00U |
| #define | RTC_DR_MU_0 0x00000100U |
| #define | RTC_DR_MU_1 0x00000200U |
| #define | RTC_DR_MU_2 0x00000400U |
| #define | RTC_DR_MU_3 0x00000800U |
| #define | RTC_DR_DT 0x00000030U |
| #define | RTC_DR_DT_0 0x00000010U |
| #define | RTC_DR_DT_1 0x00000020U |
| #define | RTC_DR_DU 0x0000000FU |
| #define | RTC_DR_DU_0 0x00000001U |
| #define | RTC_DR_DU_1 0x00000002U |
| #define | RTC_DR_DU_2 0x00000004U |
| #define | RTC_DR_DU_3 0x00000008U |
| #define | RTC_CR_COE 0x00800000U |
| #define | RTC_CR_OSEL 0x00600000U |
| #define | RTC_CR_OSEL_0 0x00200000U |
| #define | RTC_CR_OSEL_1 0x00400000U |
| #define | RTC_CR_POL 0x00100000U |
| #define | RTC_CR_COSEL 0x00080000U |
| #define | RTC_CR_BCK 0x00040000U |
| #define | RTC_CR_SUB1H 0x00020000U |
| #define | RTC_CR_ADD1H 0x00010000U |
| #define | RTC_CR_TSIE 0x00008000U |
| #define | RTC_CR_WUTIE 0x00004000U |
| #define | RTC_CR_ALRBIE 0x00002000U |
| #define | RTC_CR_ALRAIE 0x00001000U |
| #define | RTC_CR_TSE 0x00000800U |
| #define | RTC_CR_WUTE 0x00000400U |
| #define | RTC_CR_ALRBE 0x00000200U |
| #define | RTC_CR_ALRAE 0x00000100U |
| #define | RTC_CR_DCE 0x00000080U |
| #define | RTC_CR_FMT 0x00000040U |
| #define | RTC_CR_BYPSHAD 0x00000020U |
| #define | RTC_CR_REFCKON 0x00000010U |
| #define | RTC_CR_TSEDGE 0x00000008U |
| #define | RTC_CR_WUCKSEL 0x00000007U |
| #define | RTC_CR_WUCKSEL_0 0x00000001U |
| #define | RTC_CR_WUCKSEL_1 0x00000002U |
| #define | RTC_CR_WUCKSEL_2 0x00000004U |
| #define | RTC_ISR_RECALPF 0x00010000U |
| #define | RTC_ISR_TAMP1F 0x00002000U |
| #define | RTC_ISR_TAMP2F 0x00004000U |
| #define | RTC_ISR_TSOVF 0x00001000U |
| #define | RTC_ISR_TSF 0x00000800U |
| #define | RTC_ISR_WUTF 0x00000400U |
| #define | RTC_ISR_ALRBF 0x00000200U |
| #define | RTC_ISR_ALRAF 0x00000100U |
| #define | RTC_ISR_INIT 0x00000080U |
| #define | RTC_ISR_INITF 0x00000040U |
| #define | RTC_ISR_RSF 0x00000020U |
| #define | RTC_ISR_INITS 0x00000010U |
| #define | RTC_ISR_SHPF 0x00000008U |
| #define | RTC_ISR_WUTWF 0x00000004U |
| #define | RTC_ISR_ALRBWF 0x00000002U |
| #define | RTC_ISR_ALRAWF 0x00000001U |
| #define | RTC_PRER_PREDIV_A 0x007F0000U |
| #define | RTC_PRER_PREDIV_S 0x00007FFFU |
| #define | RTC_WUTR_WUT 0x0000FFFFU |
| #define | RTC_CALIBR_DCS 0x00000080U |
| #define | RTC_CALIBR_DC 0x0000001FU |
| #define | RTC_ALRMAR_MSK4 0x80000000U |
| #define | RTC_ALRMAR_WDSEL 0x40000000U |
| #define | RTC_ALRMAR_DT 0x30000000U |
| #define | RTC_ALRMAR_DT_0 0x10000000U |
| #define | RTC_ALRMAR_DT_1 0x20000000U |
| #define | RTC_ALRMAR_DU 0x0F000000U |
| #define | RTC_ALRMAR_DU_0 0x01000000U |
| #define | RTC_ALRMAR_DU_1 0x02000000U |
| #define | RTC_ALRMAR_DU_2 0x04000000U |
| #define | RTC_ALRMAR_DU_3 0x08000000U |
| #define | RTC_ALRMAR_MSK3 0x00800000U |
| #define | RTC_ALRMAR_PM 0x00400000U |
| #define | RTC_ALRMAR_HT 0x00300000U |
| #define | RTC_ALRMAR_HT_0 0x00100000U |
| #define | RTC_ALRMAR_HT_1 0x00200000U |
| #define | RTC_ALRMAR_HU 0x000F0000U |
| #define | RTC_ALRMAR_HU_0 0x00010000U |
| #define | RTC_ALRMAR_HU_1 0x00020000U |
| #define | RTC_ALRMAR_HU_2 0x00040000U |
| #define | RTC_ALRMAR_HU_3 0x00080000U |
| #define | RTC_ALRMAR_MSK2 0x00008000U |
| #define | RTC_ALRMAR_MNT 0x00007000U |
| #define | RTC_ALRMAR_MNT_0 0x00001000U |
| #define | RTC_ALRMAR_MNT_1 0x00002000U |
| #define | RTC_ALRMAR_MNT_2 0x00004000U |
| #define | RTC_ALRMAR_MNU 0x00000F00U |
| #define | RTC_ALRMAR_MNU_0 0x00000100U |
| #define | RTC_ALRMAR_MNU_1 0x00000200U |
| #define | RTC_ALRMAR_MNU_2 0x00000400U |
| #define | RTC_ALRMAR_MNU_3 0x00000800U |
| #define | RTC_ALRMAR_MSK1 0x00000080U |
| #define | RTC_ALRMAR_ST 0x00000070U |
| #define | RTC_ALRMAR_ST_0 0x00000010U |
| #define | RTC_ALRMAR_ST_1 0x00000020U |
| #define | RTC_ALRMAR_ST_2 0x00000040U |
| #define | RTC_ALRMAR_SU 0x0000000FU |
| #define | RTC_ALRMAR_SU_0 0x00000001U |
| #define | RTC_ALRMAR_SU_1 0x00000002U |
| #define | RTC_ALRMAR_SU_2 0x00000004U |
| #define | RTC_ALRMAR_SU_3 0x00000008U |
| #define | RTC_ALRMBR_MSK4 0x80000000U |
| #define | RTC_ALRMBR_WDSEL 0x40000000U |
| #define | RTC_ALRMBR_DT 0x30000000U |
| #define | RTC_ALRMBR_DT_0 0x10000000U |
| #define | RTC_ALRMBR_DT_1 0x20000000U |
| #define | RTC_ALRMBR_DU 0x0F000000U |
| #define | RTC_ALRMBR_DU_0 0x01000000U |
| #define | RTC_ALRMBR_DU_1 0x02000000U |
| #define | RTC_ALRMBR_DU_2 0x04000000U |
| #define | RTC_ALRMBR_DU_3 0x08000000U |
| #define | RTC_ALRMBR_MSK3 0x00800000U |
| #define | RTC_ALRMBR_PM 0x00400000U |
| #define | RTC_ALRMBR_HT 0x00300000U |
| #define | RTC_ALRMBR_HT_0 0x00100000U |
| #define | RTC_ALRMBR_HT_1 0x00200000U |
| #define | RTC_ALRMBR_HU 0x000F0000U |
| #define | RTC_ALRMBR_HU_0 0x00010000U |
| #define | RTC_ALRMBR_HU_1 0x00020000U |
| #define | RTC_ALRMBR_HU_2 0x00040000U |
| #define | RTC_ALRMBR_HU_3 0x00080000U |
| #define | RTC_ALRMBR_MSK2 0x00008000U |
| #define | RTC_ALRMBR_MNT 0x00007000U |
| #define | RTC_ALRMBR_MNT_0 0x00001000U |
| #define | RTC_ALRMBR_MNT_1 0x00002000U |
| #define | RTC_ALRMBR_MNT_2 0x00004000U |
| #define | RTC_ALRMBR_MNU 0x00000F00U |
| #define | RTC_ALRMBR_MNU_0 0x00000100U |
| #define | RTC_ALRMBR_MNU_1 0x00000200U |
| #define | RTC_ALRMBR_MNU_2 0x00000400U |
| #define | RTC_ALRMBR_MNU_3 0x00000800U |
| #define | RTC_ALRMBR_MSK1 0x00000080U |
| #define | RTC_ALRMBR_ST 0x00000070U |
| #define | RTC_ALRMBR_ST_0 0x00000010U |
| #define | RTC_ALRMBR_ST_1 0x00000020U |
| #define | RTC_ALRMBR_ST_2 0x00000040U |
| #define | RTC_ALRMBR_SU 0x0000000FU |
| #define | RTC_ALRMBR_SU_0 0x00000001U |
| #define | RTC_ALRMBR_SU_1 0x00000002U |
| #define | RTC_ALRMBR_SU_2 0x00000004U |
| #define | RTC_ALRMBR_SU_3 0x00000008U |
| #define | RTC_WPR_KEY 0x000000FFU |
| #define | RTC_SSR_SS 0x0000FFFFU |
| #define | RTC_SHIFTR_SUBFS 0x00007FFFU |
| #define | RTC_SHIFTR_ADD1S 0x80000000U |
| #define | RTC_TSTR_PM 0x00400000U |
| #define | RTC_TSTR_HT 0x00300000U |
| #define | RTC_TSTR_HT_0 0x00100000U |
| #define | RTC_TSTR_HT_1 0x00200000U |
| #define | RTC_TSTR_HU 0x000F0000U |
| #define | RTC_TSTR_HU_0 0x00010000U |
| #define | RTC_TSTR_HU_1 0x00020000U |
| #define | RTC_TSTR_HU_2 0x00040000U |
| #define | RTC_TSTR_HU_3 0x00080000U |
| #define | RTC_TSTR_MNT 0x00007000U |
| #define | RTC_TSTR_MNT_0 0x00001000U |
| #define | RTC_TSTR_MNT_1 0x00002000U |
| #define | RTC_TSTR_MNT_2 0x00004000U |
| #define | RTC_TSTR_MNU 0x00000F00U |
| #define | RTC_TSTR_MNU_0 0x00000100U |
| #define | RTC_TSTR_MNU_1 0x00000200U |
| #define | RTC_TSTR_MNU_2 0x00000400U |
| #define | RTC_TSTR_MNU_3 0x00000800U |
| #define | RTC_TSTR_ST 0x00000070U |
| #define | RTC_TSTR_ST_0 0x00000010U |
| #define | RTC_TSTR_ST_1 0x00000020U |
| #define | RTC_TSTR_ST_2 0x00000040U |
| #define | RTC_TSTR_SU 0x0000000FU |
| #define | RTC_TSTR_SU_0 0x00000001U |
| #define | RTC_TSTR_SU_1 0x00000002U |
| #define | RTC_TSTR_SU_2 0x00000004U |
| #define | RTC_TSTR_SU_3 0x00000008U |
| #define | RTC_TSDR_WDU 0x0000E000U |
| #define | RTC_TSDR_WDU_0 0x00002000U |
| #define | RTC_TSDR_WDU_1 0x00004000U |
| #define | RTC_TSDR_WDU_2 0x00008000U |
| #define | RTC_TSDR_MT 0x00001000U |
| #define | RTC_TSDR_MU 0x00000F00U |
| #define | RTC_TSDR_MU_0 0x00000100U |
| #define | RTC_TSDR_MU_1 0x00000200U |
| #define | RTC_TSDR_MU_2 0x00000400U |
| #define | RTC_TSDR_MU_3 0x00000800U |
| #define | RTC_TSDR_DT 0x00000030U |
| #define | RTC_TSDR_DT_0 0x00000010U |
| #define | RTC_TSDR_DT_1 0x00000020U |
| #define | RTC_TSDR_DU 0x0000000FU |
| #define | RTC_TSDR_DU_0 0x00000001U |
| #define | RTC_TSDR_DU_1 0x00000002U |
| #define | RTC_TSDR_DU_2 0x00000004U |
| #define | RTC_TSDR_DU_3 0x00000008U |
| #define | RTC_TSSSR_SS 0x0000FFFFU |
| #define | RTC_CALR_CALP 0x00008000U |
| #define | RTC_CALR_CALW8 0x00004000U |
| #define | RTC_CALR_CALW16 0x00002000U |
| #define | RTC_CALR_CALM 0x000001FFU |
| #define | RTC_CALR_CALM_0 0x00000001U |
| #define | RTC_CALR_CALM_1 0x00000002U |
| #define | RTC_CALR_CALM_2 0x00000004U |
| #define | RTC_CALR_CALM_3 0x00000008U |
| #define | RTC_CALR_CALM_4 0x00000010U |
| #define | RTC_CALR_CALM_5 0x00000020U |
| #define | RTC_CALR_CALM_6 0x00000040U |
| #define | RTC_CALR_CALM_7 0x00000080U |
| #define | RTC_CALR_CALM_8 0x00000100U |
| #define | RTC_TAFCR_ALARMOUTTYPE 0x00040000U |
| #define | RTC_TAFCR_TSINSEL 0x00020000U |
| #define | RTC_TAFCR_TAMPINSEL 0x00010000U |
| #define | RTC_TAFCR_TAMPPUDIS 0x00008000U |
| #define | RTC_TAFCR_TAMPPRCH 0x00006000U |
| #define | RTC_TAFCR_TAMPPRCH_0 0x00002000U |
| #define | RTC_TAFCR_TAMPPRCH_1 0x00004000U |
| #define | RTC_TAFCR_TAMPFLT 0x00001800U |
| #define | RTC_TAFCR_TAMPFLT_0 0x00000800U |
| #define | RTC_TAFCR_TAMPFLT_1 0x00001000U |
| #define | RTC_TAFCR_TAMPFREQ 0x00000700U |
| #define | RTC_TAFCR_TAMPFREQ_0 0x00000100U |
| #define | RTC_TAFCR_TAMPFREQ_1 0x00000200U |
| #define | RTC_TAFCR_TAMPFREQ_2 0x00000400U |
| #define | RTC_TAFCR_TAMPTS 0x00000080U |
| #define | RTC_TAFCR_TAMP2TRG 0x00000010U |
| #define | RTC_TAFCR_TAMP2E 0x00000008U |
| #define | RTC_TAFCR_TAMPIE 0x00000004U |
| #define | RTC_TAFCR_TAMP1TRG 0x00000002U |
| #define | RTC_TAFCR_TAMP1E 0x00000001U |
| #define | RTC_ALRMASSR_MASKSS 0x0F000000U |
| #define | RTC_ALRMASSR_MASKSS_0 0x01000000U |
| #define | RTC_ALRMASSR_MASKSS_1 0x02000000U |
| #define | RTC_ALRMASSR_MASKSS_2 0x04000000U |
| #define | RTC_ALRMASSR_MASKSS_3 0x08000000U |
| #define | RTC_ALRMASSR_SS 0x00007FFFU |
| #define | RTC_ALRMBSSR_MASKSS 0x0F000000U |
| #define | RTC_ALRMBSSR_MASKSS_0 0x01000000U |
| #define | RTC_ALRMBSSR_MASKSS_1 0x02000000U |
| #define | RTC_ALRMBSSR_MASKSS_2 0x04000000U |
| #define | RTC_ALRMBSSR_MASKSS_3 0x08000000U |
| #define | RTC_ALRMBSSR_SS 0x00007FFFU |
| #define | RTC_BKP0R 0xFFFFFFFFU |
| #define | RTC_BKP1R 0xFFFFFFFFU |
| #define | RTC_BKP2R 0xFFFFFFFFU |
| #define | RTC_BKP3R 0xFFFFFFFFU |
| #define | RTC_BKP4R 0xFFFFFFFFU |
| #define | RTC_BKP5R 0xFFFFFFFFU |
| #define | RTC_BKP6R 0xFFFFFFFFU |
| #define | RTC_BKP7R 0xFFFFFFFFU |
| #define | RTC_BKP8R 0xFFFFFFFFU |
| #define | RTC_BKP9R 0xFFFFFFFFU |
| #define | RTC_BKP10R 0xFFFFFFFFU |
| #define | RTC_BKP11R 0xFFFFFFFFU |
| #define | RTC_BKP12R 0xFFFFFFFFU |
| #define | RTC_BKP13R 0xFFFFFFFFU |
| #define | RTC_BKP14R 0xFFFFFFFFU |
| #define | RTC_BKP15R 0xFFFFFFFFU |
| #define | RTC_BKP16R 0xFFFFFFFFU |
| #define | RTC_BKP17R 0xFFFFFFFFU |
| #define | RTC_BKP18R 0xFFFFFFFFU |
| #define | RTC_BKP19R 0xFFFFFFFFU |
| #define | SDIO_POWER_PWRCTRL 0x03U |
| #define | SDIO_POWER_PWRCTRL_0 0x01U |
| #define | SDIO_POWER_PWRCTRL_1 0x02U |
| #define | SDIO_CLKCR_CLKDIV 0x00FFU |
| #define | SDIO_CLKCR_CLKEN 0x0100U |
| #define | SDIO_CLKCR_PWRSAV 0x0200U |
| #define | SDIO_CLKCR_BYPASS 0x0400U |
| #define | SDIO_CLKCR_WIDBUS 0x1800U |
| #define | SDIO_CLKCR_WIDBUS_0 0x0800U |
| #define | SDIO_CLKCR_WIDBUS_1 0x1000U |
| #define | SDIO_CLKCR_NEGEDGE 0x2000U |
| #define | SDIO_CLKCR_HWFC_EN 0x4000U |
| #define | SDIO_ARG_CMDARG 0xFFFFFFFFU |
| #define | SDIO_CMD_CMDINDEX 0x003FU |
| #define | SDIO_CMD_WAITRESP 0x00C0U |
| #define | SDIO_CMD_WAITRESP_0 0x0040U |
| #define | SDIO_CMD_WAITRESP_1 0x0080U |
| #define | SDIO_CMD_WAITINT 0x0100U |
| #define | SDIO_CMD_WAITPEND 0x0200U |
| #define | SDIO_CMD_CPSMEN 0x0400U |
| #define | SDIO_CMD_SDIOSUSPEND 0x0800U |
| #define | SDIO_CMD_ENCMDCOMPL 0x1000U |
| #define | SDIO_CMD_NIEN 0x2000U |
| #define | SDIO_CMD_CEATACMD 0x4000U |
| #define | SDIO_RESPCMD_RESPCMD 0x3FU |
| #define | SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU |
| #define | SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU |
| #define | SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU |
| #define | SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU |
| #define | SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU |
| #define | SDIO_DTIMER_DATATIME 0xFFFFFFFFU |
| #define | SDIO_DLEN_DATALENGTH 0x01FFFFFFU |
| #define | SDIO_DCTRL_DTEN 0x0001U |
| #define | SDIO_DCTRL_DTDIR 0x0002U |
| #define | SDIO_DCTRL_DTMODE 0x0004U |
| #define | SDIO_DCTRL_DMAEN 0x0008U |
| #define | SDIO_DCTRL_DBLOCKSIZE 0x00F0U |
| #define | SDIO_DCTRL_DBLOCKSIZE_0 0x0010U |
| #define | SDIO_DCTRL_DBLOCKSIZE_1 0x0020U |
| #define | SDIO_DCTRL_DBLOCKSIZE_2 0x0040U |
| #define | SDIO_DCTRL_DBLOCKSIZE_3 0x0080U |
| #define | SDIO_DCTRL_RWSTART 0x0100U |
| #define | SDIO_DCTRL_RWSTOP 0x0200U |
| #define | SDIO_DCTRL_RWMOD 0x0400U |
| #define | SDIO_DCTRL_SDIOEN 0x0800U |
| #define | SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU |
| #define | SDIO_STA_CCRCFAIL 0x00000001U |
| #define | SDIO_STA_DCRCFAIL 0x00000002U |
| #define | SDIO_STA_CTIMEOUT 0x00000004U |
| #define | SDIO_STA_DTIMEOUT 0x00000008U |
| #define | SDIO_STA_TXUNDERR 0x00000010U |
| #define | SDIO_STA_RXOVERR 0x00000020U |
| #define | SDIO_STA_CMDREND 0x00000040U |
| #define | SDIO_STA_CMDSENT 0x00000080U |
| #define | SDIO_STA_DATAEND 0x00000100U |
| #define | SDIO_STA_STBITERR 0x00000200U |
| #define | SDIO_STA_DBCKEND 0x00000400U |
| #define | SDIO_STA_CMDACT 0x00000800U |
| #define | SDIO_STA_TXACT 0x00001000U |
| #define | SDIO_STA_RXACT 0x00002000U |
| #define | SDIO_STA_TXFIFOHE 0x00004000U |
| #define | SDIO_STA_RXFIFOHF 0x00008000U |
| #define | SDIO_STA_TXFIFOF 0x00010000U |
| #define | SDIO_STA_RXFIFOF 0x00020000U |
| #define | SDIO_STA_TXFIFOE 0x00040000U |
| #define | SDIO_STA_RXFIFOE 0x00080000U |
| #define | SDIO_STA_TXDAVL 0x00100000U |
| #define | SDIO_STA_RXDAVL 0x00200000U |
| #define | SDIO_STA_SDIOIT 0x00400000U |
| #define | SDIO_STA_CEATAEND 0x00800000U |
| #define | SDIO_ICR_CCRCFAILC 0x00000001U |
| #define | SDIO_ICR_DCRCFAILC 0x00000002U |
| #define | SDIO_ICR_CTIMEOUTC 0x00000004U |
| #define | SDIO_ICR_DTIMEOUTC 0x00000008U |
| #define | SDIO_ICR_TXUNDERRC 0x00000010U |
| #define | SDIO_ICR_RXOVERRC 0x00000020U |
| #define | SDIO_ICR_CMDRENDC 0x00000040U |
| #define | SDIO_ICR_CMDSENTC 0x00000080U |
| #define | SDIO_ICR_DATAENDC 0x00000100U |
| #define | SDIO_ICR_STBITERRC 0x00000200U |
| #define | SDIO_ICR_DBCKENDC 0x00000400U |
| #define | SDIO_ICR_SDIOITC 0x00400000U |
| #define | SDIO_ICR_CEATAENDC 0x00800000U |
| #define | SDIO_MASK_CCRCFAILIE 0x00000001U |
| #define | SDIO_MASK_DCRCFAILIE 0x00000002U |
| #define | SDIO_MASK_CTIMEOUTIE 0x00000004U |
| #define | SDIO_MASK_DTIMEOUTIE 0x00000008U |
| #define | SDIO_MASK_TXUNDERRIE 0x00000010U |
| #define | SDIO_MASK_RXOVERRIE 0x00000020U |
| #define | SDIO_MASK_CMDRENDIE 0x00000040U |
| #define | SDIO_MASK_CMDSENTIE 0x00000080U |
| #define | SDIO_MASK_DATAENDIE 0x00000100U |
| #define | SDIO_MASK_STBITERRIE 0x00000200U |
| #define | SDIO_MASK_DBCKENDIE 0x00000400U |
| #define | SDIO_MASK_CMDACTIE 0x00000800U |
| #define | SDIO_MASK_TXACTIE 0x00001000U |
| #define | SDIO_MASK_RXACTIE 0x00002000U |
| #define | SDIO_MASK_TXFIFOHEIE 0x00004000U |
| #define | SDIO_MASK_RXFIFOHFIE 0x00008000U |
| #define | SDIO_MASK_TXFIFOFIE 0x00010000U |
| #define | SDIO_MASK_RXFIFOFIE 0x00020000U |
| #define | SDIO_MASK_TXFIFOEIE 0x00040000U |
| #define | SDIO_MASK_RXFIFOEIE 0x00080000U |
| #define | SDIO_MASK_TXDAVLIE 0x00100000U |
| #define | SDIO_MASK_RXDAVLIE 0x00200000U |
| #define | SDIO_MASK_SDIOITIE 0x00400000U |
| #define | SDIO_MASK_CEATAENDIE 0x00800000U |
| #define | SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU |
| #define | SDIO_FIFO_FIFODATA 0xFFFFFFFFU |
| #define | SPI_CR1_CPHA 0x00000001U |
| #define | SPI_CR1_CPOL 0x00000002U |
| #define | SPI_CR1_MSTR 0x00000004U |
| #define | SPI_CR1_BR 0x00000038U |
| #define | SPI_CR1_BR_0 0x00000008U |
| #define | SPI_CR1_BR_1 0x00000010U |
| #define | SPI_CR1_BR_2 0x00000020U |
| #define | SPI_CR1_SPE 0x00000040U |
| #define | SPI_CR1_LSBFIRST 0x00000080U |
| #define | SPI_CR1_SSI 0x00000100U |
| #define | SPI_CR1_SSM 0x00000200U |
| #define | SPI_CR1_RXONLY 0x00000400U |
| #define | SPI_CR1_DFF 0x00000800U |
| #define | SPI_CR1_CRCNEXT 0x00001000U |
| #define | SPI_CR1_CRCEN 0x00002000U |
| #define | SPI_CR1_BIDIOE 0x00004000U |
| #define | SPI_CR1_BIDIMODE 0x00008000U |
| #define | SPI_CR2_RXDMAEN 0x00000001U |
| #define | SPI_CR2_TXDMAEN 0x00000002U |
| #define | SPI_CR2_SSOE 0x00000004U |
| #define | SPI_CR2_FRF 0x00000010U |
| #define | SPI_CR2_ERRIE 0x00000020U |
| #define | SPI_CR2_RXNEIE 0x00000040U |
| #define | SPI_CR2_TXEIE 0x00000080U |
| #define | SPI_SR_RXNE 0x00000001U |
| #define | SPI_SR_TXE 0x00000002U |
| #define | SPI_SR_CHSIDE 0x00000004U |
| #define | SPI_SR_UDR 0x00000008U |
| #define | SPI_SR_CRCERR 0x00000010U |
| #define | SPI_SR_MODF 0x00000020U |
| #define | SPI_SR_OVR 0x00000040U |
| #define | SPI_SR_BSY 0x00000080U |
| #define | SPI_SR_FRE 0x00000100U |
| #define | SPI_DR_DR 0x0000FFFFU |
| #define | SPI_CRCPR_CRCPOLY 0x0000FFFFU |
| #define | SPI_RXCRCR_RXCRC 0x0000FFFFU |
| #define | SPI_TXCRCR_TXCRC 0x0000FFFFU |
| #define | SPI_I2SCFGR_CHLEN 0x00000001U |
| #define | SPI_I2SCFGR_DATLEN 0x00000006U |
| #define | SPI_I2SCFGR_DATLEN_0 0x00000002U |
| #define | SPI_I2SCFGR_DATLEN_1 0x00000004U |
| #define | SPI_I2SCFGR_CKPOL 0x00000008U |
| #define | SPI_I2SCFGR_I2SSTD 0x00000030U |
| #define | SPI_I2SCFGR_I2SSTD_0 0x00000010U |
| #define | SPI_I2SCFGR_I2SSTD_1 0x00000020U |
| #define | SPI_I2SCFGR_PCMSYNC 0x00000080U |
| #define | SPI_I2SCFGR_I2SCFG 0x00000300U |
| #define | SPI_I2SCFGR_I2SCFG_0 0x00000100U |
| #define | SPI_I2SCFGR_I2SCFG_1 0x00000200U |
| #define | SPI_I2SCFGR_I2SE 0x00000400U |
| #define | SPI_I2SCFGR_I2SMOD 0x00000800U |
| #define | SPI_I2SPR_I2SDIV 0x000000FFU |
| #define | SPI_I2SPR_ODD 0x00000100U |
| #define | SPI_I2SPR_MCKOE 0x00000200U |
| #define | SYSCFG_MEMRMP_MEM_MODE 0x00000007U |
| #define | SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U |
| #define | SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U |
| #define | SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U |
| #define | SYSCFG_PMC_MII_RMII_SEL 0x00800000U |
| #define | SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL |
| #define | SYSCFG_EXTICR1_EXTI0 0x000FU |
| #define | SYSCFG_EXTICR1_EXTI1 0x00F0U |
| #define | SYSCFG_EXTICR1_EXTI2 0x0F00U |
| #define | SYSCFG_EXTICR1_EXTI3 0xF000U |
| #define | SYSCFG_EXTICR1_EXTI0_PA 0x0000U |
| EXTI0 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI0_PB 0x0001U |
| #define | SYSCFG_EXTICR1_EXTI0_PC 0x0002U |
| #define | SYSCFG_EXTICR1_EXTI0_PD 0x0003U |
| #define | SYSCFG_EXTICR1_EXTI0_PE 0x0004U |
| #define | SYSCFG_EXTICR1_EXTI0_PF 0x0005U |
| #define | SYSCFG_EXTICR1_EXTI0_PG 0x0006U |
| #define | SYSCFG_EXTICR1_EXTI0_PH 0x0007U |
| #define | SYSCFG_EXTICR1_EXTI0_PI 0x0008U |
| #define | SYSCFG_EXTICR1_EXTI1_PA 0x0000U |
| EXTI1 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI1_PB 0x0010U |
| #define | SYSCFG_EXTICR1_EXTI1_PC 0x0020U |
| #define | SYSCFG_EXTICR1_EXTI1_PD 0x0030U |
| #define | SYSCFG_EXTICR1_EXTI1_PE 0x0040U |
| #define | SYSCFG_EXTICR1_EXTI1_PF 0x0050U |
| #define | SYSCFG_EXTICR1_EXTI1_PG 0x0060U |
| #define | SYSCFG_EXTICR1_EXTI1_PH 0x0070U |
| #define | SYSCFG_EXTICR1_EXTI1_PI 0x0080U |
| #define | SYSCFG_EXTICR1_EXTI2_PA 0x0000U |
| EXTI2 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI2_PB 0x0100U |
| #define | SYSCFG_EXTICR1_EXTI2_PC 0x0200U |
| #define | SYSCFG_EXTICR1_EXTI2_PD 0x0300U |
| #define | SYSCFG_EXTICR1_EXTI2_PE 0x0400U |
| #define | SYSCFG_EXTICR1_EXTI2_PF 0x0500U |
| #define | SYSCFG_EXTICR1_EXTI2_PG 0x0600U |
| #define | SYSCFG_EXTICR1_EXTI2_PH 0x0700U |
| #define | SYSCFG_EXTICR1_EXTI2_PI 0x0800U |
| #define | SYSCFG_EXTICR1_EXTI3_PA 0x0000U |
| EXTI3 configuration More... | |
| #define | SYSCFG_EXTICR1_EXTI3_PB 0x1000U |
| #define | SYSCFG_EXTICR1_EXTI3_PC 0x2000U |
| #define | SYSCFG_EXTICR1_EXTI3_PD 0x3000U |
| #define | SYSCFG_EXTICR1_EXTI3_PE 0x4000U |
| #define | SYSCFG_EXTICR1_EXTI3_PF 0x5000U |
| #define | SYSCFG_EXTICR1_EXTI3_PG 0x6000U |
| #define | SYSCFG_EXTICR1_EXTI3_PH 0x7000U |
| #define | SYSCFG_EXTICR1_EXTI3_PI 0x8000U |
| #define | SYSCFG_EXTICR2_EXTI4 0x000FU |
| #define | SYSCFG_EXTICR2_EXTI5 0x00F0U |
| #define | SYSCFG_EXTICR2_EXTI6 0x0F00U |
| #define | SYSCFG_EXTICR2_EXTI7 0xF000U |
| #define | SYSCFG_EXTICR2_EXTI4_PA 0x0000U |
| EXTI4 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI4_PB 0x0001U |
| #define | SYSCFG_EXTICR2_EXTI4_PC 0x0002U |
| #define | SYSCFG_EXTICR2_EXTI4_PD 0x0003U |
| #define | SYSCFG_EXTICR2_EXTI4_PE 0x0004U |
| #define | SYSCFG_EXTICR2_EXTI4_PF 0x0005U |
| #define | SYSCFG_EXTICR2_EXTI4_PG 0x0006U |
| #define | SYSCFG_EXTICR2_EXTI4_PH 0x0007U |
| #define | SYSCFG_EXTICR2_EXTI4_PI 0x0008U |
| #define | SYSCFG_EXTICR2_EXTI5_PA 0x0000U |
| EXTI5 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI5_PB 0x0010U |
| #define | SYSCFG_EXTICR2_EXTI5_PC 0x0020U |
| #define | SYSCFG_EXTICR2_EXTI5_PD 0x0030U |
| #define | SYSCFG_EXTICR2_EXTI5_PE 0x0040U |
| #define | SYSCFG_EXTICR2_EXTI5_PF 0x0050U |
| #define | SYSCFG_EXTICR2_EXTI5_PG 0x0060U |
| #define | SYSCFG_EXTICR2_EXTI5_PH 0x0070U |
| #define | SYSCFG_EXTICR2_EXTI5_PI 0x0080U |
| #define | SYSCFG_EXTICR2_EXTI6_PA 0x0000U |
| EXTI6 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI6_PB 0x0100U |
| #define | SYSCFG_EXTICR2_EXTI6_PC 0x0200U |
| #define | SYSCFG_EXTICR2_EXTI6_PD 0x0300U |
| #define | SYSCFG_EXTICR2_EXTI6_PE 0x0400U |
| #define | SYSCFG_EXTICR2_EXTI6_PF 0x0500U |
| #define | SYSCFG_EXTICR2_EXTI6_PG 0x0600U |
| #define | SYSCFG_EXTICR2_EXTI6_PH 0x0700U |
| #define | SYSCFG_EXTICR2_EXTI6_PI 0x0800U |
| #define | SYSCFG_EXTICR2_EXTI7_PA 0x0000U |
| EXTI7 configuration More... | |
| #define | SYSCFG_EXTICR2_EXTI7_PB 0x1000U |
| #define | SYSCFG_EXTICR2_EXTI7_PC 0x2000U |
| #define | SYSCFG_EXTICR2_EXTI7_PD 0x3000U |
| #define | SYSCFG_EXTICR2_EXTI7_PE 0x4000U |
| #define | SYSCFG_EXTICR2_EXTI7_PF 0x5000U |
| #define | SYSCFG_EXTICR2_EXTI7_PG 0x6000U |
| #define | SYSCFG_EXTICR2_EXTI7_PH 0x7000U |
| #define | SYSCFG_EXTICR2_EXTI7_PI 0x8000U |
| #define | SYSCFG_EXTICR3_EXTI8 0x000FU |
| #define | SYSCFG_EXTICR3_EXTI9 0x00F0U |
| #define | SYSCFG_EXTICR3_EXTI10 0x0F00U |
| #define | SYSCFG_EXTICR3_EXTI11 0xF000U |
| #define | SYSCFG_EXTICR3_EXTI8_PA 0x0000U |
| EXTI8 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI8_PB 0x0001U |
| #define | SYSCFG_EXTICR3_EXTI8_PC 0x0002U |
| #define | SYSCFG_EXTICR3_EXTI8_PD 0x0003U |
| #define | SYSCFG_EXTICR3_EXTI8_PE 0x0004U |
| #define | SYSCFG_EXTICR3_EXTI8_PF 0x0005U |
| #define | SYSCFG_EXTICR3_EXTI8_PG 0x0006U |
| #define | SYSCFG_EXTICR3_EXTI8_PH 0x0007U |
| #define | SYSCFG_EXTICR3_EXTI8_PI 0x0008U |
| #define | SYSCFG_EXTICR3_EXTI9_PA 0x0000U |
| EXTI9 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI9_PB 0x0010U |
| #define | SYSCFG_EXTICR3_EXTI9_PC 0x0020U |
| #define | SYSCFG_EXTICR3_EXTI9_PD 0x0030U |
| #define | SYSCFG_EXTICR3_EXTI9_PE 0x0040U |
| #define | SYSCFG_EXTICR3_EXTI9_PF 0x0050U |
| #define | SYSCFG_EXTICR3_EXTI9_PG 0x0060U |
| #define | SYSCFG_EXTICR3_EXTI9_PH 0x0070U |
| #define | SYSCFG_EXTICR3_EXTI9_PI 0x0080U |
| #define | SYSCFG_EXTICR3_EXTI10_PA 0x0000U |
| EXTI10 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI10_PB 0x0100U |
| #define | SYSCFG_EXTICR3_EXTI10_PC 0x0200U |
| #define | SYSCFG_EXTICR3_EXTI10_PD 0x0300U |
| #define | SYSCFG_EXTICR3_EXTI10_PE 0x0400U |
| #define | SYSCFG_EXTICR3_EXTI10_PF 0x0500U |
| #define | SYSCFG_EXTICR3_EXTI10_PG 0x0600U |
| #define | SYSCFG_EXTICR3_EXTI10_PH 0x0700U |
| #define | SYSCFG_EXTICR3_EXTI10_PI 0x0800U |
| #define | SYSCFG_EXTICR3_EXTI11_PA 0x0000U |
| EXTI11 configuration More... | |
| #define | SYSCFG_EXTICR3_EXTI11_PB 0x1000U |
| #define | SYSCFG_EXTICR3_EXTI11_PC 0x2000U |
| #define | SYSCFG_EXTICR3_EXTI11_PD 0x3000U |
| #define | SYSCFG_EXTICR3_EXTI11_PE 0x4000U |
| #define | SYSCFG_EXTICR3_EXTI11_PF 0x5000U |
| #define | SYSCFG_EXTICR3_EXTI11_PG 0x6000U |
| #define | SYSCFG_EXTICR3_EXTI11_PH 0x7000U |
| #define | SYSCFG_EXTICR3_EXTI11_PI 0x8000U |
| #define | SYSCFG_EXTICR4_EXTI12 0x000FU |
| #define | SYSCFG_EXTICR4_EXTI13 0x00F0U |
| #define | SYSCFG_EXTICR4_EXTI14 0x0F00U |
| #define | SYSCFG_EXTICR4_EXTI15 0xF000U |
| #define | SYSCFG_EXTICR4_EXTI12_PA 0x0000U |
| EXTI12 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI12_PB 0x0001U |
| #define | SYSCFG_EXTICR4_EXTI12_PC 0x0002U |
| #define | SYSCFG_EXTICR4_EXTI12_PD 0x0003U |
| #define | SYSCFG_EXTICR4_EXTI12_PE 0x0004U |
| #define | SYSCFG_EXTICR4_EXTI12_PF 0x0005U |
| #define | SYSCFG_EXTICR4_EXTI12_PG 0x0006U |
| #define | SYSCFG_EXTICR4_EXTI12_PH 0x0007U |
| #define | SYSCFG_EXTICR4_EXTI13_PA 0x0000U |
| EXTI13 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI13_PB 0x0010U |
| #define | SYSCFG_EXTICR4_EXTI13_PC 0x0020U |
| #define | SYSCFG_EXTICR4_EXTI13_PD 0x0030U |
| #define | SYSCFG_EXTICR4_EXTI13_PE 0x0040U |
| #define | SYSCFG_EXTICR4_EXTI13_PF 0x0050U |
| #define | SYSCFG_EXTICR4_EXTI13_PG 0x0060U |
| #define | SYSCFG_EXTICR4_EXTI13_PH 0x0070U |
| #define | SYSCFG_EXTICR4_EXTI14_PA 0x0000U |
| EXTI14 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI14_PB 0x0100U |
| #define | SYSCFG_EXTICR4_EXTI14_PC 0x0200U |
| #define | SYSCFG_EXTICR4_EXTI14_PD 0x0300U |
| #define | SYSCFG_EXTICR4_EXTI14_PE 0x0400U |
| #define | SYSCFG_EXTICR4_EXTI14_PF 0x0500U |
| #define | SYSCFG_EXTICR4_EXTI14_PG 0x0600U |
| #define | SYSCFG_EXTICR4_EXTI14_PH 0x0700U |
| #define | SYSCFG_EXTICR4_EXTI15_PA 0x0000U |
| EXTI15 configuration More... | |
| #define | SYSCFG_EXTICR4_EXTI15_PB 0x1000U |
| #define | SYSCFG_EXTICR4_EXTI15_PC 0x2000U |
| #define | SYSCFG_EXTICR4_EXTI15_PD 0x3000U |
| #define | SYSCFG_EXTICR4_EXTI15_PE 0x4000U |
| #define | SYSCFG_EXTICR4_EXTI15_PF 0x5000U |
| #define | SYSCFG_EXTICR4_EXTI15_PG 0x6000U |
| #define | SYSCFG_EXTICR4_EXTI15_PH 0x7000U |
| #define | SYSCFG_CMPCR_CMP_PD 0x00000001U |
| #define | SYSCFG_CMPCR_READY 0x00000100U |
| #define | TIM_CR1_CEN 0x0001U |
| #define | TIM_CR1_UDIS 0x0002U |
| #define | TIM_CR1_URS 0x0004U |
| #define | TIM_CR1_OPM 0x0008U |
| #define | TIM_CR1_DIR 0x0010U |
| #define | TIM_CR1_CMS 0x0060U |
| #define | TIM_CR1_CMS_0 0x0020U |
| #define | TIM_CR1_CMS_1 0x0040U |
| #define | TIM_CR1_ARPE 0x0080U |
| #define | TIM_CR1_CKD 0x0300U |
| #define | TIM_CR1_CKD_0 0x0100U |
| #define | TIM_CR1_CKD_1 0x0200U |
| #define | TIM_CR2_CCPC 0x0001U |
| #define | TIM_CR2_CCUS 0x0004U |
| #define | TIM_CR2_CCDS 0x0008U |
| #define | TIM_CR2_MMS 0x0070U |
| #define | TIM_CR2_MMS_0 0x0010U |
| #define | TIM_CR2_MMS_1 0x0020U |
| #define | TIM_CR2_MMS_2 0x0040U |
| #define | TIM_CR2_TI1S 0x0080U |
| #define | TIM_CR2_OIS1 0x0100U |
| #define | TIM_CR2_OIS1N 0x0200U |
| #define | TIM_CR2_OIS2 0x0400U |
| #define | TIM_CR2_OIS2N 0x0800U |
| #define | TIM_CR2_OIS3 0x1000U |
| #define | TIM_CR2_OIS3N 0x2000U |
| #define | TIM_CR2_OIS4 0x4000U |
| #define | TIM_SMCR_SMS 0x0007U |
| #define | TIM_SMCR_SMS_0 0x0001U |
| #define | TIM_SMCR_SMS_1 0x0002U |
| #define | TIM_SMCR_SMS_2 0x0004U |
| #define | TIM_SMCR_TS 0x0070U |
| #define | TIM_SMCR_TS_0 0x0010U |
| #define | TIM_SMCR_TS_1 0x0020U |
| #define | TIM_SMCR_TS_2 0x0040U |
| #define | TIM_SMCR_MSM 0x0080U |
| #define | TIM_SMCR_ETF 0x0F00U |
| #define | TIM_SMCR_ETF_0 0x0100U |
| #define | TIM_SMCR_ETF_1 0x0200U |
| #define | TIM_SMCR_ETF_2 0x0400U |
| #define | TIM_SMCR_ETF_3 0x0800U |
| #define | TIM_SMCR_ETPS 0x3000U |
| #define | TIM_SMCR_ETPS_0 0x1000U |
| #define | TIM_SMCR_ETPS_1 0x2000U |
| #define | TIM_SMCR_ECE 0x4000U |
| #define | TIM_SMCR_ETP 0x8000U |
| #define | TIM_DIER_UIE 0x0001U |
| #define | TIM_DIER_CC1IE 0x0002U |
| #define | TIM_DIER_CC2IE 0x0004U |
| #define | TIM_DIER_CC3IE 0x0008U |
| #define | TIM_DIER_CC4IE 0x0010U |
| #define | TIM_DIER_COMIE 0x0020U |
| #define | TIM_DIER_TIE 0x0040U |
| #define | TIM_DIER_BIE 0x0080U |
| #define | TIM_DIER_UDE 0x0100U |
| #define | TIM_DIER_CC1DE 0x0200U |
| #define | TIM_DIER_CC2DE 0x0400U |
| #define | TIM_DIER_CC3DE 0x0800U |
| #define | TIM_DIER_CC4DE 0x1000U |
| #define | TIM_DIER_COMDE 0x2000U |
| #define | TIM_DIER_TDE 0x4000U |
| #define | TIM_SR_UIF 0x0001U |
| #define | TIM_SR_CC1IF 0x0002U |
| #define | TIM_SR_CC2IF 0x0004U |
| #define | TIM_SR_CC3IF 0x0008U |
| #define | TIM_SR_CC4IF 0x0010U |
| #define | TIM_SR_COMIF 0x0020U |
| #define | TIM_SR_TIF 0x0040U |
| #define | TIM_SR_BIF 0x0080U |
| #define | TIM_SR_CC1OF 0x0200U |
| #define | TIM_SR_CC2OF 0x0400U |
| #define | TIM_SR_CC3OF 0x0800U |
| #define | TIM_SR_CC4OF 0x1000U |
| #define | TIM_EGR_UG 0x01U |
| #define | TIM_EGR_CC1G 0x02U |
| #define | TIM_EGR_CC2G 0x04U |
| #define | TIM_EGR_CC3G 0x08U |
| #define | TIM_EGR_CC4G 0x10U |
| #define | TIM_EGR_COMG 0x20U |
| #define | TIM_EGR_TG 0x40U |
| #define | TIM_EGR_BG 0x80U |
| #define | TIM_CCMR1_CC1S 0x0003U |
| #define | TIM_CCMR1_CC1S_0 0x0001U |
| #define | TIM_CCMR1_CC1S_1 0x0002U |
| #define | TIM_CCMR1_OC1FE 0x0004U |
| #define | TIM_CCMR1_OC1PE 0x0008U |
| #define | TIM_CCMR1_OC1M 0x0070U |
| #define | TIM_CCMR1_OC1M_0 0x0010U |
| #define | TIM_CCMR1_OC1M_1 0x0020U |
| #define | TIM_CCMR1_OC1M_2 0x0040U |
| #define | TIM_CCMR1_OC1CE 0x0080U |
| #define | TIM_CCMR1_CC2S 0x0300U |
| #define | TIM_CCMR1_CC2S_0 0x0100U |
| #define | TIM_CCMR1_CC2S_1 0x0200U |
| #define | TIM_CCMR1_OC2FE 0x0400U |
| #define | TIM_CCMR1_OC2PE 0x0800U |
| #define | TIM_CCMR1_OC2M 0x7000U |
| #define | TIM_CCMR1_OC2M_0 0x1000U |
| #define | TIM_CCMR1_OC2M_1 0x2000U |
| #define | TIM_CCMR1_OC2M_2 0x4000U |
| #define | TIM_CCMR1_OC2CE 0x8000U |
| #define | TIM_CCMR1_IC1PSC 0x000CU |
| #define | TIM_CCMR1_IC1PSC_0 0x0004U |
| #define | TIM_CCMR1_IC1PSC_1 0x0008U |
| #define | TIM_CCMR1_IC1F 0x00F0U |
| #define | TIM_CCMR1_IC1F_0 0x0010U |
| #define | TIM_CCMR1_IC1F_1 0x0020U |
| #define | TIM_CCMR1_IC1F_2 0x0040U |
| #define | TIM_CCMR1_IC1F_3 0x0080U |
| #define | TIM_CCMR1_IC2PSC 0x0C00U |
| #define | TIM_CCMR1_IC2PSC_0 0x0400U |
| #define | TIM_CCMR1_IC2PSC_1 0x0800U |
| #define | TIM_CCMR1_IC2F 0xF000U |
| #define | TIM_CCMR1_IC2F_0 0x1000U |
| #define | TIM_CCMR1_IC2F_1 0x2000U |
| #define | TIM_CCMR1_IC2F_2 0x4000U |
| #define | TIM_CCMR1_IC2F_3 0x8000U |
| #define | TIM_CCMR2_CC3S 0x0003U |
| #define | TIM_CCMR2_CC3S_0 0x0001U |
| #define | TIM_CCMR2_CC3S_1 0x0002U |
| #define | TIM_CCMR2_OC3FE 0x0004U |
| #define | TIM_CCMR2_OC3PE 0x0008U |
| #define | TIM_CCMR2_OC3M 0x0070U |
| #define | TIM_CCMR2_OC3M_0 0x0010U |
| #define | TIM_CCMR2_OC3M_1 0x0020U |
| #define | TIM_CCMR2_OC3M_2 0x0040U |
| #define | TIM_CCMR2_OC3CE 0x0080U |
| #define | TIM_CCMR2_CC4S 0x0300U |
| #define | TIM_CCMR2_CC4S_0 0x0100U |
| #define | TIM_CCMR2_CC4S_1 0x0200U |
| #define | TIM_CCMR2_OC4FE 0x0400U |
| #define | TIM_CCMR2_OC4PE 0x0800U |
| #define | TIM_CCMR2_OC4M 0x7000U |
| #define | TIM_CCMR2_OC4M_0 0x1000U |
| #define | TIM_CCMR2_OC4M_1 0x2000U |
| #define | TIM_CCMR2_OC4M_2 0x4000U |
| #define | TIM_CCMR2_OC4CE 0x8000U |
| #define | TIM_CCMR2_IC3PSC 0x000CU |
| #define | TIM_CCMR2_IC3PSC_0 0x0004U |
| #define | TIM_CCMR2_IC3PSC_1 0x0008U |
| #define | TIM_CCMR2_IC3F 0x00F0U |
| #define | TIM_CCMR2_IC3F_0 0x0010U |
| #define | TIM_CCMR2_IC3F_1 0x0020U |
| #define | TIM_CCMR2_IC3F_2 0x0040U |
| #define | TIM_CCMR2_IC3F_3 0x0080U |
| #define | TIM_CCMR2_IC4PSC 0x0C00U |
| #define | TIM_CCMR2_IC4PSC_0 0x0400U |
| #define | TIM_CCMR2_IC4PSC_1 0x0800U |
| #define | TIM_CCMR2_IC4F 0xF000U |
| #define | TIM_CCMR2_IC4F_0 0x1000U |
| #define | TIM_CCMR2_IC4F_1 0x2000U |
| #define | TIM_CCMR2_IC4F_2 0x4000U |
| #define | TIM_CCMR2_IC4F_3 0x8000U |
| #define | TIM_CCER_CC1E 0x0001U |
| #define | TIM_CCER_CC1P 0x0002U |
| #define | TIM_CCER_CC1NE 0x0004U |
| #define | TIM_CCER_CC1NP 0x0008U |
| #define | TIM_CCER_CC2E 0x0010U |
| #define | TIM_CCER_CC2P 0x0020U |
| #define | TIM_CCER_CC2NE 0x0040U |
| #define | TIM_CCER_CC2NP 0x0080U |
| #define | TIM_CCER_CC3E 0x0100U |
| #define | TIM_CCER_CC3P 0x0200U |
| #define | TIM_CCER_CC3NE 0x0400U |
| #define | TIM_CCER_CC3NP 0x0800U |
| #define | TIM_CCER_CC4E 0x1000U |
| #define | TIM_CCER_CC4P 0x2000U |
| #define | TIM_CCER_CC4NP 0x8000U |
| #define | TIM_CNT_CNT 0xFFFFU |
| #define | TIM_PSC_PSC 0xFFFFU |
| #define | TIM_ARR_ARR 0xFFFFU |
| #define | TIM_RCR_REP 0xFFU |
| #define | TIM_CCR1_CCR1 0xFFFFU |
| #define | TIM_CCR2_CCR2 0xFFFFU |
| #define | TIM_CCR3_CCR3 0xFFFFU |
| #define | TIM_CCR4_CCR4 0xFFFFU |
| #define | TIM_BDTR_DTG 0x00FFU |
| #define | TIM_BDTR_DTG_0 0x0001U |
| #define | TIM_BDTR_DTG_1 0x0002U |
| #define | TIM_BDTR_DTG_2 0x0004U |
| #define | TIM_BDTR_DTG_3 0x0008U |
| #define | TIM_BDTR_DTG_4 0x0010U |
| #define | TIM_BDTR_DTG_5 0x0020U |
| #define | TIM_BDTR_DTG_6 0x0040U |
| #define | TIM_BDTR_DTG_7 0x0080U |
| #define | TIM_BDTR_LOCK 0x0300U |
| #define | TIM_BDTR_LOCK_0 0x0100U |
| #define | TIM_BDTR_LOCK_1 0x0200U |
| #define | TIM_BDTR_OSSI 0x0400U |
| #define | TIM_BDTR_OSSR 0x0800U |
| #define | TIM_BDTR_BKE 0x1000U |
| #define | TIM_BDTR_BKP 0x2000U |
| #define | TIM_BDTR_AOE 0x4000U |
| #define | TIM_BDTR_MOE 0x8000U |
| #define | TIM_DCR_DBA 0x001FU |
| #define | TIM_DCR_DBA_0 0x0001U |
| #define | TIM_DCR_DBA_1 0x0002U |
| #define | TIM_DCR_DBA_2 0x0004U |
| #define | TIM_DCR_DBA_3 0x0008U |
| #define | TIM_DCR_DBA_4 0x0010U |
| #define | TIM_DCR_DBL 0x1F00U |
| #define | TIM_DCR_DBL_0 0x0100U |
| #define | TIM_DCR_DBL_1 0x0200U |
| #define | TIM_DCR_DBL_2 0x0400U |
| #define | TIM_DCR_DBL_3 0x0800U |
| #define | TIM_DCR_DBL_4 0x1000U |
| #define | TIM_DMAR_DMAB 0xFFFFU |
| #define | TIM_OR_TI4_RMP 0x00C0U |
| #define | TIM_OR_TI4_RMP_0 0x0040U |
| #define | TIM_OR_TI4_RMP_1 0x0080U |
| #define | TIM_OR_ITR1_RMP 0x0C00U |
| #define | TIM_OR_ITR1_RMP_0 0x0400U |
| #define | TIM_OR_ITR1_RMP_1 0x0800U |
| #define | USART_SR_PE 0x0001U |
| #define | USART_SR_FE 0x0002U |
| #define | USART_SR_NE 0x0004U |
| #define | USART_SR_ORE 0x0008U |
| #define | USART_SR_IDLE 0x0010U |
| #define | USART_SR_RXNE 0x0020U |
| #define | USART_SR_TC 0x0040U |
| #define | USART_SR_TXE 0x0080U |
| #define | USART_SR_LBD 0x0100U |
| #define | USART_SR_CTS 0x0200U |
| #define | USART_DR_DR 0x01FFU |
| #define | USART_BRR_DIV_Fraction 0x000FU |
| #define | USART_BRR_DIV_Mantissa 0xFFF0U |
| #define | USART_CR1_SBK 0x0001U |
| #define | USART_CR1_RWU 0x0002U |
| #define | USART_CR1_RE 0x0004U |
| #define | USART_CR1_TE 0x0008U |
| #define | USART_CR1_IDLEIE 0x0010U |
| #define | USART_CR1_RXNEIE 0x0020U |
| #define | USART_CR1_TCIE 0x0040U |
| #define | USART_CR1_TXEIE 0x0080U |
| #define | USART_CR1_PEIE 0x0100U |
| #define | USART_CR1_PS 0x0200U |
| #define | USART_CR1_PCE 0x0400U |
| #define | USART_CR1_WAKE 0x0800U |
| #define | USART_CR1_M 0x1000U |
| #define | USART_CR1_UE 0x2000U |
| #define | USART_CR1_OVER8 0x8000U |
| #define | USART_CR2_ADD 0x000FU |
| #define | USART_CR2_LBDL 0x0020U |
| #define | USART_CR2_LBDIE 0x0040U |
| #define | USART_CR2_LBCL 0x0100U |
| #define | USART_CR2_CPHA 0x0200U |
| #define | USART_CR2_CPOL 0x0400U |
| #define | USART_CR2_CLKEN 0x0800U |
| #define | USART_CR2_STOP 0x3000U |
| #define | USART_CR2_STOP_0 0x1000U |
| #define | USART_CR2_STOP_1 0x2000U |
| #define | USART_CR2_LINEN 0x4000U |
| #define | USART_CR3_EIE 0x0001U |
| #define | USART_CR3_IREN 0x0002U |
| #define | USART_CR3_IRLP 0x0004U |
| #define | USART_CR3_HDSEL 0x0008U |
| #define | USART_CR3_NACK 0x0010U |
| #define | USART_CR3_SCEN 0x0020U |
| #define | USART_CR3_DMAR 0x0040U |
| #define | USART_CR3_DMAT 0x0080U |
| #define | USART_CR3_RTSE 0x0100U |
| #define | USART_CR3_CTSE 0x0200U |
| #define | USART_CR3_CTSIE 0x0400U |
| #define | USART_CR3_ONEBIT 0x0800U |
| #define | USART_GTPR_PSC 0x00FFU |
| #define | USART_GTPR_PSC_0 0x0001U |
| #define | USART_GTPR_PSC_1 0x0002U |
| #define | USART_GTPR_PSC_2 0x0004U |
| #define | USART_GTPR_PSC_3 0x0008U |
| #define | USART_GTPR_PSC_4 0x0010U |
| #define | USART_GTPR_PSC_5 0x0020U |
| #define | USART_GTPR_PSC_6 0x0040U |
| #define | USART_GTPR_PSC_7 0x0080U |
| #define | USART_GTPR_GT 0xFF00U |
| #define | WWDG_CR_T 0x7FU |
| #define | WWDG_CR_T_0 0x01U |
| #define | WWDG_CR_T_1 0x02U |
| #define | WWDG_CR_T_2 0x04U |
| #define | WWDG_CR_T_3 0x08U |
| #define | WWDG_CR_T_4 0x10U |
| #define | WWDG_CR_T_5 0x20U |
| #define | WWDG_CR_T_6 0x40U |
| #define | WWDG_CR_T0 WWDG_CR_T_0 |
| #define | WWDG_CR_T1 WWDG_CR_T_1 |
| #define | WWDG_CR_T2 WWDG_CR_T_2 |
| #define | WWDG_CR_T3 WWDG_CR_T_3 |
| #define | WWDG_CR_T4 WWDG_CR_T_4 |
| #define | WWDG_CR_T5 WWDG_CR_T_5 |
| #define | WWDG_CR_T6 WWDG_CR_T_6 |
| #define | WWDG_CR_WDGA 0x80U |
| #define | WWDG_CFR_W 0x007FU |
| #define | WWDG_CFR_W_0 0x0001U |
| #define | WWDG_CFR_W_1 0x0002U |
| #define | WWDG_CFR_W_2 0x0004U |
| #define | WWDG_CFR_W_3 0x0008U |
| #define | WWDG_CFR_W_4 0x0010U |
| #define | WWDG_CFR_W_5 0x0020U |
| #define | WWDG_CFR_W_6 0x0040U |
| #define | WWDG_CFR_W0 WWDG_CFR_W_0 |
| #define | WWDG_CFR_W1 WWDG_CFR_W_1 |
| #define | WWDG_CFR_W2 WWDG_CFR_W_2 |
| #define | WWDG_CFR_W3 WWDG_CFR_W_3 |
| #define | WWDG_CFR_W4 WWDG_CFR_W_4 |
| #define | WWDG_CFR_W5 WWDG_CFR_W_5 |
| #define | WWDG_CFR_W6 WWDG_CFR_W_6 |
| #define | WWDG_CFR_WDGTB 0x0180U |
| #define | WWDG_CFR_WDGTB_0 0x0080U |
| #define | WWDG_CFR_WDGTB_1 0x0100U |
| #define | WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 |
| #define | WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 |
| #define | WWDG_CFR_EWI 0x0200U |
| #define | WWDG_SR_EWIF 0x01U |
| #define | DBGMCU_IDCODE_DEV_ID 0x00000FFFU |
| #define | DBGMCU_IDCODE_REV_ID 0xFFFF0000U |
| #define | DBGMCU_CR_DBG_SLEEP 0x00000001U |
| #define | DBGMCU_CR_DBG_STOP 0x00000002U |
| #define | DBGMCU_CR_DBG_STANDBY 0x00000004U |
| #define | DBGMCU_CR_TRACE_IOEN 0x00000020U |
| #define | DBGMCU_CR_TRACE_MODE 0x000000C0U |
| #define | DBGMCU_CR_TRACE_MODE_0 0x00000040U |
| #define | DBGMCU_CR_TRACE_MODE_1 0x00000080U |
| #define | DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U |
| #define | DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U |
| #define | DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U |
| #define | DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U |
| #define | DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U |
| #define | DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U |
| #define | DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U |
| #define | DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U |
| #define | DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U |
| #define | DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U |
| #define | DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U |
| #define | DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U |
| #define | DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U |
| #define | DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U |
| #define | DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U |
| #define | DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U |
| #define | DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U |
| #define | DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP |
| #define | DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U |
| #define | DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U |
| #define | DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U |
| #define | DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U |
| #define | DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U |
| #define | ETH_MACCR_WD 0x00800000U /* Watchdog disable */ |
| #define | ETH_MACCR_JD 0x00400000U /* Jabber disable */ |
| #define | ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */ |
| #define | ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */ |
| #define | ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */ |
| #define | ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */ |
| #define | ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */ |
| #define | ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */ |
| #define | ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */ |
| #define | ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */ |
| #define | ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */ |
| #define | ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */ |
| #define | ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */ |
| #define | ETH_MACCR_ROD 0x00002000U /* Receive own disable */ |
| #define | ETH_MACCR_LM 0x00001000U /* loopback mode */ |
| #define | ETH_MACCR_DM 0x00000800U /* Duplex mode */ |
| #define | ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */ |
| #define | ETH_MACCR_RD 0x00000200U /* Retry disable */ |
| #define | ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */ |
| #define | ETH_MACCR_BL |
| #define | ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */ |
| #define | ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */ |
| #define | ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */ |
| #define | ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */ |
| #define | ETH_MACCR_DC 0x00000010U /* Defferal check */ |
| #define | ETH_MACCR_TE 0x00000008U /* Transmitter enable */ |
| #define | ETH_MACCR_RE 0x00000004U /* Receiver enable */ |
| #define | ETH_MACFFR_RA 0x80000000U /* Receive all */ |
| #define | ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */ |
| #define | ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */ |
| #define | ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */ |
| #define | ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */ |
| #define | ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */ |
| #define | ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */ |
| #define | ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */ |
| #define | ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */ |
| #define | ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */ |
| #define | ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */ |
| #define | ETH_MACFFR_HM 0x00000004U /* Hash multicast */ |
| #define | ETH_MACFFR_HU 0x00000002U /* Hash unicast */ |
| #define | ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */ |
| #define | ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */ |
| #define | ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */ |
| #define | ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */ |
| #define | ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */ |
| #define | ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */ |
| #define | ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ |
| #define | ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ |
| #define | ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
| #define | ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
| #define | ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ |
| #define | ETH_MACMIIAR_MW 0x00000002U /* MII write */ |
| #define | ETH_MACMIIAR_MB 0x00000001U /* MII busy */ |
| #define | ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */ |
| #define | ETH_MACFCR_PT 0xFFFF0000U /* Pause time */ |
| #define | ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */ |
| #define | ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */ |
| #define | ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */ |
| #define | ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */ |
| #define | ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */ |
| #define | ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */ |
| #define | ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */ |
| #define | ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */ |
| #define | ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */ |
| #define | ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */ |
| #define | ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */ |
| #define | ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */ |
| #define | ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */ |
| #define | ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */ |
| #define | ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */ |
| #define | ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */ |
| #define | ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */ |
| #define | ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */ |
| #define | ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */ |
| #define | ETH_MACPMTCSR_PD 0x00000001U /* Power Down */ |
| #define | ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */ |
| #define | ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */ |
| #define | ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */ |
| #define | ETH_MACSR_MMCS 0x00000010U /* MMC status */ |
| #define | ETH_MACSR_PMTS 0x00000008U /* PMT status */ |
| #define | ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */ |
| #define | ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */ |
| #define | ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */ |
| #define | ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */ |
| #define | ETH_MACA1HR_AE 0x80000000U /* Address enable */ |
| #define | ETH_MACA1HR_SA 0x40000000U /* Source address */ |
| #define | ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
| #define | ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */ |
| #define | ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */ |
| #define | ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */ |
| #define | ETH_MACA2HR_AE 0x80000000U /* Address enable */ |
| #define | ETH_MACA2HR_SA 0x40000000U /* Source address */ |
| #define | ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */ |
| #define | ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ |
| #define | ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */ |
| #define | ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */ |
| #define | ETH_MACA3HR_AE 0x80000000U /* Address enable */ |
| #define | ETH_MACA3HR_SA 0x40000000U /* Source address */ |
| #define | ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */ |
| #define | ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
| #define | ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
| #define | ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
| #define | ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
| #define | ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
| #define | ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ |
| #define | ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */ |
| #define | ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */ |
| #define | ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */ |
| #define | ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */ |
| #define | ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */ |
| #define | ETH_MMCCR_ROR 0x00000004U /* Reset on Read */ |
| #define | ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */ |
| #define | ETH_MMCCR_CR 0x00000001U /* Counters Reset */ |
| #define | ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */ |
| #define | ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */ |
| #define | ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */ |
| #define | ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
| #define | ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
| #define | ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
| #define | ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
| #define | ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
| #define | ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */ |
| #define | ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */ |
| #define | ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */ |
| #define | ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */ |
| #define | ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */ |
| #define | ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */ |
| #define | ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */ |
| #define | ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */ |
| #define | ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */ |
| #define | ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */ |
| #define | ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */ |
| #define | ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */ |
| #define | ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */ |
| #define | ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */ |
| #define | ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */ |
| #define | ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */ |
| #define | ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */ |
| #define | ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */ |
| #define | ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */ |
| #define | ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */ |
| #define | ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */ |
| #define | ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */ |
| #define | ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */ |
| #define | ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */ |
| #define | ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */ |
| #define | ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */ |
| #define | ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */ |
| #define | ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */ |
| #define | ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */ |
| #define | ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */ |
| #define | ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */ |
| #define | ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */ |
| #define | ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */ |
| #define | ETH_DMABMR_USP 0x00800000U /* Use separate PBL */ |
| #define | ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */ |
| #define | ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
| #define | ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
| #define | ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| #define | ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| #define | ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| #define | ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| #define | ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| #define | ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| #define | ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| #define | ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| #define | ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
| #define | ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
| #define | ETH_DMABMR_FB 0x00010000U /* Fixed Burst */ |
| #define | ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */ |
| #define | ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */ |
| #define | ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
| #define | ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
| #define | ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| #define | ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| #define | ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| #define | ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| #define | ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| #define | ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| #define | ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| #define | ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| #define | ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
| #define | ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
| #define | ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */ |
| #define | ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */ |
| #define | ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */ |
| #define | ETH_DMABMR_SR 0x00000001U /* Software reset */ |
| #define | ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */ |
| #define | ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */ |
| #define | ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */ |
| #define | ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */ |
| #define | ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */ |
| #define | ETH_DMASR_PMTS 0x10000000U /* PMT status */ |
| #define | ETH_DMASR_MMCS 0x08000000U /* MMC status */ |
| #define | ETH_DMASR_EBS 0x03800000U /* Error bits status */ |
| #define | ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */ |
| #define | ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */ |
| #define | ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */ |
| #define | ETH_DMASR_TPS 0x00700000U /* Transmit process state */ |
| #define | ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */ |
| #define | ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */ |
| #define | ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */ |
| #define | ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */ |
| #define | ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */ |
| #define | ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */ |
| #define | ETH_DMASR_RPS 0x000E0000U /* Receive process state */ |
| #define | ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */ |
| #define | ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */ |
| #define | ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */ |
| #define | ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */ |
| #define | ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */ |
| #define | ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */ |
| #define | ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */ |
| #define | ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */ |
| #define | ETH_DMASR_ERS 0x00004000U /* Early receive status */ |
| #define | ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */ |
| #define | ETH_DMASR_ETS 0x00000400U /* Early transmit status */ |
| #define | ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */ |
| #define | ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */ |
| #define | ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */ |
| #define | ETH_DMASR_RS 0x00000040U /* Receive status */ |
| #define | ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */ |
| #define | ETH_DMASR_ROS 0x00000010U /* Receive overflow status */ |
| #define | ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */ |
| #define | ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */ |
| #define | ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */ |
| #define | ETH_DMASR_TS 0x00000001U /* Transmit status */ |
| #define | ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */ |
| #define | ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */ |
| #define | ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */ |
| #define | ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */ |
| #define | ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */ |
| #define | ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */ |
| #define | ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
| #define | ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
| #define | ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
| #define | ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
| #define | ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
| #define | ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
| #define | ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
| #define | ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
| #define | ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */ |
| #define | ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */ |
| #define | ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */ |
| #define | ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */ |
| #define | ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
| #define | ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
| #define | ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
| #define | ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
| #define | ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */ |
| #define | ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */ |
| #define | ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */ |
| #define | ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */ |
| #define | ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */ |
| #define | ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */ |
| #define | ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */ |
| #define | ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */ |
| #define | ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */ |
| #define | ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */ |
| #define | ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */ |
| #define | ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */ |
| #define | ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */ |
| #define | ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */ |
| #define | ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */ |
| #define | ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */ |
| #define | ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */ |
| #define | ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */ |
| #define | ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */ |
| #define | ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */ |
| #define | ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */ |
| #define | ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */ |
| #define | ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */ |
| #define | ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */ |
| #define | ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */ |
| #define | USB_OTG_GOTGCTL_SRQSCS 0x00000001U |
| #define | USB_OTG_GOTGCTL_SRQ 0x00000002U |
| #define | USB_OTG_GOTGCTL_HNGSCS 0x00000100U |
| #define | USB_OTG_GOTGCTL_HNPRQ 0x00000200U |
| #define | USB_OTG_GOTGCTL_HSHNPEN 0x00000400U |
| #define | USB_OTG_GOTGCTL_DHNPEN 0x00000800U |
| #define | USB_OTG_GOTGCTL_CIDSTS 0x00010000U |
| #define | USB_OTG_GOTGCTL_DBCT 0x00020000U |
| #define | USB_OTG_GOTGCTL_ASVLD 0x00040000U |
| #define | USB_OTG_GOTGCTL_BSVLD 0x00080000U |
| #define | USB_OTG_HCFG_FSLSPCS 0x00000003U |
| #define | USB_OTG_HCFG_FSLSPCS_0 0x00000001U |
| #define | USB_OTG_HCFG_FSLSPCS_1 0x00000002U |
| #define | USB_OTG_HCFG_FSLSS 0x00000004U |
| #define | USB_OTG_DCFG_DSPD 0x00000003U |
| #define | USB_OTG_DCFG_DSPD_0 0x00000001U |
| #define | USB_OTG_DCFG_DSPD_1 0x00000002U |
| #define | USB_OTG_DCFG_NZLSOHSK 0x00000004U |
| #define | USB_OTG_DCFG_DAD 0x000007F0U |
| #define | USB_OTG_DCFG_DAD_0 0x00000010U |
| #define | USB_OTG_DCFG_DAD_1 0x00000020U |
| #define | USB_OTG_DCFG_DAD_2 0x00000040U |
| #define | USB_OTG_DCFG_DAD_3 0x00000080U |
| #define | USB_OTG_DCFG_DAD_4 0x00000100U |
| #define | USB_OTG_DCFG_DAD_5 0x00000200U |
| #define | USB_OTG_DCFG_DAD_6 0x00000400U |
| #define | USB_OTG_DCFG_PFIVL 0x00001800U |
| #define | USB_OTG_DCFG_PFIVL_0 0x00000800U |
| #define | USB_OTG_DCFG_PFIVL_1 0x00001000U |
| #define | USB_OTG_DCFG_PERSCHIVL 0x03000000U |
| #define | USB_OTG_DCFG_PERSCHIVL_0 0x01000000U |
| #define | USB_OTG_DCFG_PERSCHIVL_1 0x02000000U |
| #define | USB_OTG_PCGCR_STPPCLK 0x00000001U |
| #define | USB_OTG_PCGCR_GATEHCLK 0x00000002U |
| #define | USB_OTG_PCGCR_PHYSUSP 0x00000010U |
| #define | USB_OTG_GOTGINT_SEDET 0x00000004U |
| #define | USB_OTG_GOTGINT_SRSSCHG 0x00000100U |
| #define | USB_OTG_GOTGINT_HNSSCHG 0x00000200U |
| #define | USB_OTG_GOTGINT_HNGDET 0x00020000U |
| #define | USB_OTG_GOTGINT_ADTOCHG 0x00040000U |
| #define | USB_OTG_GOTGINT_DBCDNE 0x00080000U |
| #define | USB_OTG_DCTL_RWUSIG 0x00000001U |
| #define | USB_OTG_DCTL_SDIS 0x00000002U |
| #define | USB_OTG_DCTL_GINSTS 0x00000004U |
| #define | USB_OTG_DCTL_GONSTS 0x00000008U |
| #define | USB_OTG_DCTL_TCTL 0x00000070U |
| #define | USB_OTG_DCTL_TCTL_0 0x00000010U |
| #define | USB_OTG_DCTL_TCTL_1 0x00000020U |
| #define | USB_OTG_DCTL_TCTL_2 0x00000040U |
| #define | USB_OTG_DCTL_SGINAK 0x00000080U |
| #define | USB_OTG_DCTL_CGINAK 0x00000100U |
| #define | USB_OTG_DCTL_SGONAK 0x00000200U |
| #define | USB_OTG_DCTL_CGONAK 0x00000400U |
| #define | USB_OTG_DCTL_POPRGDNE 0x00000800U |
| #define | USB_OTG_HFIR_FRIVL 0x0000FFFFU |
| #define | USB_OTG_HFNUM_FRNUM 0x0000FFFFU |
| #define | USB_OTG_HFNUM_FTREM 0xFFFF0000U |
| #define | USB_OTG_DSTS_SUSPSTS 0x00000001U |
| #define | USB_OTG_DSTS_ENUMSPD 0x00000006U |
| #define | USB_OTG_DSTS_ENUMSPD_0 0x00000002U |
| #define | USB_OTG_DSTS_ENUMSPD_1 0x00000004U |
| #define | USB_OTG_DSTS_EERR 0x00000008U |
| #define | USB_OTG_DSTS_FNSOF 0x003FFF00U |
| #define | USB_OTG_GAHBCFG_GINT 0x00000001U |
| #define | USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU |
| #define | USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U |
| #define | USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U |
| #define | USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U |
| #define | USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U |
| #define | USB_OTG_GAHBCFG_DMAEN 0x00000020U |
| #define | USB_OTG_GAHBCFG_TXFELVL 0x00000080U |
| #define | USB_OTG_GAHBCFG_PTXFELVL 0x00000100U |
| #define | USB_OTG_GUSBCFG_TOCAL 0x00000007U |
| #define | USB_OTG_GUSBCFG_TOCAL_0 0x00000001U |
| #define | USB_OTG_GUSBCFG_TOCAL_1 0x00000002U |
| #define | USB_OTG_GUSBCFG_TOCAL_2 0x00000004U |
| #define | USB_OTG_GUSBCFG_PHYSEL 0x00000040U |
| #define | USB_OTG_GUSBCFG_SRPCAP 0x00000100U |
| #define | USB_OTG_GUSBCFG_HNPCAP 0x00000200U |
| #define | USB_OTG_GUSBCFG_TRDT 0x00003C00U |
| #define | USB_OTG_GUSBCFG_TRDT_0 0x00000400U |
| #define | USB_OTG_GUSBCFG_TRDT_1 0x00000800U |
| #define | USB_OTG_GUSBCFG_TRDT_2 0x00001000U |
| #define | USB_OTG_GUSBCFG_TRDT_3 0x00002000U |
| #define | USB_OTG_GUSBCFG_PHYLPCS 0x00008000U |
| #define | USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U |
| #define | USB_OTG_GUSBCFG_ULPIAR 0x00040000U |
| #define | USB_OTG_GUSBCFG_ULPICSM 0x00080000U |
| #define | USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U |
| #define | USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U |
| #define | USB_OTG_GUSBCFG_TSDPS 0x00400000U |
| #define | USB_OTG_GUSBCFG_PCCI 0x00800000U |
| #define | USB_OTG_GUSBCFG_PTCI 0x01000000U |
| #define | USB_OTG_GUSBCFG_ULPIIPD 0x02000000U |
| #define | USB_OTG_GUSBCFG_FHMOD 0x20000000U |
| #define | USB_OTG_GUSBCFG_FDMOD 0x40000000U |
| #define | USB_OTG_GUSBCFG_CTXPKT 0x80000000U |
| #define | USB_OTG_GRSTCTL_CSRST 0x00000001U |
| #define | USB_OTG_GRSTCTL_HSRST 0x00000002U |
| #define | USB_OTG_GRSTCTL_FCRST 0x00000004U |
| #define | USB_OTG_GRSTCTL_RXFFLSH 0x00000010U |
| #define | USB_OTG_GRSTCTL_TXFFLSH 0x00000020U |
| #define | USB_OTG_GRSTCTL_TXFNUM 0x000007C0U |
| #define | USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U |
| #define | USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U |
| #define | USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U |
| #define | USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U |
| #define | USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U |
| #define | USB_OTG_GRSTCTL_DMAREQ 0x40000000U |
| #define | USB_OTG_GRSTCTL_AHBIDL 0x80000000U |
| #define | USB_OTG_DIEPMSK_XFRCM 0x00000001U |
| #define | USB_OTG_DIEPMSK_EPDM 0x00000002U |
| #define | USB_OTG_DIEPMSK_TOM 0x00000008U |
| #define | USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U |
| #define | USB_OTG_DIEPMSK_INEPNMM 0x00000020U |
| #define | USB_OTG_DIEPMSK_INEPNEM 0x00000040U |
| #define | USB_OTG_DIEPMSK_TXFURM 0x00000100U |
| #define | USB_OTG_DIEPMSK_BIM 0x00000200U |
| #define | USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU |
| #define | USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U |
| #define | USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U |
| #define | USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U |
| #define | USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U |
| #define | USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U |
| #define | USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U |
| #define | USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U |
| #define | USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U |
| #define | USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U |
| #define | USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U |
| #define | USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U |
| #define | USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U |
| #define | USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U |
| #define | USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U |
| #define | USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U |
| #define | USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U |
| #define | USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U |
| #define | USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U |
| #define | USB_OTG_HAINT_HAINT 0x0000FFFFU |
| #define | USB_OTG_DOEPMSK_XFRCM 0x00000001U |
| #define | USB_OTG_DOEPMSK_EPDM 0x00000002U |
| #define | USB_OTG_DOEPMSK_STUPM 0x00000008U |
| #define | USB_OTG_DOEPMSK_OTEPDM 0x00000010U |
| #define | USB_OTG_DOEPMSK_B2BSTUP 0x00000040U |
| #define | USB_OTG_DOEPMSK_OPEM 0x00000100U |
| #define | USB_OTG_DOEPMSK_BOIM 0x00000200U |
| #define | USB_OTG_GINTSTS_CMOD 0x00000001U |
| #define | USB_OTG_GINTSTS_MMIS 0x00000002U |
| #define | USB_OTG_GINTSTS_OTGINT 0x00000004U |
| #define | USB_OTG_GINTSTS_SOF 0x00000008U |
| #define | USB_OTG_GINTSTS_RXFLVL 0x00000010U |
| #define | USB_OTG_GINTSTS_NPTXFE 0x00000020U |
| #define | USB_OTG_GINTSTS_GINAKEFF 0x00000040U |
| #define | USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U |
| #define | USB_OTG_GINTSTS_ESUSP 0x00000400U |
| #define | USB_OTG_GINTSTS_USBSUSP 0x00000800U |
| #define | USB_OTG_GINTSTS_USBRST 0x00001000U |
| #define | USB_OTG_GINTSTS_ENUMDNE 0x00002000U |
| #define | USB_OTG_GINTSTS_ISOODRP 0x00004000U |
| #define | USB_OTG_GINTSTS_EOPF 0x00008000U |
| #define | USB_OTG_GINTSTS_IEPINT 0x00040000U |
| #define | USB_OTG_GINTSTS_OEPINT 0x00080000U |
| #define | USB_OTG_GINTSTS_IISOIXFR 0x00100000U |
| #define | USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U |
| #define | USB_OTG_GINTSTS_DATAFSUSP 0x00400000U |
| #define | USB_OTG_GINTSTS_HPRTINT 0x01000000U |
| #define | USB_OTG_GINTSTS_HCINT 0x02000000U |
| #define | USB_OTG_GINTSTS_PTXFE 0x04000000U |
| #define | USB_OTG_GINTSTS_CIDSCHG 0x10000000U |
| #define | USB_OTG_GINTSTS_DISCINT 0x20000000U |
| #define | USB_OTG_GINTSTS_SRQINT 0x40000000U |
| #define | USB_OTG_GINTSTS_WKUINT 0x80000000U |
| #define | USB_OTG_GINTMSK_MMISM 0x00000002U |
| #define | USB_OTG_GINTMSK_OTGINT 0x00000004U |
| #define | USB_OTG_GINTMSK_SOFM 0x00000008U |
| #define | USB_OTG_GINTMSK_RXFLVLM 0x00000010U |
| #define | USB_OTG_GINTMSK_NPTXFEM 0x00000020U |
| #define | USB_OTG_GINTMSK_GINAKEFFM 0x00000040U |
| #define | USB_OTG_GINTMSK_GONAKEFFM 0x00000080U |
| #define | USB_OTG_GINTMSK_ESUSPM 0x00000400U |
| #define | USB_OTG_GINTMSK_USBSUSPM 0x00000800U |
| #define | USB_OTG_GINTMSK_USBRST 0x00001000U |
| #define | USB_OTG_GINTMSK_ENUMDNEM 0x00002000U |
| #define | USB_OTG_GINTMSK_ISOODRPM 0x00004000U |
| #define | USB_OTG_GINTMSK_EOPFM 0x00008000U |
| #define | USB_OTG_GINTMSK_EPMISM 0x00020000U |
| #define | USB_OTG_GINTMSK_IEPINT 0x00040000U |
| #define | USB_OTG_GINTMSK_OEPINT 0x00080000U |
| #define | USB_OTG_GINTMSK_IISOIXFRM 0x00100000U |
| #define | USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U |
| #define | USB_OTG_GINTMSK_FSUSPM 0x00400000U |
| #define | USB_OTG_GINTMSK_PRTIM 0x01000000U |
| #define | USB_OTG_GINTMSK_HCIM 0x02000000U |
| #define | USB_OTG_GINTMSK_PTXFEM 0x04000000U |
| #define | USB_OTG_GINTMSK_CIDSCHGM 0x10000000U |
| #define | USB_OTG_GINTMSK_DISCINT 0x20000000U |
| #define | USB_OTG_GINTMSK_SRQIM 0x40000000U |
| #define | USB_OTG_GINTMSK_WUIM 0x80000000U |
| #define | USB_OTG_DAINT_IEPINT 0x0000FFFFU |
| #define | USB_OTG_DAINT_OEPINT 0xFFFF0000U |
| #define | USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU |
| #define | USB_OTG_GRXSTSP_EPNUM 0x0000000FU |
| #define | USB_OTG_GRXSTSP_BCNT 0x00007FF0U |
| #define | USB_OTG_GRXSTSP_DPID 0x00018000U |
| #define | USB_OTG_GRXSTSP_PKTSTS 0x001E0000U |
| #define | USB_OTG_DAINTMSK_IEPM 0x0000FFFFU |
| #define | USB_OTG_DAINTMSK_OEPM 0xFFFF0000U |
| #define | USB_OTG_CHNUM 0x0000000FU |
| #define | USB_OTG_CHNUM 0x0000000FU |
| #define | USB_OTG_CHNUM_0 0x00000001U |
| #define | USB_OTG_CHNUM_0 0x00000001U |
| #define | USB_OTG_CHNUM_1 0x00000002U |
| #define | USB_OTG_CHNUM_1 0x00000002U |
| #define | USB_OTG_CHNUM_2 0x00000004U |
| #define | USB_OTG_CHNUM_2 0x00000004U |
| #define | USB_OTG_CHNUM_3 0x00000008U |
| #define | USB_OTG_CHNUM_3 0x00000008U |
| #define | USB_OTG_BCNT 0x00007FF0U |
| #define | USB_OTG_BCNT 0x00007FF0U |
| #define | USB_OTG_DPID 0x00018000U |
| #define | USB_OTG_DPID 0x00018000U |
| #define | USB_OTG_DPID_0 0x00008000U |
| #define | USB_OTG_DPID_0 0x00008000U |
| #define | USB_OTG_DPID_1 0x00010000U |
| #define | USB_OTG_DPID_1 0x00010000U |
| #define | USB_OTG_PKTSTS 0x001E0000U |
| #define | USB_OTG_PKTSTS 0x001E0000U |
| #define | USB_OTG_PKTSTS_0 0x00020000U |
| #define | USB_OTG_PKTSTS_0 0x00020000U |
| #define | USB_OTG_PKTSTS_1 0x00040000U |
| #define | USB_OTG_PKTSTS_1 0x00040000U |
| #define | USB_OTG_PKTSTS_2 0x00080000U |
| #define | USB_OTG_PKTSTS_2 0x00080000U |
| #define | USB_OTG_PKTSTS_3 0x00100000U |
| #define | USB_OTG_PKTSTS_3 0x00100000U |
| #define | USB_OTG_EPNUM 0x0000000FU |
| #define | USB_OTG_EPNUM 0x0000000FU |
| #define | USB_OTG_EPNUM_0 0x00000001U |
| #define | USB_OTG_EPNUM_0 0x00000001U |
| #define | USB_OTG_EPNUM_1 0x00000002U |
| #define | USB_OTG_EPNUM_1 0x00000002U |
| #define | USB_OTG_EPNUM_2 0x00000004U |
| #define | USB_OTG_EPNUM_2 0x00000004U |
| #define | USB_OTG_EPNUM_3 0x00000008U |
| #define | USB_OTG_EPNUM_3 0x00000008U |
| #define | USB_OTG_FRMNUM 0x01E00000U |
| #define | USB_OTG_FRMNUM 0x01E00000U |
| #define | USB_OTG_FRMNUM_0 0x00200000U |
| #define | USB_OTG_FRMNUM_0 0x00200000U |
| #define | USB_OTG_FRMNUM_1 0x00400000U |
| #define | USB_OTG_FRMNUM_1 0x00400000U |
| #define | USB_OTG_FRMNUM_2 0x00800000U |
| #define | USB_OTG_FRMNUM_2 0x00800000U |
| #define | USB_OTG_FRMNUM_3 0x01000000U |
| #define | USB_OTG_FRMNUM_3 0x01000000U |
| #define | USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU |
| #define | USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU |
| #define | USB_OTG_NPTXFSA 0x0000FFFFU |
| #define | USB_OTG_NPTXFD 0xFFFF0000U |
| #define | USB_OTG_TX0FSA 0x0000FFFFU |
| #define | USB_OTG_TX0FD 0xFFFF0000U |
| #define | USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU |
| #define | USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U |
| #define | USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U |
| #define | USB_OTG_DTHRCTL_ISOTHREN 0x00000002U |
| #define | USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U |
| #define | USB_OTG_DTHRCTL_RXTHREN 0x00010000U |
| #define | USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U |
| #define | USB_OTG_DTHRCTL_ARPEN 0x08000000U |
| #define | USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU |
| #define | USB_OTG_DEACHINT_IEP1INT 0x00000002U |
| #define | USB_OTG_DEACHINT_OEP1INT 0x00020000U |
| #define | USB_OTG_GCCFG_PWRDWN 0x00010000U |
| #define | USB_OTG_GCCFG_I2CPADEN 0x00020000U |
| #define | USB_OTG_GCCFG_VBUSASEN 0x00040000U |
| #define | USB_OTG_GCCFG_VBUSBSEN 0x00080000U |
| #define | USB_OTG_GCCFG_SOFOUTEN 0x00100000U |
| #define | USB_OTG_GCCFG_NOVBUSSENS 0x00200000U |
| #define | USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U |
| #define | USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U |
| #define | USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU |
| #define | USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U |
| #define | USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U |
| #define | USB_OTG_DIEPEACHMSK1_TOM 0x00000008U |
| #define | USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U |
| #define | USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U |
| #define | USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U |
| #define | USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U |
| #define | USB_OTG_DIEPEACHMSK1_BIM 0x00000200U |
| #define | USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U |
| #define | USB_OTG_HPRT_PCSTS 0x00000001U |
| #define | USB_OTG_HPRT_PCDET 0x00000002U |
| #define | USB_OTG_HPRT_PENA 0x00000004U |
| #define | USB_OTG_HPRT_PENCHNG 0x00000008U |
| #define | USB_OTG_HPRT_POCA 0x00000010U |
| #define | USB_OTG_HPRT_POCCHNG 0x00000020U |
| #define | USB_OTG_HPRT_PRES 0x00000040U |
| #define | USB_OTG_HPRT_PSUSP 0x00000080U |
| #define | USB_OTG_HPRT_PRST 0x00000100U |
| #define | USB_OTG_HPRT_PLSTS 0x00000C00U |
| #define | USB_OTG_HPRT_PLSTS_0 0x00000400U |
| #define | USB_OTG_HPRT_PLSTS_1 0x00000800U |
| #define | USB_OTG_HPRT_PPWR 0x00001000U |
| #define | USB_OTG_HPRT_PTCTL 0x0001E000U |
| #define | USB_OTG_HPRT_PTCTL_0 0x00002000U |
| #define | USB_OTG_HPRT_PTCTL_1 0x00004000U |
| #define | USB_OTG_HPRT_PTCTL_2 0x00008000U |
| #define | USB_OTG_HPRT_PTCTL_3 0x00010000U |
| #define | USB_OTG_HPRT_PSPD 0x00060000U |
| #define | USB_OTG_HPRT_PSPD_0 0x00020000U |
| #define | USB_OTG_HPRT_PSPD_1 0x00040000U |
| #define | USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U |
| #define | USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U |
| #define | USB_OTG_DOEPEACHMSK1_TOM 0x00000008U |
| #define | USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U |
| #define | USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U |
| #define | USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U |
| #define | USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U |
| #define | USB_OTG_DOEPEACHMSK1_BIM 0x00000200U |
| #define | USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U |
| #define | USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U |
| #define | USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U |
| #define | USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU |
| #define | USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U |
| #define | USB_OTG_DIEPCTL_MPSIZ 0x000007FFU |
| #define | USB_OTG_DIEPCTL_USBAEP 0x00008000U |
| #define | USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U |
| #define | USB_OTG_DIEPCTL_NAKSTS 0x00020000U |
| #define | USB_OTG_DIEPCTL_EPTYP 0x000C0000U |
| #define | USB_OTG_DIEPCTL_EPTYP_0 0x00040000U |
| #define | USB_OTG_DIEPCTL_EPTYP_1 0x00080000U |
| #define | USB_OTG_DIEPCTL_STALL 0x00200000U |
| #define | USB_OTG_DIEPCTL_TXFNUM 0x03C00000U |
| #define | USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U |
| #define | USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U |
| #define | USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U |
| #define | USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U |
| #define | USB_OTG_DIEPCTL_CNAK 0x04000000U |
| #define | USB_OTG_DIEPCTL_SNAK 0x08000000U |
| #define | USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U |
| #define | USB_OTG_DIEPCTL_SODDFRM 0x20000000U |
| #define | USB_OTG_DIEPCTL_EPDIS 0x40000000U |
| #define | USB_OTG_DIEPCTL_EPENA 0x80000000U |
| #define | USB_OTG_HCCHAR_MPSIZ 0x000007FFU |
| #define | USB_OTG_HCCHAR_EPNUM 0x00007800U |
| #define | USB_OTG_HCCHAR_EPNUM_0 0x00000800U |
| #define | USB_OTG_HCCHAR_EPNUM_1 0x00001000U |
| #define | USB_OTG_HCCHAR_EPNUM_2 0x00002000U |
| #define | USB_OTG_HCCHAR_EPNUM_3 0x00004000U |
| #define | USB_OTG_HCCHAR_EPDIR 0x00008000U |
| #define | USB_OTG_HCCHAR_LSDEV 0x00020000U |
| #define | USB_OTG_HCCHAR_EPTYP 0x000C0000U |
| #define | USB_OTG_HCCHAR_EPTYP_0 0x00040000U |
| #define | USB_OTG_HCCHAR_EPTYP_1 0x00080000U |
| #define | USB_OTG_HCCHAR_MC 0x00300000U |
| #define | USB_OTG_HCCHAR_MC_0 0x00100000U |
| #define | USB_OTG_HCCHAR_MC_1 0x00200000U |
| #define | USB_OTG_HCCHAR_DAD 0x1FC00000U |
| #define | USB_OTG_HCCHAR_DAD_0 0x00400000U |
| #define | USB_OTG_HCCHAR_DAD_1 0x00800000U |
| #define | USB_OTG_HCCHAR_DAD_2 0x01000000U |
| #define | USB_OTG_HCCHAR_DAD_3 0x02000000U |
| #define | USB_OTG_HCCHAR_DAD_4 0x04000000U |
| #define | USB_OTG_HCCHAR_DAD_5 0x08000000U |
| #define | USB_OTG_HCCHAR_DAD_6 0x10000000U |
| #define | USB_OTG_HCCHAR_ODDFRM 0x20000000U |
| #define | USB_OTG_HCCHAR_CHDIS 0x40000000U |
| #define | USB_OTG_HCCHAR_CHENA 0x80000000U |
| #define | USB_OTG_HCSPLT_PRTADDR 0x0000007FU |
| #define | USB_OTG_HCSPLT_PRTADDR_0 0x00000001U |
| #define | USB_OTG_HCSPLT_PRTADDR_1 0x00000002U |
| #define | USB_OTG_HCSPLT_PRTADDR_2 0x00000004U |
| #define | USB_OTG_HCSPLT_PRTADDR_3 0x00000008U |
| #define | USB_OTG_HCSPLT_PRTADDR_4 0x00000010U |
| #define | USB_OTG_HCSPLT_PRTADDR_5 0x00000020U |
| #define | USB_OTG_HCSPLT_PRTADDR_6 0x00000040U |
| #define | USB_OTG_HCSPLT_HUBADDR 0x00003F80U |
| #define | USB_OTG_HCSPLT_HUBADDR_0 0x00000080U |
| #define | USB_OTG_HCSPLT_HUBADDR_1 0x00000100U |
| #define | USB_OTG_HCSPLT_HUBADDR_2 0x00000200U |
| #define | USB_OTG_HCSPLT_HUBADDR_3 0x00000400U |
| #define | USB_OTG_HCSPLT_HUBADDR_4 0x00000800U |
| #define | USB_OTG_HCSPLT_HUBADDR_5 0x00001000U |
| #define | USB_OTG_HCSPLT_HUBADDR_6 0x00002000U |
| #define | USB_OTG_HCSPLT_XACTPOS 0x0000C000U |
| #define | USB_OTG_HCSPLT_XACTPOS_0 0x00004000U |
| #define | USB_OTG_HCSPLT_XACTPOS_1 0x00008000U |
| #define | USB_OTG_HCSPLT_COMPLSPLT 0x00010000U |
| #define | USB_OTG_HCSPLT_SPLITEN 0x80000000U |
| #define | USB_OTG_HCINT_XFRC 0x00000001U |
| #define | USB_OTG_HCINT_CHH 0x00000002U |
| #define | USB_OTG_HCINT_AHBERR 0x00000004U |
| #define | USB_OTG_HCINT_STALL 0x00000008U |
| #define | USB_OTG_HCINT_NAK 0x00000010U |
| #define | USB_OTG_HCINT_ACK 0x00000020U |
| #define | USB_OTG_HCINT_NYET 0x00000040U |
| #define | USB_OTG_HCINT_TXERR 0x00000080U |
| #define | USB_OTG_HCINT_BBERR 0x00000100U |
| #define | USB_OTG_HCINT_FRMOR 0x00000200U |
| #define | USB_OTG_HCINT_DTERR 0x00000400U |
| #define | USB_OTG_DIEPINT_XFRC 0x00000001U |
| #define | USB_OTG_DIEPINT_EPDISD 0x00000002U |
| #define | USB_OTG_DIEPINT_TOC 0x00000008U |
| #define | USB_OTG_DIEPINT_ITTXFE 0x00000010U |
| #define | USB_OTG_DIEPINT_INEPNE 0x00000040U |
| #define | USB_OTG_DIEPINT_TXFE 0x00000080U |
| #define | USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U |
| #define | USB_OTG_DIEPINT_BNA 0x00000200U |
| #define | USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U |
| #define | USB_OTG_DIEPINT_BERR 0x00001000U |
| #define | USB_OTG_DIEPINT_NAK 0x00002000U |
| #define | USB_OTG_HCINTMSK_XFRCM 0x00000001U |
| #define | USB_OTG_HCINTMSK_CHHM 0x00000002U |
| #define | USB_OTG_HCINTMSK_AHBERR 0x00000004U |
| #define | USB_OTG_HCINTMSK_STALLM 0x00000008U |
| #define | USB_OTG_HCINTMSK_NAKM 0x00000010U |
| #define | USB_OTG_HCINTMSK_ACKM 0x00000020U |
| #define | USB_OTG_HCINTMSK_NYET 0x00000040U |
| #define | USB_OTG_HCINTMSK_TXERRM 0x00000080U |
| #define | USB_OTG_HCINTMSK_BBERRM 0x00000100U |
| #define | USB_OTG_HCINTMSK_FRMORM 0x00000200U |
| #define | USB_OTG_HCINTMSK_DTERRM 0x00000400U |
| #define | USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU |
| #define | USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U |
| #define | USB_OTG_DIEPTSIZ_MULCNT 0x60000000U |
| #define | USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU |
| #define | USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U |
| #define | USB_OTG_HCTSIZ_DOPING 0x80000000U |
| #define | USB_OTG_HCTSIZ_DPID 0x60000000U |
| #define | USB_OTG_HCTSIZ_DPID_0 0x20000000U |
| #define | USB_OTG_HCTSIZ_DPID_1 0x40000000U |
| #define | USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU |
| #define | USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU |
| #define | USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU |
| #define | USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU |
| #define | USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U |
| #define | USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ |
| #define | USB_OTG_DOEPCTL_USBAEP 0x00008000U |
| #define | USB_OTG_DOEPCTL_NAKSTS 0x00020000U |
| #define | USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U |
| #define | USB_OTG_DOEPCTL_SODDFRM 0x20000000U |
| #define | USB_OTG_DOEPCTL_EPTYP 0x000C0000U |
| #define | USB_OTG_DOEPCTL_EPTYP_0 0x00040000U |
| #define | USB_OTG_DOEPCTL_EPTYP_1 0x00080000U |
| #define | USB_OTG_DOEPCTL_SNPM 0x00100000U |
| #define | USB_OTG_DOEPCTL_STALL 0x00200000U |
| #define | USB_OTG_DOEPCTL_CNAK 0x04000000U |
| #define | USB_OTG_DOEPCTL_SNAK 0x08000000U |
| #define | USB_OTG_DOEPCTL_EPDIS 0x40000000U |
| #define | USB_OTG_DOEPCTL_EPENA 0x80000000U |
| #define | USB_OTG_DOEPINT_XFRC 0x00000001U |
| #define | USB_OTG_DOEPINT_EPDISD 0x00000002U |
| #define | USB_OTG_DOEPINT_STUP 0x00000008U |
| #define | USB_OTG_DOEPINT_OTEPDIS 0x00000010U |
| #define | USB_OTG_DOEPINT_B2BSTUP 0x00000040U |
| #define | USB_OTG_DOEPINT_NYET 0x00004000U |
| #define | USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU |
| #define | USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U |
| #define | USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U |
| #define | USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U |
| #define | USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U |
| #define | USB_OTG_PCGCCTL_STOPCLK 0x00000001U |
| #define | USB_OTG_PCGCCTL_GATECLK 0x00000002U |
| #define | USB_OTG_PCGCCTL_PHYSUSP 0x00000010U |
| #define ADC_CCR_ADCPRE 0x00030000U |
ADCPRE[1:0] bits (ADC prescaler)
Definition at line 1538 of file stm32f407xx.h.
| #define ADC_CCR_ADCPRE_0 0x00010000U |
Bit 0
Definition at line 1539 of file stm32f407xx.h.
| #define ADC_CCR_ADCPRE_1 0x00020000U |
Bit 1
Definition at line 1540 of file stm32f407xx.h.
| #define ADC_CCR_DDS 0x00002000U |
DMA disable selection (Multi-ADC mode)
Definition at line 1534 of file stm32f407xx.h.
| #define ADC_CCR_DELAY 0x00000F00U |
DELAY[3:0] bits (Delay between 2 sampling phases)
Definition at line 1529 of file stm32f407xx.h.
| #define ADC_CCR_DELAY_0 0x00000100U |
Bit 0
Definition at line 1530 of file stm32f407xx.h.
| #define ADC_CCR_DELAY_1 0x00000200U |
Bit 1
Definition at line 1531 of file stm32f407xx.h.
| #define ADC_CCR_DELAY_2 0x00000400U |
Bit 2
Definition at line 1532 of file stm32f407xx.h.
| #define ADC_CCR_DELAY_3 0x00000800U |
Bit 3
Definition at line 1533 of file stm32f407xx.h.
| #define ADC_CCR_DMA 0x0000C000U |
DMA[1:0] bits (Direct Memory Access mode for multimode)
Definition at line 1535 of file stm32f407xx.h.
| #define ADC_CCR_DMA_0 0x00004000U |
Bit 0
Definition at line 1536 of file stm32f407xx.h.
| #define ADC_CCR_DMA_1 0x00008000U |
Bit 1
Definition at line 1537 of file stm32f407xx.h.
| #define ADC_CCR_MULTI 0x0000001FU |
MULTI[4:0] bits (Multi-ADC mode selection)
Definition at line 1523 of file stm32f407xx.h.
| #define ADC_CCR_MULTI_0 0x00000001U |
Bit 0
Definition at line 1524 of file stm32f407xx.h.
| #define ADC_CCR_MULTI_1 0x00000002U |
Bit 1
Definition at line 1525 of file stm32f407xx.h.
| #define ADC_CCR_MULTI_2 0x00000004U |
Bit 2
Definition at line 1526 of file stm32f407xx.h.
| #define ADC_CCR_MULTI_3 0x00000008U |
Bit 3
Definition at line 1527 of file stm32f407xx.h.
| #define ADC_CCR_MULTI_4 0x00000010U |
Bit 4
Definition at line 1528 of file stm32f407xx.h.
| #define ADC_CCR_TSVREFE 0x00800000U |
Temperature Sensor and VREFINT Enable
Definition at line 1542 of file stm32f407xx.h.
| #define ADC_CCR_VBATE 0x00400000U |
VBAT Enable
Definition at line 1541 of file stm32f407xx.h.
| #define ADC_CDR_DATA1 0x0000FFFFU |
1st data of a pair of regular conversions
Definition at line 1545 of file stm32f407xx.h.
| #define ADC_CDR_DATA2 0xFFFF0000U |
2nd data of a pair of regular conversions
Definition at line 1546 of file stm32f407xx.h.
| #define ADC_CR1_AWDCH 0x0000001FU |
AWDCH[4:0] bits (Analog watchdog channel select bits)
Definition at line 1196 of file stm32f407xx.h.
| #define ADC_CR1_AWDCH_0 0x00000001U |
Bit 0
Definition at line 1197 of file stm32f407xx.h.
| #define ADC_CR1_AWDCH_1 0x00000002U |
Bit 1
Definition at line 1198 of file stm32f407xx.h.
| #define ADC_CR1_AWDCH_2 0x00000004U |
Bit 2
Definition at line 1199 of file stm32f407xx.h.
| #define ADC_CR1_AWDCH_3 0x00000008U |
Bit 3
Definition at line 1200 of file stm32f407xx.h.
| #define ADC_CR1_AWDCH_4 0x00000010U |
Bit 4
Definition at line 1201 of file stm32f407xx.h.
| #define ADC_CR1_AWDEN 0x00800000U |
Analog watchdog enable on regular channels
Definition at line 1215 of file stm32f407xx.h.
| #define ADC_CR1_AWDIE 0x00000040U |
AAnalog Watchdog interrupt enable
Definition at line 1203 of file stm32f407xx.h.
| #define ADC_CR1_AWDSGL 0x00000200U |
Enable the watchdog on a single channel in scan mode
Definition at line 1206 of file stm32f407xx.h.
| #define ADC_CR1_DISCEN 0x00000800U |
Discontinuous mode on regular channels
Definition at line 1208 of file stm32f407xx.h.
| #define ADC_CR1_DISCNUM 0x0000E000U |
DISCNUM[2:0] bits (Discontinuous mode channel count)
Definition at line 1210 of file stm32f407xx.h.
| #define ADC_CR1_DISCNUM_0 0x00002000U |
Bit 0
Definition at line 1211 of file stm32f407xx.h.
| #define ADC_CR1_DISCNUM_1 0x00004000U |
Bit 1
Definition at line 1212 of file stm32f407xx.h.
| #define ADC_CR1_DISCNUM_2 0x00008000U |
Bit 2
Definition at line 1213 of file stm32f407xx.h.
| #define ADC_CR1_EOCIE 0x00000020U |
Interrupt enable for EOC
Definition at line 1202 of file stm32f407xx.h.
| #define ADC_CR1_JAUTO 0x00000400U |
Automatic injected group conversion
Definition at line 1207 of file stm32f407xx.h.
| #define ADC_CR1_JAWDEN 0x00400000U |
Analog watchdog enable on injected channels
Definition at line 1214 of file stm32f407xx.h.
| #define ADC_CR1_JDISCEN 0x00001000U |
Discontinuous mode on injected channels
Definition at line 1209 of file stm32f407xx.h.
| #define ADC_CR1_JEOCIE 0x00000080U |
Interrupt enable for injected channels
Definition at line 1204 of file stm32f407xx.h.
| #define ADC_CR1_OVRIE 0x04000000U |
overrun interrupt enable
Definition at line 1219 of file stm32f407xx.h.
| #define ADC_CR1_RES 0x03000000U |
RES[2:0] bits (Resolution)
Definition at line 1216 of file stm32f407xx.h.
| #define ADC_CR1_RES_0 0x01000000U |
Bit 0
Definition at line 1217 of file stm32f407xx.h.
| #define ADC_CR1_RES_1 0x02000000U |
Bit 1
Definition at line 1218 of file stm32f407xx.h.
| #define ADC_CR1_SCAN 0x00000100U |
Scan mode
Definition at line 1205 of file stm32f407xx.h.
| #define ADC_CR2_ADON 0x00000001U |
A/D Converter ON / OFF
Definition at line 1222 of file stm32f407xx.h.
| #define ADC_CR2_ALIGN 0x00000800U |
Data Alignment
Definition at line 1227 of file stm32f407xx.h.
| #define ADC_CR2_CONT 0x00000002U |
Continuous Conversion
Definition at line 1223 of file stm32f407xx.h.
| #define ADC_CR2_DDS 0x00000200U |
DMA disable selection (Single ADC)
Definition at line 1225 of file stm32f407xx.h.
| #define ADC_CR2_DMA 0x00000100U |
Direct Memory access mode
Definition at line 1224 of file stm32f407xx.h.
| #define ADC_CR2_EOCS 0x00000400U |
End of conversion selection
Definition at line 1226 of file stm32f407xx.h.
| #define ADC_CR2_EXTEN 0x30000000U |
EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp)
Definition at line 1242 of file stm32f407xx.h.
| #define ADC_CR2_EXTEN_0 0x10000000U |
Bit 0
Definition at line 1243 of file stm32f407xx.h.
| #define ADC_CR2_EXTEN_1 0x20000000U |
Bit 1
Definition at line 1244 of file stm32f407xx.h.
| #define ADC_CR2_EXTSEL 0x0F000000U |
EXTSEL[3:0] bits (External Event Select for regular group)
Definition at line 1237 of file stm32f407xx.h.
| #define ADC_CR2_EXTSEL_0 0x01000000U |
Bit 0
Definition at line 1238 of file stm32f407xx.h.
| #define ADC_CR2_EXTSEL_1 0x02000000U |
Bit 1
Definition at line 1239 of file stm32f407xx.h.
| #define ADC_CR2_EXTSEL_2 0x04000000U |
Bit 2
Definition at line 1240 of file stm32f407xx.h.
| #define ADC_CR2_EXTSEL_3 0x08000000U |
Bit 3
Definition at line 1241 of file stm32f407xx.h.
| #define ADC_CR2_JEXTEN 0x00300000U |
JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp)
Definition at line 1233 of file stm32f407xx.h.
| #define ADC_CR2_JEXTEN_0 0x00100000U |
Bit 0
Definition at line 1234 of file stm32f407xx.h.
| #define ADC_CR2_JEXTEN_1 0x00200000U |
Bit 1
Definition at line 1235 of file stm32f407xx.h.
| #define ADC_CR2_JEXTSEL 0x000F0000U |
JEXTSEL[3:0] bits (External event select for injected group)
Definition at line 1228 of file stm32f407xx.h.
| #define ADC_CR2_JEXTSEL_0 0x00010000U |
Bit 0
Definition at line 1229 of file stm32f407xx.h.
| #define ADC_CR2_JEXTSEL_1 0x00020000U |
Bit 1
Definition at line 1230 of file stm32f407xx.h.
| #define ADC_CR2_JEXTSEL_2 0x00040000U |
Bit 2
Definition at line 1231 of file stm32f407xx.h.
| #define ADC_CR2_JEXTSEL_3 0x00080000U |
Bit 3
Definition at line 1232 of file stm32f407xx.h.
| #define ADC_CR2_JSWSTART 0x00400000U |
Start Conversion of injected channels
Definition at line 1236 of file stm32f407xx.h.
| #define ADC_CR2_SWSTART 0x40000000U |
Start Conversion of regular channels
Definition at line 1245 of file stm32f407xx.h.
| #define ADC_CSR_AWD1 0x00000001U |
ADC1 Analog watchdog flag
Definition at line 1498 of file stm32f407xx.h.
| #define ADC_CSR_AWD2 0x00000100U |
ADC2 Analog watchdog flag
Definition at line 1504 of file stm32f407xx.h.
| #define ADC_CSR_AWD3 0x00010000U |
ADC3 Analog watchdog flag
Definition at line 1510 of file stm32f407xx.h.
| #define ADC_CSR_DOVR1 ADC_CSR_OVR1 |
Definition at line 1518 of file stm32f407xx.h.
| #define ADC_CSR_DOVR2 ADC_CSR_OVR2 |
Definition at line 1519 of file stm32f407xx.h.
| #define ADC_CSR_DOVR3 ADC_CSR_OVR3 |
Definition at line 1520 of file stm32f407xx.h.
| #define ADC_CSR_EOC1 0x00000002U |
ADC1 End of conversion
Definition at line 1499 of file stm32f407xx.h.
| #define ADC_CSR_EOC2 0x00000200U |
ADC2 End of conversion
Definition at line 1505 of file stm32f407xx.h.
| #define ADC_CSR_EOC3 0x00020000U |
ADC3 End of conversion
Definition at line 1511 of file stm32f407xx.h.
| #define ADC_CSR_JEOC1 0x00000004U |
ADC1 Injected channel end of conversion
Definition at line 1500 of file stm32f407xx.h.
| #define ADC_CSR_JEOC2 0x00000400U |
ADC2 Injected channel end of conversion
Definition at line 1506 of file stm32f407xx.h.
| #define ADC_CSR_JEOC3 0x00040000U |
ADC3 Injected channel end of conversion
Definition at line 1512 of file stm32f407xx.h.
| #define ADC_CSR_JSTRT1 0x00000008U |
ADC1 Injected channel Start flag
Definition at line 1501 of file stm32f407xx.h.
| #define ADC_CSR_JSTRT2 0x00000800U |
ADC2 Injected channel Start flag
Definition at line 1507 of file stm32f407xx.h.
| #define ADC_CSR_JSTRT3 0x00080000U |
ADC3 Injected channel Start flag
Definition at line 1513 of file stm32f407xx.h.
| #define ADC_CSR_OVR1 0x00000020U |
ADC1 DMA overrun flag
Definition at line 1503 of file stm32f407xx.h.
| #define ADC_CSR_OVR2 0x00002000U |
ADC2 DMA overrun flag
Definition at line 1509 of file stm32f407xx.h.
| #define ADC_CSR_OVR3 0x00200000U |
ADC3 DMA overrun flag
Definition at line 1515 of file stm32f407xx.h.
| #define ADC_CSR_STRT1 0x00000010U |
ADC1 Regular channel Start flag
Definition at line 1502 of file stm32f407xx.h.
| #define ADC_CSR_STRT2 0x00001000U |
ADC2 Regular channel Start flag
Definition at line 1508 of file stm32f407xx.h.
| #define ADC_CSR_STRT3 0x00100000U |
ADC3 Regular channel Start flag
Definition at line 1514 of file stm32f407xx.h.
| #define ADC_DR_ADC2DATA 0xFFFF0000U |
ADC2 data
Definition at line 1495 of file stm32f407xx.h.
| #define ADC_DR_DATA 0x0000FFFFU |
Regular data
Definition at line 1494 of file stm32f407xx.h.
| #define ADC_HTR_HT 0x0FFFU |
Analog watchdog high threshold
Definition at line 1340 of file stm32f407xx.h.
| #define ADC_JDR1_JDATA 0xFFFFU |
Injected data
Definition at line 1482 of file stm32f407xx.h.
| #define ADC_JDR2_JDATA 0xFFFFU |
Injected data
Definition at line 1485 of file stm32f407xx.h.
| #define ADC_JDR3_JDATA 0xFFFFU |
Injected data
Definition at line 1488 of file stm32f407xx.h.
| #define ADC_JDR4_JDATA 0xFFFFU |
Injected data
Definition at line 1491 of file stm32f407xx.h.
| #define ADC_JOFR1_JOFFSET1 0x0FFFU |
Data offset for injected channel 1
Definition at line 1328 of file stm32f407xx.h.
| #define ADC_JOFR2_JOFFSET2 0x0FFFU |
Data offset for injected channel 2
Definition at line 1331 of file stm32f407xx.h.
| #define ADC_JOFR3_JOFFSET3 0x0FFFU |
Data offset for injected channel 3
Definition at line 1334 of file stm32f407xx.h.
| #define ADC_JOFR4_JOFFSET4 0x0FFFU |
Data offset for injected channel 4
Definition at line 1337 of file stm32f407xx.h.
| #define ADC_JSQR_JL 0x00300000U |
JL[1:0] bits (Injected Sequence length)
Definition at line 1477 of file stm32f407xx.h.
| #define ADC_JSQR_JL_0 0x00100000U |
Bit 0
Definition at line 1478 of file stm32f407xx.h.
| #define ADC_JSQR_JL_1 0x00200000U |
Bit 1
Definition at line 1479 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ1 0x0000001FU |
JSQ1[4:0] bits (1st conversion in injected sequence)
Definition at line 1453 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ1_0 0x00000001U |
Bit 0
Definition at line 1454 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ1_1 0x00000002U |
Bit 1
Definition at line 1455 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ1_2 0x00000004U |
Bit 2
Definition at line 1456 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ1_3 0x00000008U |
Bit 3
Definition at line 1457 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ1_4 0x00000010U |
Bit 4
Definition at line 1458 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ2 0x000003E0U |
JSQ2[4:0] bits (2nd conversion in injected sequence)
Definition at line 1459 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ2_0 0x00000020U |
Bit 0
Definition at line 1460 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ2_1 0x00000040U |
Bit 1
Definition at line 1461 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ2_2 0x00000080U |
Bit 2
Definition at line 1462 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ2_3 0x00000100U |
Bit 3
Definition at line 1463 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ2_4 0x00000200U |
Bit 4
Definition at line 1464 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ3 0x00007C00U |
JSQ3[4:0] bits (3rd conversion in injected sequence)
Definition at line 1465 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ3_0 0x00000400U |
Bit 0
Definition at line 1466 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ3_1 0x00000800U |
Bit 1
Definition at line 1467 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ3_2 0x00001000U |
Bit 2
Definition at line 1468 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ3_3 0x00002000U |
Bit 3
Definition at line 1469 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ3_4 0x00004000U |
Bit 4
Definition at line 1470 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ4 0x000F8000U |
JSQ4[4:0] bits (4th conversion in injected sequence)
Definition at line 1471 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ4_0 0x00008000U |
Bit 0
Definition at line 1472 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ4_1 0x00010000U |
Bit 1
Definition at line 1473 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ4_2 0x00020000U |
Bit 2
Definition at line 1474 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ4_3 0x00040000U |
Bit 3
Definition at line 1475 of file stm32f407xx.h.
| #define ADC_JSQR_JSQ4_4 0x00080000U |
Bit 4
Definition at line 1476 of file stm32f407xx.h.
| #define ADC_LTR_LT 0x0FFFU |
Analog watchdog low threshold
Definition at line 1343 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP10 0x00000007U |
SMP10[2:0] bits (Channel 10 Sample time selection)
Definition at line 1248 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP10_0 0x00000001U |
Bit 0
Definition at line 1249 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP10_1 0x00000002U |
Bit 1
Definition at line 1250 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP10_2 0x00000004U |
Bit 2
Definition at line 1251 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP11 0x00000038U |
SMP11[2:0] bits (Channel 11 Sample time selection)
Definition at line 1252 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP11_0 0x00000008U |
Bit 0
Definition at line 1253 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP11_1 0x00000010U |
Bit 1
Definition at line 1254 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP11_2 0x00000020U |
Bit 2
Definition at line 1255 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP12 0x000001C0U |
SMP12[2:0] bits (Channel 12 Sample time selection)
Definition at line 1256 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP12_0 0x00000040U |
Bit 0
Definition at line 1257 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP12_1 0x00000080U |
Bit 1
Definition at line 1258 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP12_2 0x00000100U |
Bit 2
Definition at line 1259 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP13 0x00000E00U |
SMP13[2:0] bits (Channel 13 Sample time selection)
Definition at line 1260 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP13_0 0x00000200U |
Bit 0
Definition at line 1261 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP13_1 0x00000400U |
Bit 1
Definition at line 1262 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP13_2 0x00000800U |
Bit 2
Definition at line 1263 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP14 0x00007000U |
SMP14[2:0] bits (Channel 14 Sample time selection)
Definition at line 1264 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP14_0 0x00001000U |
Bit 0
Definition at line 1265 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP14_1 0x00002000U |
Bit 1
Definition at line 1266 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP14_2 0x00004000U |
Bit 2
Definition at line 1267 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP15 0x00038000U |
SMP15[2:0] bits (Channel 15 Sample time selection)
Definition at line 1268 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP15_0 0x00008000U |
Bit 0
Definition at line 1269 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP15_1 0x00010000U |
Bit 1
Definition at line 1270 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP15_2 0x00020000U |
Bit 2
Definition at line 1271 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP16 0x001C0000U |
SMP16[2:0] bits (Channel 16 Sample time selection)
Definition at line 1272 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP16_0 0x00040000U |
Bit 0
Definition at line 1273 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP16_1 0x00080000U |
Bit 1
Definition at line 1274 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP16_2 0x00100000U |
Bit 2
Definition at line 1275 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP17 0x00E00000U |
SMP17[2:0] bits (Channel 17 Sample time selection)
Definition at line 1276 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP17_0 0x00200000U |
Bit 0
Definition at line 1277 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP17_1 0x00400000U |
Bit 1
Definition at line 1278 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP17_2 0x00800000U |
Bit 2
Definition at line 1279 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP18 0x07000000U |
SMP18[2:0] bits (Channel 18 Sample time selection)
Definition at line 1280 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP18_0 0x01000000U |
Bit 0
Definition at line 1281 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP18_1 0x02000000U |
Bit 1
Definition at line 1282 of file stm32f407xx.h.
| #define ADC_SMPR1_SMP18_2 0x04000000U |
Bit 2
Definition at line 1283 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP0 0x00000007U |
SMP0[2:0] bits (Channel 0 Sample time selection)
Definition at line 1286 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP0_0 0x00000001U |
Bit 0
Definition at line 1287 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP0_1 0x00000002U |
Bit 1
Definition at line 1288 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP0_2 0x00000004U |
Bit 2
Definition at line 1289 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP1 0x00000038U |
SMP1[2:0] bits (Channel 1 Sample time selection)
Definition at line 1290 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP1_0 0x00000008U |
Bit 0
Definition at line 1291 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP1_1 0x00000010U |
Bit 1
Definition at line 1292 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP1_2 0x00000020U |
Bit 2
Definition at line 1293 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP2 0x000001C0U |
SMP2[2:0] bits (Channel 2 Sample time selection)
Definition at line 1294 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP2_0 0x00000040U |
Bit 0
Definition at line 1295 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP2_1 0x00000080U |
Bit 1
Definition at line 1296 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP2_2 0x00000100U |
Bit 2
Definition at line 1297 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP3 0x00000E00U |
SMP3[2:0] bits (Channel 3 Sample time selection)
Definition at line 1298 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP3_0 0x00000200U |
Bit 0
Definition at line 1299 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP3_1 0x00000400U |
Bit 1
Definition at line 1300 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP3_2 0x00000800U |
Bit 2
Definition at line 1301 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP4 0x00007000U |
SMP4[2:0] bits (Channel 4 Sample time selection)
Definition at line 1302 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP4_0 0x00001000U |
Bit 0
Definition at line 1303 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP4_1 0x00002000U |
Bit 1
Definition at line 1304 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP4_2 0x00004000U |
Bit 2
Definition at line 1305 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP5 0x00038000U |
SMP5[2:0] bits (Channel 5 Sample time selection)
Definition at line 1306 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP5_0 0x00008000U |
Bit 0
Definition at line 1307 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP5_1 0x00010000U |
Bit 1
Definition at line 1308 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP5_2 0x00020000U |
Bit 2
Definition at line 1309 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP6 0x001C0000U |
SMP6[2:0] bits (Channel 6 Sample time selection)
Definition at line 1310 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP6_0 0x00040000U |
Bit 0
Definition at line 1311 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP6_1 0x00080000U |
Bit 1
Definition at line 1312 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP6_2 0x00100000U |
Bit 2
Definition at line 1313 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP7 0x00E00000U |
SMP7[2:0] bits (Channel 7 Sample time selection)
Definition at line 1314 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP7_0 0x00200000U |
Bit 0
Definition at line 1315 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP7_1 0x00400000U |
Bit 1
Definition at line 1316 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP7_2 0x00800000U |
Bit 2
Definition at line 1317 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP8 0x07000000U |
SMP8[2:0] bits (Channel 8 Sample time selection)
Definition at line 1318 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP8_0 0x01000000U |
Bit 0
Definition at line 1319 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP8_1 0x02000000U |
Bit 1
Definition at line 1320 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP8_2 0x04000000U |
Bit 2
Definition at line 1321 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP9 0x38000000U |
SMP9[2:0] bits (Channel 9 Sample time selection)
Definition at line 1322 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP9_0 0x08000000U |
Bit 0
Definition at line 1323 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP9_1 0x10000000U |
Bit 1
Definition at line 1324 of file stm32f407xx.h.
| #define ADC_SMPR2_SMP9_2 0x20000000U |
Bit 2
Definition at line 1325 of file stm32f407xx.h.
| #define ADC_SQR1_L 0x00F00000U |
L[3:0] bits (Regular channel sequence length)
Definition at line 1370 of file stm32f407xx.h.
| #define ADC_SQR1_L_0 0x00100000U |
Bit 0
Definition at line 1371 of file stm32f407xx.h.
| #define ADC_SQR1_L_1 0x00200000U |
Bit 1
Definition at line 1372 of file stm32f407xx.h.
| #define ADC_SQR1_L_2 0x00400000U |
Bit 2
Definition at line 1373 of file stm32f407xx.h.
| #define ADC_SQR1_L_3 0x00800000U |
Bit 3
Definition at line 1374 of file stm32f407xx.h.
| #define ADC_SQR1_SQ13 0x0000001FU |
SQ13[4:0] bits (13th conversion in regular sequence)
Definition at line 1346 of file stm32f407xx.h.
| #define ADC_SQR1_SQ13_0 0x00000001U |
Bit 0
Definition at line 1347 of file stm32f407xx.h.
| #define ADC_SQR1_SQ13_1 0x00000002U |
Bit 1
Definition at line 1348 of file stm32f407xx.h.
| #define ADC_SQR1_SQ13_2 0x00000004U |
Bit 2
Definition at line 1349 of file stm32f407xx.h.
| #define ADC_SQR1_SQ13_3 0x00000008U |
Bit 3
Definition at line 1350 of file stm32f407xx.h.
| #define ADC_SQR1_SQ13_4 0x00000010U |
Bit 4
Definition at line 1351 of file stm32f407xx.h.
| #define ADC_SQR1_SQ14 0x000003E0U |
SQ14[4:0] bits (14th conversion in regular sequence)
Definition at line 1352 of file stm32f407xx.h.
| #define ADC_SQR1_SQ14_0 0x00000020U |
Bit 0
Definition at line 1353 of file stm32f407xx.h.
| #define ADC_SQR1_SQ14_1 0x00000040U |
Bit 1
Definition at line 1354 of file stm32f407xx.h.
| #define ADC_SQR1_SQ14_2 0x00000080U |
Bit 2
Definition at line 1355 of file stm32f407xx.h.
| #define ADC_SQR1_SQ14_3 0x00000100U |
Bit 3
Definition at line 1356 of file stm32f407xx.h.
| #define ADC_SQR1_SQ14_4 0x00000200U |
Bit 4
Definition at line 1357 of file stm32f407xx.h.
| #define ADC_SQR1_SQ15 0x00007C00U |
SQ15[4:0] bits (15th conversion in regular sequence)
Definition at line 1358 of file stm32f407xx.h.
| #define ADC_SQR1_SQ15_0 0x00000400U |
Bit 0
Definition at line 1359 of file stm32f407xx.h.
| #define ADC_SQR1_SQ15_1 0x00000800U |
Bit 1
Definition at line 1360 of file stm32f407xx.h.
| #define ADC_SQR1_SQ15_2 0x00001000U |
Bit 2
Definition at line 1361 of file stm32f407xx.h.
| #define ADC_SQR1_SQ15_3 0x00002000U |
Bit 3
Definition at line 1362 of file stm32f407xx.h.
| #define ADC_SQR1_SQ15_4 0x00004000U |
Bit 4
Definition at line 1363 of file stm32f407xx.h.
| #define ADC_SQR1_SQ16 0x000F8000U |
SQ16[4:0] bits (16th conversion in regular sequence)
Definition at line 1364 of file stm32f407xx.h.
| #define ADC_SQR1_SQ16_0 0x00008000U |
Bit 0
Definition at line 1365 of file stm32f407xx.h.
| #define ADC_SQR1_SQ16_1 0x00010000U |
Bit 1
Definition at line 1366 of file stm32f407xx.h.
| #define ADC_SQR1_SQ16_2 0x00020000U |
Bit 2
Definition at line 1367 of file stm32f407xx.h.
| #define ADC_SQR1_SQ16_3 0x00040000U |
Bit 3
Definition at line 1368 of file stm32f407xx.h.
| #define ADC_SQR1_SQ16_4 0x00080000U |
Bit 4
Definition at line 1369 of file stm32f407xx.h.
| #define ADC_SQR2_SQ10 0x000F8000U |
SQ10[4:0] bits (10th conversion in regular sequence)
Definition at line 1395 of file stm32f407xx.h.
| #define ADC_SQR2_SQ10_0 0x00008000U |
Bit 0
Definition at line 1396 of file stm32f407xx.h.
| #define ADC_SQR2_SQ10_1 0x00010000U |
Bit 1
Definition at line 1397 of file stm32f407xx.h.
| #define ADC_SQR2_SQ10_2 0x00020000U |
Bit 2
Definition at line 1398 of file stm32f407xx.h.
| #define ADC_SQR2_SQ10_3 0x00040000U |
Bit 3
Definition at line 1399 of file stm32f407xx.h.
| #define ADC_SQR2_SQ10_4 0x00080000U |
Bit 4
Definition at line 1400 of file stm32f407xx.h.
| #define ADC_SQR2_SQ11 0x01F00000U |
SQ11[4:0] bits (11th conversion in regular sequence)
Definition at line 1401 of file stm32f407xx.h.
| #define ADC_SQR2_SQ11_0 0x00100000U |
Bit 0
Definition at line 1402 of file stm32f407xx.h.
| #define ADC_SQR2_SQ11_1 0x00200000U |
Bit 1
Definition at line 1403 of file stm32f407xx.h.
| #define ADC_SQR2_SQ11_2 0x00400000U |
Bit 2
Definition at line 1404 of file stm32f407xx.h.
| #define ADC_SQR2_SQ11_3 0x00800000U |
Bit 3
Definition at line 1405 of file stm32f407xx.h.
| #define ADC_SQR2_SQ11_4 0x01000000U |
Bit 4
Definition at line 1406 of file stm32f407xx.h.
| #define ADC_SQR2_SQ12 0x3E000000U |
SQ12[4:0] bits (12th conversion in regular sequence)
Definition at line 1407 of file stm32f407xx.h.
| #define ADC_SQR2_SQ12_0 0x02000000U |
Bit 0
Definition at line 1408 of file stm32f407xx.h.
| #define ADC_SQR2_SQ12_1 0x04000000U |
Bit 1
Definition at line 1409 of file stm32f407xx.h.
| #define ADC_SQR2_SQ12_2 0x08000000U |
Bit 2
Definition at line 1410 of file stm32f407xx.h.
| #define ADC_SQR2_SQ12_3 0x10000000U |
Bit 3
Definition at line 1411 of file stm32f407xx.h.
| #define ADC_SQR2_SQ12_4 0x20000000U |
Bit 4
Definition at line 1412 of file stm32f407xx.h.
| #define ADC_SQR2_SQ7 0x0000001FU |
SQ7[4:0] bits (7th conversion in regular sequence)
Definition at line 1377 of file stm32f407xx.h.
| #define ADC_SQR2_SQ7_0 0x00000001U |
Bit 0
Definition at line 1378 of file stm32f407xx.h.
| #define ADC_SQR2_SQ7_1 0x00000002U |
Bit 1
Definition at line 1379 of file stm32f407xx.h.
| #define ADC_SQR2_SQ7_2 0x00000004U |
Bit 2
Definition at line 1380 of file stm32f407xx.h.
| #define ADC_SQR2_SQ7_3 0x00000008U |
Bit 3
Definition at line 1381 of file stm32f407xx.h.
| #define ADC_SQR2_SQ7_4 0x00000010U |
Bit 4
Definition at line 1382 of file stm32f407xx.h.
| #define ADC_SQR2_SQ8 0x000003E0U |
SQ8[4:0] bits (8th conversion in regular sequence)
Definition at line 1383 of file stm32f407xx.h.
| #define ADC_SQR2_SQ8_0 0x00000020U |
Bit 0
Definition at line 1384 of file stm32f407xx.h.
| #define ADC_SQR2_SQ8_1 0x00000040U |
Bit 1
Definition at line 1385 of file stm32f407xx.h.
| #define ADC_SQR2_SQ8_2 0x00000080U |
Bit 2
Definition at line 1386 of file stm32f407xx.h.
| #define ADC_SQR2_SQ8_3 0x00000100U |
Bit 3
Definition at line 1387 of file stm32f407xx.h.
| #define ADC_SQR2_SQ8_4 0x00000200U |
Bit 4
Definition at line 1388 of file stm32f407xx.h.
| #define ADC_SQR2_SQ9 0x00007C00U |
SQ9[4:0] bits (9th conversion in regular sequence)
Definition at line 1389 of file stm32f407xx.h.
| #define ADC_SQR2_SQ9_0 0x00000400U |
Bit 0
Definition at line 1390 of file stm32f407xx.h.
| #define ADC_SQR2_SQ9_1 0x00000800U |
Bit 1
Definition at line 1391 of file stm32f407xx.h.
| #define ADC_SQR2_SQ9_2 0x00001000U |
Bit 2
Definition at line 1392 of file stm32f407xx.h.
| #define ADC_SQR2_SQ9_3 0x00002000U |
Bit 3
Definition at line 1393 of file stm32f407xx.h.
| #define ADC_SQR2_SQ9_4 0x00004000U |
Bit 4
Definition at line 1394 of file stm32f407xx.h.
| #define ADC_SQR3_SQ1 0x0000001FU |
SQ1[4:0] bits (1st conversion in regular sequence)
Definition at line 1415 of file stm32f407xx.h.
| #define ADC_SQR3_SQ1_0 0x00000001U |
Bit 0
Definition at line 1416 of file stm32f407xx.h.
| #define ADC_SQR3_SQ1_1 0x00000002U |
Bit 1
Definition at line 1417 of file stm32f407xx.h.
| #define ADC_SQR3_SQ1_2 0x00000004U |
Bit 2
Definition at line 1418 of file stm32f407xx.h.
| #define ADC_SQR3_SQ1_3 0x00000008U |
Bit 3
Definition at line 1419 of file stm32f407xx.h.
| #define ADC_SQR3_SQ1_4 0x00000010U |
Bit 4
Definition at line 1420 of file stm32f407xx.h.
| #define ADC_SQR3_SQ2 0x000003E0U |
SQ2[4:0] bits (2nd conversion in regular sequence)
Definition at line 1421 of file stm32f407xx.h.
| #define ADC_SQR3_SQ2_0 0x00000020U |
Bit 0
Definition at line 1422 of file stm32f407xx.h.
| #define ADC_SQR3_SQ2_1 0x00000040U |
Bit 1
Definition at line 1423 of file stm32f407xx.h.
| #define ADC_SQR3_SQ2_2 0x00000080U |
Bit 2
Definition at line 1424 of file stm32f407xx.h.
| #define ADC_SQR3_SQ2_3 0x00000100U |
Bit 3
Definition at line 1425 of file stm32f407xx.h.
| #define ADC_SQR3_SQ2_4 0x00000200U |
Bit 4
Definition at line 1426 of file stm32f407xx.h.
| #define ADC_SQR3_SQ3 0x00007C00U |
SQ3[4:0] bits (3rd conversion in regular sequence)
Definition at line 1427 of file stm32f407xx.h.
| #define ADC_SQR3_SQ3_0 0x00000400U |
Bit 0
Definition at line 1428 of file stm32f407xx.h.
| #define ADC_SQR3_SQ3_1 0x00000800U |
Bit 1
Definition at line 1429 of file stm32f407xx.h.
| #define ADC_SQR3_SQ3_2 0x00001000U |
Bit 2
Definition at line 1430 of file stm32f407xx.h.
| #define ADC_SQR3_SQ3_3 0x00002000U |
Bit 3
Definition at line 1431 of file stm32f407xx.h.
| #define ADC_SQR3_SQ3_4 0x00004000U |
Bit 4
Definition at line 1432 of file stm32f407xx.h.
| #define ADC_SQR3_SQ4 0x000F8000U |
SQ4[4:0] bits (4th conversion in regular sequence)
Definition at line 1433 of file stm32f407xx.h.
| #define ADC_SQR3_SQ4_0 0x00008000U |
Bit 0
Definition at line 1434 of file stm32f407xx.h.
| #define ADC_SQR3_SQ4_1 0x00010000U |
Bit 1
Definition at line 1435 of file stm32f407xx.h.
| #define ADC_SQR3_SQ4_2 0x00020000U |
Bit 2
Definition at line 1436 of file stm32f407xx.h.
| #define ADC_SQR3_SQ4_3 0x00040000U |
Bit 3
Definition at line 1437 of file stm32f407xx.h.
| #define ADC_SQR3_SQ4_4 0x00080000U |
Bit 4
Definition at line 1438 of file stm32f407xx.h.
| #define ADC_SQR3_SQ5 0x01F00000U |
SQ5[4:0] bits (5th conversion in regular sequence)
Definition at line 1439 of file stm32f407xx.h.
| #define ADC_SQR3_SQ5_0 0x00100000U |
Bit 0
Definition at line 1440 of file stm32f407xx.h.
| #define ADC_SQR3_SQ5_1 0x00200000U |
Bit 1
Definition at line 1441 of file stm32f407xx.h.
| #define ADC_SQR3_SQ5_2 0x00400000U |
Bit 2
Definition at line 1442 of file stm32f407xx.h.
| #define ADC_SQR3_SQ5_3 0x00800000U |
Bit 3
Definition at line 1443 of file stm32f407xx.h.
| #define ADC_SQR3_SQ5_4 0x01000000U |
Bit 4
Definition at line 1444 of file stm32f407xx.h.
| #define ADC_SQR3_SQ6 0x3E000000U |
SQ6[4:0] bits (6th conversion in regular sequence)
Definition at line 1445 of file stm32f407xx.h.
| #define ADC_SQR3_SQ6_0 0x02000000U |
Bit 0
Definition at line 1446 of file stm32f407xx.h.
| #define ADC_SQR3_SQ6_1 0x04000000U |
Bit 1
Definition at line 1447 of file stm32f407xx.h.
| #define ADC_SQR3_SQ6_2 0x08000000U |
Bit 2
Definition at line 1448 of file stm32f407xx.h.
| #define ADC_SQR3_SQ6_3 0x10000000U |
Bit 3
Definition at line 1449 of file stm32f407xx.h.
| #define ADC_SQR3_SQ6_4 0x20000000U |
Bit 4
Definition at line 1450 of file stm32f407xx.h.
| #define ADC_SR_AWD 0x00000001U |
Analog watchdog flag
Definition at line 1188 of file stm32f407xx.h.
| #define ADC_SR_EOC 0x00000002U |
End of conversion
Definition at line 1189 of file stm32f407xx.h.
| #define ADC_SR_JEOC 0x00000004U |
Injected channel end of conversion
Definition at line 1190 of file stm32f407xx.h.
| #define ADC_SR_JSTRT 0x00000008U |
Injected channel Start flag
Definition at line 1191 of file stm32f407xx.h.
| #define ADC_SR_OVR 0x00000020U |
Overrun flag
Definition at line 1193 of file stm32f407xx.h.
| #define ADC_SR_STRT 0x00000010U |
Regular channel Start flag
Definition at line 1192 of file stm32f407xx.h.
| #define CAN_BTR_BRP 0x000003FFU |
Baud Rate Prescaler
Definition at line 1652 of file stm32f407xx.h.
| #define CAN_BTR_LBKM 0x40000000U |
Loop Back Mode (Debug)
Definition at line 1665 of file stm32f407xx.h.
| #define CAN_BTR_SILM 0x80000000U |
Silent Mode Mailbox registers
Definition at line 1669 of file stm32f407xx.h.
| #define CAN_BTR_SJW 0x03000000U |
Resynchronization Jump Width
Definition at line 1662 of file stm32f407xx.h.
| #define CAN_BTR_SJW_0 0x01000000U |
Bit 0
Definition at line 1663 of file stm32f407xx.h.
| #define CAN_BTR_SJW_1 0x02000000U |
Bit 1
Definition at line 1664 of file stm32f407xx.h.
| #define CAN_BTR_TS1 0x000F0000U |
Time Segment 1
Definition at line 1653 of file stm32f407xx.h.
| #define CAN_BTR_TS1_0 0x00010000U |
Bit 0
Definition at line 1654 of file stm32f407xx.h.
| #define CAN_BTR_TS1_1 0x00020000U |
Bit 1
Definition at line 1655 of file stm32f407xx.h.
| #define CAN_BTR_TS1_2 0x00040000U |
Bit 2
Definition at line 1656 of file stm32f407xx.h.
| #define CAN_BTR_TS1_3 0x00080000U |
Bit 3
Definition at line 1657 of file stm32f407xx.h.
| #define CAN_BTR_TS2 0x00700000U |
Time Segment 2
Definition at line 1658 of file stm32f407xx.h.
| #define CAN_BTR_TS2_0 0x00100000U |
Bit 0
Definition at line 1659 of file stm32f407xx.h.
| #define CAN_BTR_TS2_1 0x00200000U |
Bit 1
Definition at line 1660 of file stm32f407xx.h.
| #define CAN_BTR_TS2_2 0x00400000U |
Bit 2
Definition at line 1661 of file stm32f407xx.h.
| #define CAN_ESR_BOFF 0x00000004U |
Bus-Off Flag
Definition at line 1641 of file stm32f407xx.h.
| #define CAN_ESR_EPVF 0x00000002U |
Error Passive Flag
Definition at line 1640 of file stm32f407xx.h.
| #define CAN_ESR_EWGF 0x00000001U |
Error Warning Flag
Definition at line 1639 of file stm32f407xx.h.
| #define CAN_ESR_LEC 0x00000070U |
LEC[2:0] bits (Last Error Code)
Definition at line 1643 of file stm32f407xx.h.
| #define CAN_ESR_LEC_0 0x00000010U |
Bit 0
Definition at line 1644 of file stm32f407xx.h.
| #define CAN_ESR_LEC_1 0x00000020U |
Bit 1
Definition at line 1645 of file stm32f407xx.h.
| #define CAN_ESR_LEC_2 0x00000040U |
Bit 2
Definition at line 1646 of file stm32f407xx.h.
| #define CAN_ESR_REC 0xFF000000U |
Receive Error Counter
Definition at line 1649 of file stm32f407xx.h.
| #define CAN_ESR_TEC 0x00FF0000U |
Least significant byte of the 9-bit Transmit Error Counter
Definition at line 1648 of file stm32f407xx.h.
| #define CAN_F0R1_FB0 0x00000001U |
Filter bit 0
Definition at line 1918 of file stm32f407xx.h.
| #define CAN_F0R1_FB1 0x00000002U |
Filter bit 1
Definition at line 1919 of file stm32f407xx.h.
| #define CAN_F0R1_FB10 0x00000400U |
Filter bit 10
Definition at line 1928 of file stm32f407xx.h.
| #define CAN_F0R1_FB11 0x00000800U |
Filter bit 11
Definition at line 1929 of file stm32f407xx.h.
| #define CAN_F0R1_FB12 0x00001000U |
Filter bit 12
Definition at line 1930 of file stm32f407xx.h.
| #define CAN_F0R1_FB13 0x00002000U |
Filter bit 13
Definition at line 1931 of file stm32f407xx.h.
| #define CAN_F0R1_FB14 0x00004000U |
Filter bit 14
Definition at line 1932 of file stm32f407xx.h.
| #define CAN_F0R1_FB15 0x00008000U |
Filter bit 15
Definition at line 1933 of file stm32f407xx.h.
| #define CAN_F0R1_FB16 0x00010000U |
Filter bit 16
Definition at line 1934 of file stm32f407xx.h.
| #define CAN_F0R1_FB17 0x00020000U |
Filter bit 17
Definition at line 1935 of file stm32f407xx.h.
| #define CAN_F0R1_FB18 0x00040000U |
Filter bit 18
Definition at line 1936 of file stm32f407xx.h.
| #define CAN_F0R1_FB19 0x00080000U |
Filter bit 19
Definition at line 1937 of file stm32f407xx.h.
| #define CAN_F0R1_FB2 0x00000004U |
Filter bit 2
Definition at line 1920 of file stm32f407xx.h.
| #define CAN_F0R1_FB20 0x00100000U |
Filter bit 20
Definition at line 1938 of file stm32f407xx.h.
| #define CAN_F0R1_FB21 0x00200000U |
Filter bit 21
Definition at line 1939 of file stm32f407xx.h.
| #define CAN_F0R1_FB22 0x00400000U |
Filter bit 22
Definition at line 1940 of file stm32f407xx.h.
| #define CAN_F0R1_FB23 0x00800000U |
Filter bit 23
Definition at line 1941 of file stm32f407xx.h.
| #define CAN_F0R1_FB24 0x01000000U |
Filter bit 24
Definition at line 1942 of file stm32f407xx.h.
| #define CAN_F0R1_FB25 0x02000000U |
Filter bit 25
Definition at line 1943 of file stm32f407xx.h.
| #define CAN_F0R1_FB26 0x04000000U |
Filter bit 26
Definition at line 1944 of file stm32f407xx.h.
| #define CAN_F0R1_FB27 0x08000000U |
Filter bit 27
Definition at line 1945 of file stm32f407xx.h.
| #define CAN_F0R1_FB28 0x10000000U |
Filter bit 28
Definition at line 1946 of file stm32f407xx.h.
| #define CAN_F0R1_FB29 0x20000000U |
Filter bit 29
Definition at line 1947 of file stm32f407xx.h.
| #define CAN_F0R1_FB3 0x00000008U |
Filter bit 3
Definition at line 1921 of file stm32f407xx.h.
| #define CAN_F0R1_FB30 0x40000000U |
Filter bit 30
Definition at line 1948 of file stm32f407xx.h.
| #define CAN_F0R1_FB31 0x80000000U |
Filter bit 31
Definition at line 1949 of file stm32f407xx.h.
| #define CAN_F0R1_FB4 0x00000010U |
Filter bit 4
Definition at line 1922 of file stm32f407xx.h.
| #define CAN_F0R1_FB5 0x00000020U |
Filter bit 5
Definition at line 1923 of file stm32f407xx.h.
| #define CAN_F0R1_FB6 0x00000040U |
Filter bit 6
Definition at line 1924 of file stm32f407xx.h.
| #define CAN_F0R1_FB7 0x00000080U |
Filter bit 7
Definition at line 1925 of file stm32f407xx.h.
| #define CAN_F0R1_FB8 0x00000100U |
Filter bit 8
Definition at line 1926 of file stm32f407xx.h.
| #define CAN_F0R1_FB9 0x00000200U |
Filter bit 9
Definition at line 1927 of file stm32f407xx.h.
| #define CAN_F0R2_FB0 0x00000001U |
Filter bit 0
Definition at line 2394 of file stm32f407xx.h.
| #define CAN_F0R2_FB1 0x00000002U |
Filter bit 1
Definition at line 2395 of file stm32f407xx.h.
| #define CAN_F0R2_FB10 0x00000400U |
Filter bit 10
Definition at line 2404 of file stm32f407xx.h.
| #define CAN_F0R2_FB11 0x00000800U |
Filter bit 11
Definition at line 2405 of file stm32f407xx.h.
| #define CAN_F0R2_FB12 0x00001000U |
Filter bit 12
Definition at line 2406 of file stm32f407xx.h.
| #define CAN_F0R2_FB13 0x00002000U |
Filter bit 13
Definition at line 2407 of file stm32f407xx.h.
| #define CAN_F0R2_FB14 0x00004000U |
Filter bit 14
Definition at line 2408 of file stm32f407xx.h.
| #define CAN_F0R2_FB15 0x00008000U |
Filter bit 15
Definition at line 2409 of file stm32f407xx.h.
| #define CAN_F0R2_FB16 0x00010000U |
Filter bit 16
Definition at line 2410 of file stm32f407xx.h.
| #define CAN_F0R2_FB17 0x00020000U |
Filter bit 17
Definition at line 2411 of file stm32f407xx.h.
| #define CAN_F0R2_FB18 0x00040000U |
Filter bit 18
Definition at line 2412 of file stm32f407xx.h.
| #define CAN_F0R2_FB19 0x00080000U |
Filter bit 19
Definition at line 2413 of file stm32f407xx.h.
| #define CAN_F0R2_FB2 0x00000004U |
Filter bit 2
Definition at line 2396 of file stm32f407xx.h.
| #define CAN_F0R2_FB20 0x00100000U |
Filter bit 20
Definition at line 2414 of file stm32f407xx.h.
| #define CAN_F0R2_FB21 0x00200000U |
Filter bit 21
Definition at line 2415 of file stm32f407xx.h.
| #define CAN_F0R2_FB22 0x00400000U |
Filter bit 22
Definition at line 2416 of file stm32f407xx.h.
| #define CAN_F0R2_FB23 0x00800000U |
Filter bit 23
Definition at line 2417 of file stm32f407xx.h.
| #define CAN_F0R2_FB24 0x01000000U |
Filter bit 24
Definition at line 2418 of file stm32f407xx.h.
| #define CAN_F0R2_FB25 0x02000000U |
Filter bit 25
Definition at line 2419 of file stm32f407xx.h.
| #define CAN_F0R2_FB26 0x04000000U |
Filter bit 26
Definition at line 2420 of file stm32f407xx.h.
| #define CAN_F0R2_FB27 0x08000000U |
Filter bit 27
Definition at line 2421 of file stm32f407xx.h.
| #define CAN_F0R2_FB28 0x10000000U |
Filter bit 28
Definition at line 2422 of file stm32f407xx.h.
| #define CAN_F0R2_FB29 0x20000000U |
Filter bit 29
Definition at line 2423 of file stm32f407xx.h.
| #define CAN_F0R2_FB3 0x00000008U |
Filter bit 3
Definition at line 2397 of file stm32f407xx.h.
| #define CAN_F0R2_FB30 0x40000000U |
Filter bit 30
Definition at line 2424 of file stm32f407xx.h.
| #define CAN_F0R2_FB31 0x80000000U |
Filter bit 31
Definition at line 2425 of file stm32f407xx.h.
| #define CAN_F0R2_FB4 0x00000010U |
Filter bit 4
Definition at line 2398 of file stm32f407xx.h.
| #define CAN_F0R2_FB5 0x00000020U |
Filter bit 5
Definition at line 2399 of file stm32f407xx.h.
| #define CAN_F0R2_FB6 0x00000040U |
Filter bit 6
Definition at line 2400 of file stm32f407xx.h.
| #define CAN_F0R2_FB7 0x00000080U |
Filter bit 7
Definition at line 2401 of file stm32f407xx.h.
| #define CAN_F0R2_FB8 0x00000100U |
Filter bit 8
Definition at line 2402 of file stm32f407xx.h.
| #define CAN_F0R2_FB9 0x00000200U |
Filter bit 9
Definition at line 2403 of file stm32f407xx.h.
| #define CAN_F10R1_FB0 0x00000001U |
Filter bit 0
Definition at line 2258 of file stm32f407xx.h.
| #define CAN_F10R1_FB1 0x00000002U |
Filter bit 1
Definition at line 2259 of file stm32f407xx.h.
| #define CAN_F10R1_FB10 0x00000400U |
Filter bit 10
Definition at line 2268 of file stm32f407xx.h.
| #define CAN_F10R1_FB11 0x00000800U |
Filter bit 11
Definition at line 2269 of file stm32f407xx.h.
| #define CAN_F10R1_FB12 0x00001000U |
Filter bit 12
Definition at line 2270 of file stm32f407xx.h.
| #define CAN_F10R1_FB13 0x00002000U |
Filter bit 13
Definition at line 2271 of file stm32f407xx.h.
| #define CAN_F10R1_FB14 0x00004000U |
Filter bit 14
Definition at line 2272 of file stm32f407xx.h.
| #define CAN_F10R1_FB15 0x00008000U |
Filter bit 15
Definition at line 2273 of file stm32f407xx.h.
| #define CAN_F10R1_FB16 0x00010000U |
Filter bit 16
Definition at line 2274 of file stm32f407xx.h.
| #define CAN_F10R1_FB17 0x00020000U |
Filter bit 17
Definition at line 2275 of file stm32f407xx.h.
| #define CAN_F10R1_FB18 0x00040000U |
Filter bit 18
Definition at line 2276 of file stm32f407xx.h.
| #define CAN_F10R1_FB19 0x00080000U |
Filter bit 19
Definition at line 2277 of file stm32f407xx.h.
| #define CAN_F10R1_FB2 0x00000004U |
Filter bit 2
Definition at line 2260 of file stm32f407xx.h.
| #define CAN_F10R1_FB20 0x00100000U |
Filter bit 20
Definition at line 2278 of file stm32f407xx.h.
| #define CAN_F10R1_FB21 0x00200000U |
Filter bit 21
Definition at line 2279 of file stm32f407xx.h.
| #define CAN_F10R1_FB22 0x00400000U |
Filter bit 22
Definition at line 2280 of file stm32f407xx.h.
| #define CAN_F10R1_FB23 0x00800000U |
Filter bit 23
Definition at line 2281 of file stm32f407xx.h.
| #define CAN_F10R1_FB24 0x01000000U |
Filter bit 24
Definition at line 2282 of file stm32f407xx.h.
| #define CAN_F10R1_FB25 0x02000000U |
Filter bit 25
Definition at line 2283 of file stm32f407xx.h.
| #define CAN_F10R1_FB26 0x04000000U |
Filter bit 26
Definition at line 2284 of file stm32f407xx.h.
| #define CAN_F10R1_FB27 0x08000000U |
Filter bit 27
Definition at line 2285 of file stm32f407xx.h.
| #define CAN_F10R1_FB28 0x10000000U |
Filter bit 28
Definition at line 2286 of file stm32f407xx.h.
| #define CAN_F10R1_FB29 0x20000000U |
Filter bit 29
Definition at line 2287 of file stm32f407xx.h.
| #define CAN_F10R1_FB3 0x00000008U |
Filter bit 3
Definition at line 2261 of file stm32f407xx.h.
| #define CAN_F10R1_FB30 0x40000000U |
Filter bit 30
Definition at line 2288 of file stm32f407xx.h.
| #define CAN_F10R1_FB31 0x80000000U |
Filter bit 31
Definition at line 2289 of file stm32f407xx.h.
| #define CAN_F10R1_FB4 0x00000010U |
Filter bit 4
Definition at line 2262 of file stm32f407xx.h.
| #define CAN_F10R1_FB5 0x00000020U |
Filter bit 5
Definition at line 2263 of file stm32f407xx.h.
| #define CAN_F10R1_FB6 0x00000040U |
Filter bit 6
Definition at line 2264 of file stm32f407xx.h.
| #define CAN_F10R1_FB7 0x00000080U |
Filter bit 7
Definition at line 2265 of file stm32f407xx.h.
| #define CAN_F10R1_FB8 0x00000100U |
Filter bit 8
Definition at line 2266 of file stm32f407xx.h.
| #define CAN_F10R1_FB9 0x00000200U |
Filter bit 9
Definition at line 2267 of file stm32f407xx.h.
| #define CAN_F10R2_FB0 0x00000001U |
Filter bit 0
Definition at line 2734 of file stm32f407xx.h.
| #define CAN_F10R2_FB1 0x00000002U |
Filter bit 1
Definition at line 2735 of file stm32f407xx.h.
| #define CAN_F10R2_FB10 0x00000400U |
Filter bit 10
Definition at line 2744 of file stm32f407xx.h.
| #define CAN_F10R2_FB11 0x00000800U |
Filter bit 11
Definition at line 2745 of file stm32f407xx.h.
| #define CAN_F10R2_FB12 0x00001000U |
Filter bit 12
Definition at line 2746 of file stm32f407xx.h.
| #define CAN_F10R2_FB13 0x00002000U |
Filter bit 13
Definition at line 2747 of file stm32f407xx.h.
| #define CAN_F10R2_FB14 0x00004000U |
Filter bit 14
Definition at line 2748 of file stm32f407xx.h.
| #define CAN_F10R2_FB15 0x00008000U |
Filter bit 15
Definition at line 2749 of file stm32f407xx.h.
| #define CAN_F10R2_FB16 0x00010000U |
Filter bit 16
Definition at line 2750 of file stm32f407xx.h.
| #define CAN_F10R2_FB17 0x00020000U |
Filter bit 17
Definition at line 2751 of file stm32f407xx.h.
| #define CAN_F10R2_FB18 0x00040000U |
Filter bit 18
Definition at line 2752 of file stm32f407xx.h.
| #define CAN_F10R2_FB19 0x00080000U |
Filter bit 19
Definition at line 2753 of file stm32f407xx.h.
| #define CAN_F10R2_FB2 0x00000004U |
Filter bit 2
Definition at line 2736 of file stm32f407xx.h.
| #define CAN_F10R2_FB20 0x00100000U |
Filter bit 20
Definition at line 2754 of file stm32f407xx.h.
| #define CAN_F10R2_FB21 0x00200000U |
Filter bit 21
Definition at line 2755 of file stm32f407xx.h.
| #define CAN_F10R2_FB22 0x00400000U |
Filter bit 22
Definition at line 2756 of file stm32f407xx.h.
| #define CAN_F10R2_FB23 0x00800000U |
Filter bit 23
Definition at line 2757 of file stm32f407xx.h.
| #define CAN_F10R2_FB24 0x01000000U |
Filter bit 24
Definition at line 2758 of file stm32f407xx.h.
| #define CAN_F10R2_FB25 0x02000000U |
Filter bit 25
Definition at line 2759 of file stm32f407xx.h.
| #define CAN_F10R2_FB26 0x04000000U |
Filter bit 26
Definition at line 2760 of file stm32f407xx.h.
| #define CAN_F10R2_FB27 0x08000000U |
Filter bit 27
Definition at line 2761 of file stm32f407xx.h.
| #define CAN_F10R2_FB28 0x10000000U |
Filter bit 28
Definition at line 2762 of file stm32f407xx.h.
| #define CAN_F10R2_FB29 0x20000000U |
Filter bit 29
Definition at line 2763 of file stm32f407xx.h.
| #define CAN_F10R2_FB3 0x00000008U |
Filter bit 3
Definition at line 2737 of file stm32f407xx.h.
| #define CAN_F10R2_FB30 0x40000000U |
Filter bit 30
Definition at line 2764 of file stm32f407xx.h.
| #define CAN_F10R2_FB31 0x80000000U |
Filter bit 31
Definition at line 2765 of file stm32f407xx.h.
| #define CAN_F10R2_FB4 0x00000010U |
Filter bit 4
Definition at line 2738 of file stm32f407xx.h.
| #define CAN_F10R2_FB5 0x00000020U |
Filter bit 5
Definition at line 2739 of file stm32f407xx.h.
| #define CAN_F10R2_FB6 0x00000040U |
Filter bit 6
Definition at line 2740 of file stm32f407xx.h.
| #define CAN_F10R2_FB7 0x00000080U |
Filter bit 7
Definition at line 2741 of file stm32f407xx.h.
| #define CAN_F10R2_FB8 0x00000100U |
Filter bit 8
Definition at line 2742 of file stm32f407xx.h.
| #define CAN_F10R2_FB9 0x00000200U |
Filter bit 9
Definition at line 2743 of file stm32f407xx.h.
| #define CAN_F11R1_FB0 0x00000001U |
Filter bit 0
Definition at line 2292 of file stm32f407xx.h.
| #define CAN_F11R1_FB1 0x00000002U |
Filter bit 1
Definition at line 2293 of file stm32f407xx.h.
| #define CAN_F11R1_FB10 0x00000400U |
Filter bit 10
Definition at line 2302 of file stm32f407xx.h.
| #define CAN_F11R1_FB11 0x00000800U |
Filter bit 11
Definition at line 2303 of file stm32f407xx.h.
| #define CAN_F11R1_FB12 0x00001000U |
Filter bit 12
Definition at line 2304 of file stm32f407xx.h.
| #define CAN_F11R1_FB13 0x00002000U |
Filter bit 13
Definition at line 2305 of file stm32f407xx.h.
| #define CAN_F11R1_FB14 0x00004000U |
Filter bit 14
Definition at line 2306 of file stm32f407xx.h.
| #define CAN_F11R1_FB15 0x00008000U |
Filter bit 15
Definition at line 2307 of file stm32f407xx.h.
| #define CAN_F11R1_FB16 0x00010000U |
Filter bit 16
Definition at line 2308 of file stm32f407xx.h.
| #define CAN_F11R1_FB17 0x00020000U |
Filter bit 17
Definition at line 2309 of file stm32f407xx.h.
| #define CAN_F11R1_FB18 0x00040000U |
Filter bit 18
Definition at line 2310 of file stm32f407xx.h.
| #define CAN_F11R1_FB19 0x00080000U |
Filter bit 19
Definition at line 2311 of file stm32f407xx.h.
| #define CAN_F11R1_FB2 0x00000004U |
Filter bit 2
Definition at line 2294 of file stm32f407xx.h.
| #define CAN_F11R1_FB20 0x00100000U |
Filter bit 20
Definition at line 2312 of file stm32f407xx.h.
| #define CAN_F11R1_FB21 0x00200000U |
Filter bit 21
Definition at line 2313 of file stm32f407xx.h.
| #define CAN_F11R1_FB22 0x00400000U |
Filter bit 22
Definition at line 2314 of file stm32f407xx.h.
| #define CAN_F11R1_FB23 0x00800000U |
Filter bit 23
Definition at line 2315 of file stm32f407xx.h.
| #define CAN_F11R1_FB24 0x01000000U |
Filter bit 24
Definition at line 2316 of file stm32f407xx.h.
| #define CAN_F11R1_FB25 0x02000000U |
Filter bit 25
Definition at line 2317 of file stm32f407xx.h.
| #define CAN_F11R1_FB26 0x04000000U |
Filter bit 26
Definition at line 2318 of file stm32f407xx.h.
| #define CAN_F11R1_FB27 0x08000000U |
Filter bit 27
Definition at line 2319 of file stm32f407xx.h.
| #define CAN_F11R1_FB28 0x10000000U |
Filter bit 28
Definition at line 2320 of file stm32f407xx.h.
| #define CAN_F11R1_FB29 0x20000000U |
Filter bit 29
Definition at line 2321 of file stm32f407xx.h.
| #define CAN_F11R1_FB3 0x00000008U |
Filter bit 3
Definition at line 2295 of file stm32f407xx.h.
| #define CAN_F11R1_FB30 0x40000000U |
Filter bit 30
Definition at line 2322 of file stm32f407xx.h.
| #define CAN_F11R1_FB31 0x80000000U |
Filter bit 31
Definition at line 2323 of file stm32f407xx.h.
| #define CAN_F11R1_FB4 0x00000010U |
Filter bit 4
Definition at line 2296 of file stm32f407xx.h.
| #define CAN_F11R1_FB5 0x00000020U |
Filter bit 5
Definition at line 2297 of file stm32f407xx.h.
| #define CAN_F11R1_FB6 0x00000040U |
Filter bit 6
Definition at line 2298 of file stm32f407xx.h.
| #define CAN_F11R1_FB7 0x00000080U |
Filter bit 7
Definition at line 2299 of file stm32f407xx.h.
| #define CAN_F11R1_FB8 0x00000100U |
Filter bit 8
Definition at line 2300 of file stm32f407xx.h.
| #define CAN_F11R1_FB9 0x00000200U |
Filter bit 9
Definition at line 2301 of file stm32f407xx.h.
| #define CAN_F11R2_FB0 0x00000001U |
Filter bit 0
Definition at line 2768 of file stm32f407xx.h.
| #define CAN_F11R2_FB1 0x00000002U |
Filter bit 1
Definition at line 2769 of file stm32f407xx.h.
| #define CAN_F11R2_FB10 0x00000400U |
Filter bit 10
Definition at line 2778 of file stm32f407xx.h.
| #define CAN_F11R2_FB11 0x00000800U |
Filter bit 11
Definition at line 2779 of file stm32f407xx.h.
| #define CAN_F11R2_FB12 0x00001000U |
Filter bit 12
Definition at line 2780 of file stm32f407xx.h.
| #define CAN_F11R2_FB13 0x00002000U |
Filter bit 13
Definition at line 2781 of file stm32f407xx.h.
| #define CAN_F11R2_FB14 0x00004000U |
Filter bit 14
Definition at line 2782 of file stm32f407xx.h.
| #define CAN_F11R2_FB15 0x00008000U |
Filter bit 15
Definition at line 2783 of file stm32f407xx.h.
| #define CAN_F11R2_FB16 0x00010000U |
Filter bit 16
Definition at line 2784 of file stm32f407xx.h.
| #define CAN_F11R2_FB17 0x00020000U |
Filter bit 17
Definition at line 2785 of file stm32f407xx.h.
| #define CAN_F11R2_FB18 0x00040000U |
Filter bit 18
Definition at line 2786 of file stm32f407xx.h.
| #define CAN_F11R2_FB19 0x00080000U |
Filter bit 19
Definition at line 2787 of file stm32f407xx.h.
| #define CAN_F11R2_FB2 0x00000004U |
Filter bit 2
Definition at line 2770 of file stm32f407xx.h.
| #define CAN_F11R2_FB20 0x00100000U |
Filter bit 20
Definition at line 2788 of file stm32f407xx.h.
| #define CAN_F11R2_FB21 0x00200000U |
Filter bit 21
Definition at line 2789 of file stm32f407xx.h.
| #define CAN_F11R2_FB22 0x00400000U |
Filter bit 22
Definition at line 2790 of file stm32f407xx.h.
| #define CAN_F11R2_FB23 0x00800000U |
Filter bit 23
Definition at line 2791 of file stm32f407xx.h.
| #define CAN_F11R2_FB24 0x01000000U |
Filter bit 24
Definition at line 2792 of file stm32f407xx.h.
| #define CAN_F11R2_FB25 0x02000000U |
Filter bit 25
Definition at line 2793 of file stm32f407xx.h.
| #define CAN_F11R2_FB26 0x04000000U |
Filter bit 26
Definition at line 2794 of file stm32f407xx.h.
| #define CAN_F11R2_FB27 0x08000000U |
Filter bit 27
Definition at line 2795 of file stm32f407xx.h.
| #define CAN_F11R2_FB28 0x10000000U |
Filter bit 28
Definition at line 2796 of file stm32f407xx.h.
| #define CAN_F11R2_FB29 0x20000000U |
Filter bit 29
Definition at line 2797 of file stm32f407xx.h.
| #define CAN_F11R2_FB3 0x00000008U |
Filter bit 3
Definition at line 2771 of file stm32f407xx.h.
| #define CAN_F11R2_FB30 0x40000000U |
Filter bit 30
Definition at line 2798 of file stm32f407xx.h.
| #define CAN_F11R2_FB31 0x80000000U |
Filter bit 31
Definition at line 2799 of file stm32f407xx.h.
| #define CAN_F11R2_FB4 0x00000010U |
Filter bit 4
Definition at line 2772 of file stm32f407xx.h.
| #define CAN_F11R2_FB5 0x00000020U |
Filter bit 5
Definition at line 2773 of file stm32f407xx.h.
| #define CAN_F11R2_FB6 0x00000040U |
Filter bit 6
Definition at line 2774 of file stm32f407xx.h.
| #define CAN_F11R2_FB7 0x00000080U |
Filter bit 7
Definition at line 2775 of file stm32f407xx.h.
| #define CAN_F11R2_FB8 0x00000100U |
Filter bit 8
Definition at line 2776 of file stm32f407xx.h.
| #define CAN_F11R2_FB9 0x00000200U |
Filter bit 9
Definition at line 2777 of file stm32f407xx.h.
| #define CAN_F12R1_FB0 0x00000001U |
Filter bit 0
Definition at line 2326 of file stm32f407xx.h.
| #define CAN_F12R1_FB1 0x00000002U |
Filter bit 1
Definition at line 2327 of file stm32f407xx.h.
| #define CAN_F12R1_FB10 0x00000400U |
Filter bit 10
Definition at line 2336 of file stm32f407xx.h.
| #define CAN_F12R1_FB11 0x00000800U |
Filter bit 11
Definition at line 2337 of file stm32f407xx.h.
| #define CAN_F12R1_FB12 0x00001000U |
Filter bit 12
Definition at line 2338 of file stm32f407xx.h.
| #define CAN_F12R1_FB13 0x00002000U |
Filter bit 13
Definition at line 2339 of file stm32f407xx.h.
| #define CAN_F12R1_FB14 0x00004000U |
Filter bit 14
Definition at line 2340 of file stm32f407xx.h.
| #define CAN_F12R1_FB15 0x00008000U |
Filter bit 15
Definition at line 2341 of file stm32f407xx.h.
| #define CAN_F12R1_FB16 0x00010000U |
Filter bit 16
Definition at line 2342 of file stm32f407xx.h.
| #define CAN_F12R1_FB17 0x00020000U |
Filter bit 17
Definition at line 2343 of file stm32f407xx.h.
| #define CAN_F12R1_FB18 0x00040000U |
Filter bit 18
Definition at line 2344 of file stm32f407xx.h.
| #define CAN_F12R1_FB19 0x00080000U |
Filter bit 19
Definition at line 2345 of file stm32f407xx.h.
| #define CAN_F12R1_FB2 0x00000004U |
Filter bit 2
Definition at line 2328 of file stm32f407xx.h.
| #define CAN_F12R1_FB20 0x00100000U |
Filter bit 20
Definition at line 2346 of file stm32f407xx.h.
| #define CAN_F12R1_FB21 0x00200000U |
Filter bit 21
Definition at line 2347 of file stm32f407xx.h.
| #define CAN_F12R1_FB22 0x00400000U |
Filter bit 22
Definition at line 2348 of file stm32f407xx.h.
| #define CAN_F12R1_FB23 0x00800000U |
Filter bit 23
Definition at line 2349 of file stm32f407xx.h.
| #define CAN_F12R1_FB24 0x01000000U |
Filter bit 24
Definition at line 2350 of file stm32f407xx.h.
| #define CAN_F12R1_FB25 0x02000000U |
Filter bit 25
Definition at line 2351 of file stm32f407xx.h.
| #define CAN_F12R1_FB26 0x04000000U |
Filter bit 26
Definition at line 2352 of file stm32f407xx.h.
| #define CAN_F12R1_FB27 0x08000000U |
Filter bit 27
Definition at line 2353 of file stm32f407xx.h.
| #define CAN_F12R1_FB28 0x10000000U |
Filter bit 28
Definition at line 2354 of file stm32f407xx.h.
| #define CAN_F12R1_FB29 0x20000000U |
Filter bit 29
Definition at line 2355 of file stm32f407xx.h.
| #define CAN_F12R1_FB3 0x00000008U |
Filter bit 3
Definition at line 2329 of file stm32f407xx.h.
| #define CAN_F12R1_FB30 0x40000000U |
Filter bit 30
Definition at line 2356 of file stm32f407xx.h.
| #define CAN_F12R1_FB31 0x80000000U |
Filter bit 31
Definition at line 2357 of file stm32f407xx.h.
| #define CAN_F12R1_FB4 0x00000010U |
Filter bit 4
Definition at line 2330 of file stm32f407xx.h.
| #define CAN_F12R1_FB5 0x00000020U |
Filter bit 5
Definition at line 2331 of file stm32f407xx.h.
| #define CAN_F12R1_FB6 0x00000040U |
Filter bit 6
Definition at line 2332 of file stm32f407xx.h.
| #define CAN_F12R1_FB7 0x00000080U |
Filter bit 7
Definition at line 2333 of file stm32f407xx.h.
| #define CAN_F12R1_FB8 0x00000100U |
Filter bit 8
Definition at line 2334 of file stm32f407xx.h.
| #define CAN_F12R1_FB9 0x00000200U |
Filter bit 9
Definition at line 2335 of file stm32f407xx.h.
| #define CAN_F12R2_FB0 0x00000001U |
Filter bit 0
Definition at line 2802 of file stm32f407xx.h.
| #define CAN_F12R2_FB1 0x00000002U |
Filter bit 1
Definition at line 2803 of file stm32f407xx.h.
| #define CAN_F12R2_FB10 0x00000400U |
Filter bit 10
Definition at line 2812 of file stm32f407xx.h.
| #define CAN_F12R2_FB11 0x00000800U |
Filter bit 11
Definition at line 2813 of file stm32f407xx.h.
| #define CAN_F12R2_FB12 0x00001000U |
Filter bit 12
Definition at line 2814 of file stm32f407xx.h.
| #define CAN_F12R2_FB13 0x00002000U |
Filter bit 13
Definition at line 2815 of file stm32f407xx.h.
| #define CAN_F12R2_FB14 0x00004000U |
Filter bit 14
Definition at line 2816 of file stm32f407xx.h.
| #define CAN_F12R2_FB15 0x00008000U |
Filter bit 15
Definition at line 2817 of file stm32f407xx.h.
| #define CAN_F12R2_FB16 0x00010000U |
Filter bit 16
Definition at line 2818 of file stm32f407xx.h.
| #define CAN_F12R2_FB17 0x00020000U |
Filter bit 17
Definition at line 2819 of file stm32f407xx.h.
| #define CAN_F12R2_FB18 0x00040000U |
Filter bit 18
Definition at line 2820 of file stm32f407xx.h.
| #define CAN_F12R2_FB19 0x00080000U |
Filter bit 19
Definition at line 2821 of file stm32f407xx.h.
| #define CAN_F12R2_FB2 0x00000004U |
Filter bit 2
Definition at line 2804 of file stm32f407xx.h.
| #define CAN_F12R2_FB20 0x00100000U |
Filter bit 20
Definition at line 2822 of file stm32f407xx.h.
| #define CAN_F12R2_FB21 0x00200000U |
Filter bit 21
Definition at line 2823 of file stm32f407xx.h.
| #define CAN_F12R2_FB22 0x00400000U |
Filter bit 22
Definition at line 2824 of file stm32f407xx.h.
| #define CAN_F12R2_FB23 0x00800000U |
Filter bit 23
Definition at line 2825 of file stm32f407xx.h.
| #define CAN_F12R2_FB24 0x01000000U |
Filter bit 24
Definition at line 2826 of file stm32f407xx.h.
| #define CAN_F12R2_FB25 0x02000000U |
Filter bit 25
Definition at line 2827 of file stm32f407xx.h.
| #define CAN_F12R2_FB26 0x04000000U |
Filter bit 26
Definition at line 2828 of file stm32f407xx.h.
| #define CAN_F12R2_FB27 0x08000000U |
Filter bit 27
Definition at line 2829 of file stm32f407xx.h.
| #define CAN_F12R2_FB28 0x10000000U |
Filter bit 28
Definition at line 2830 of file stm32f407xx.h.
| #define CAN_F12R2_FB29 0x20000000U |
Filter bit 29
Definition at line 2831 of file stm32f407xx.h.
| #define CAN_F12R2_FB3 0x00000008U |
Filter bit 3
Definition at line 2805 of file stm32f407xx.h.
| #define CAN_F12R2_FB30 0x40000000U |
Filter bit 30
Definition at line 2832 of file stm32f407xx.h.
| #define CAN_F12R2_FB31 0x80000000U |
Filter bit 31
Definition at line 2833 of file stm32f407xx.h.
| #define CAN_F12R2_FB4 0x00000010U |
Filter bit 4
Definition at line 2806 of file stm32f407xx.h.
| #define CAN_F12R2_FB5 0x00000020U |
Filter bit 5
Definition at line 2807 of file stm32f407xx.h.
| #define CAN_F12R2_FB6 0x00000040U |
Filter bit 6
Definition at line 2808 of file stm32f407xx.h.
| #define CAN_F12R2_FB7 0x00000080U |
Filter bit 7
Definition at line 2809 of file stm32f407xx.h.
| #define CAN_F12R2_FB8 0x00000100U |
Filter bit 8
Definition at line 2810 of file stm32f407xx.h.
| #define CAN_F12R2_FB9 0x00000200U |
Filter bit 9
Definition at line 2811 of file stm32f407xx.h.
| #define CAN_F13R1_FB0 0x00000001U |
Filter bit 0
Definition at line 2360 of file stm32f407xx.h.
| #define CAN_F13R1_FB1 0x00000002U |
Filter bit 1
Definition at line 2361 of file stm32f407xx.h.
| #define CAN_F13R1_FB10 0x00000400U |
Filter bit 10
Definition at line 2370 of file stm32f407xx.h.
| #define CAN_F13R1_FB11 0x00000800U |
Filter bit 11
Definition at line 2371 of file stm32f407xx.h.
| #define CAN_F13R1_FB12 0x00001000U |
Filter bit 12
Definition at line 2372 of file stm32f407xx.h.
| #define CAN_F13R1_FB13 0x00002000U |
Filter bit 13
Definition at line 2373 of file stm32f407xx.h.
| #define CAN_F13R1_FB14 0x00004000U |
Filter bit 14
Definition at line 2374 of file stm32f407xx.h.
| #define CAN_F13R1_FB15 0x00008000U |
Filter bit 15
Definition at line 2375 of file stm32f407xx.h.
| #define CAN_F13R1_FB16 0x00010000U |
Filter bit 16
Definition at line 2376 of file stm32f407xx.h.
| #define CAN_F13R1_FB17 0x00020000U |
Filter bit 17
Definition at line 2377 of file stm32f407xx.h.
| #define CAN_F13R1_FB18 0x00040000U |
Filter bit 18
Definition at line 2378 of file stm32f407xx.h.
| #define CAN_F13R1_FB19 0x00080000U |
Filter bit 19
Definition at line 2379 of file stm32f407xx.h.
| #define CAN_F13R1_FB2 0x00000004U |
Filter bit 2
Definition at line 2362 of file stm32f407xx.h.
| #define CAN_F13R1_FB20 0x00100000U |
Filter bit 20
Definition at line 2380 of file stm32f407xx.h.
| #define CAN_F13R1_FB21 0x00200000U |
Filter bit 21
Definition at line 2381 of file stm32f407xx.h.
| #define CAN_F13R1_FB22 0x00400000U |
Filter bit 22
Definition at line 2382 of file stm32f407xx.h.
| #define CAN_F13R1_FB23 0x00800000U |
Filter bit 23
Definition at line 2383 of file stm32f407xx.h.
| #define CAN_F13R1_FB24 0x01000000U |
Filter bit 24
Definition at line 2384 of file stm32f407xx.h.
| #define CAN_F13R1_FB25 0x02000000U |
Filter bit 25
Definition at line 2385 of file stm32f407xx.h.
| #define CAN_F13R1_FB26 0x04000000U |
Filter bit 26
Definition at line 2386 of file stm32f407xx.h.
| #define CAN_F13R1_FB27 0x08000000U |
Filter bit 27
Definition at line 2387 of file stm32f407xx.h.
| #define CAN_F13R1_FB28 0x10000000U |
Filter bit 28
Definition at line 2388 of file stm32f407xx.h.
| #define CAN_F13R1_FB29 0x20000000U |
Filter bit 29
Definition at line 2389 of file stm32f407xx.h.
| #define CAN_F13R1_FB3 0x00000008U |
Filter bit 3
Definition at line 2363 of file stm32f407xx.h.
| #define CAN_F13R1_FB30 0x40000000U |
Filter bit 30
Definition at line 2390 of file stm32f407xx.h.
| #define CAN_F13R1_FB31 0x80000000U |
Filter bit 31
Definition at line 2391 of file stm32f407xx.h.
| #define CAN_F13R1_FB4 0x00000010U |
Filter bit 4
Definition at line 2364 of file stm32f407xx.h.
| #define CAN_F13R1_FB5 0x00000020U |
Filter bit 5
Definition at line 2365 of file stm32f407xx.h.
| #define CAN_F13R1_FB6 0x00000040U |
Filter bit 6
Definition at line 2366 of file stm32f407xx.h.
| #define CAN_F13R1_FB7 0x00000080U |
Filter bit 7
Definition at line 2367 of file stm32f407xx.h.
| #define CAN_F13R1_FB8 0x00000100U |
Filter bit 8
Definition at line 2368 of file stm32f407xx.h.
| #define CAN_F13R1_FB9 0x00000200U |
Filter bit 9
Definition at line 2369 of file stm32f407xx.h.
| #define CAN_F13R2_FB0 0x00000001U |
Filter bit 0
Definition at line 2836 of file stm32f407xx.h.
| #define CAN_F13R2_FB1 0x00000002U |
Filter bit 1
Definition at line 2837 of file stm32f407xx.h.
| #define CAN_F13R2_FB10 0x00000400U |
Filter bit 10
Definition at line 2846 of file stm32f407xx.h.
| #define CAN_F13R2_FB11 0x00000800U |
Filter bit 11
Definition at line 2847 of file stm32f407xx.h.
| #define CAN_F13R2_FB12 0x00001000U |
Filter bit 12
Definition at line 2848 of file stm32f407xx.h.
| #define CAN_F13R2_FB13 0x00002000U |
Filter bit 13
Definition at line 2849 of file stm32f407xx.h.
| #define CAN_F13R2_FB14 0x00004000U |
Filter bit 14
Definition at line 2850 of file stm32f407xx.h.
| #define CAN_F13R2_FB15 0x00008000U |
Filter bit 15
Definition at line 2851 of file stm32f407xx.h.
| #define CAN_F13R2_FB16 0x00010000U |
Filter bit 16
Definition at line 2852 of file stm32f407xx.h.
| #define CAN_F13R2_FB17 0x00020000U |
Filter bit 17
Definition at line 2853 of file stm32f407xx.h.
| #define CAN_F13R2_FB18 0x00040000U |
Filter bit 18
Definition at line 2854 of file stm32f407xx.h.
| #define CAN_F13R2_FB19 0x00080000U |
Filter bit 19
Definition at line 2855 of file stm32f407xx.h.
| #define CAN_F13R2_FB2 0x00000004U |
Filter bit 2
Definition at line 2838 of file stm32f407xx.h.
| #define CAN_F13R2_FB20 0x00100000U |
Filter bit 20
Definition at line 2856 of file stm32f407xx.h.
| #define CAN_F13R2_FB21 0x00200000U |
Filter bit 21
Definition at line 2857 of file stm32f407xx.h.
| #define CAN_F13R2_FB22 0x00400000U |
Filter bit 22
Definition at line 2858 of file stm32f407xx.h.
| #define CAN_F13R2_FB23 0x00800000U |
Filter bit 23
Definition at line 2859 of file stm32f407xx.h.
| #define CAN_F13R2_FB24 0x01000000U |
Filter bit 24
Definition at line 2860 of file stm32f407xx.h.
| #define CAN_F13R2_FB25 0x02000000U |
Filter bit 25
Definition at line 2861 of file stm32f407xx.h.
| #define CAN_F13R2_FB26 0x04000000U |
Filter bit 26
Definition at line 2862 of file stm32f407xx.h.
| #define CAN_F13R2_FB27 0x08000000U |
Filter bit 27
Definition at line 2863 of file stm32f407xx.h.
| #define CAN_F13R2_FB28 0x10000000U |
Filter bit 28
Definition at line 2864 of file stm32f407xx.h.
| #define CAN_F13R2_FB29 0x20000000U |
Filter bit 29
Definition at line 2865 of file stm32f407xx.h.
| #define CAN_F13R2_FB3 0x00000008U |
Filter bit 3
Definition at line 2839 of file stm32f407xx.h.
| #define CAN_F13R2_FB30 0x40000000U |
Filter bit 30
Definition at line 2866 of file stm32f407xx.h.
| #define CAN_F13R2_FB31 0x80000000U |
Filter bit 31
Definition at line 2867 of file stm32f407xx.h.
| #define CAN_F13R2_FB4 0x00000010U |
Filter bit 4
Definition at line 2840 of file stm32f407xx.h.
| #define CAN_F13R2_FB5 0x00000020U |
Filter bit 5
Definition at line 2841 of file stm32f407xx.h.
| #define CAN_F13R2_FB6 0x00000040U |
Filter bit 6
Definition at line 2842 of file stm32f407xx.h.
| #define CAN_F13R2_FB7 0x00000080U |
Filter bit 7
Definition at line 2843 of file stm32f407xx.h.
| #define CAN_F13R2_FB8 0x00000100U |
Filter bit 8
Definition at line 2844 of file stm32f407xx.h.
| #define CAN_F13R2_FB9 0x00000200U |
Filter bit 9
Definition at line 2845 of file stm32f407xx.h.
| #define CAN_F1R1_FB0 0x00000001U |
Filter bit 0
Definition at line 1952 of file stm32f407xx.h.
| #define CAN_F1R1_FB1 0x00000002U |
Filter bit 1
Definition at line 1953 of file stm32f407xx.h.
| #define CAN_F1R1_FB10 0x00000400U |
Filter bit 10
Definition at line 1962 of file stm32f407xx.h.
| #define CAN_F1R1_FB11 0x00000800U |
Filter bit 11
Definition at line 1963 of file stm32f407xx.h.
| #define CAN_F1R1_FB12 0x00001000U |
Filter bit 12
Definition at line 1964 of file stm32f407xx.h.
| #define CAN_F1R1_FB13 0x00002000U |
Filter bit 13
Definition at line 1965 of file stm32f407xx.h.
| #define CAN_F1R1_FB14 0x00004000U |
Filter bit 14
Definition at line 1966 of file stm32f407xx.h.
| #define CAN_F1R1_FB15 0x00008000U |
Filter bit 15
Definition at line 1967 of file stm32f407xx.h.
| #define CAN_F1R1_FB16 0x00010000U |
Filter bit 16
Definition at line 1968 of file stm32f407xx.h.
| #define CAN_F1R1_FB17 0x00020000U |
Filter bit 17
Definition at line 1969 of file stm32f407xx.h.
| #define CAN_F1R1_FB18 0x00040000U |
Filter bit 18
Definition at line 1970 of file stm32f407xx.h.
| #define CAN_F1R1_FB19 0x00080000U |
Filter bit 19
Definition at line 1971 of file stm32f407xx.h.
| #define CAN_F1R1_FB2 0x00000004U |
Filter bit 2
Definition at line 1954 of file stm32f407xx.h.
| #define CAN_F1R1_FB20 0x00100000U |
Filter bit 20
Definition at line 1972 of file stm32f407xx.h.
| #define CAN_F1R1_FB21 0x00200000U |
Filter bit 21
Definition at line 1973 of file stm32f407xx.h.
| #define CAN_F1R1_FB22 0x00400000U |
Filter bit 22
Definition at line 1974 of file stm32f407xx.h.
| #define CAN_F1R1_FB23 0x00800000U |
Filter bit 23
Definition at line 1975 of file stm32f407xx.h.
| #define CAN_F1R1_FB24 0x01000000U |
Filter bit 24
Definition at line 1976 of file stm32f407xx.h.
| #define CAN_F1R1_FB25 0x02000000U |
Filter bit 25
Definition at line 1977 of file stm32f407xx.h.
| #define CAN_F1R1_FB26 0x04000000U |
Filter bit 26
Definition at line 1978 of file stm32f407xx.h.
| #define CAN_F1R1_FB27 0x08000000U |
Filter bit 27
Definition at line 1979 of file stm32f407xx.h.
| #define CAN_F1R1_FB28 0x10000000U |
Filter bit 28
Definition at line 1980 of file stm32f407xx.h.
| #define CAN_F1R1_FB29 0x20000000U |
Filter bit 29
Definition at line 1981 of file stm32f407xx.h.
| #define CAN_F1R1_FB3 0x00000008U |
Filter bit 3
Definition at line 1955 of file stm32f407xx.h.
| #define CAN_F1R1_FB30 0x40000000U |
Filter bit 30
Definition at line 1982 of file stm32f407xx.h.
| #define CAN_F1R1_FB31 0x80000000U |
Filter bit 31
Definition at line 1983 of file stm32f407xx.h.
| #define CAN_F1R1_FB4 0x00000010U |
Filter bit 4
Definition at line 1956 of file stm32f407xx.h.
| #define CAN_F1R1_FB5 0x00000020U |
Filter bit 5
Definition at line 1957 of file stm32f407xx.h.
| #define CAN_F1R1_FB6 0x00000040U |
Filter bit 6
Definition at line 1958 of file stm32f407xx.h.
| #define CAN_F1R1_FB7 0x00000080U |
Filter bit 7
Definition at line 1959 of file stm32f407xx.h.
| #define CAN_F1R1_FB8 0x00000100U |
Filter bit 8
Definition at line 1960 of file stm32f407xx.h.
| #define CAN_F1R1_FB9 0x00000200U |
Filter bit 9
Definition at line 1961 of file stm32f407xx.h.
| #define CAN_F1R2_FB0 0x00000001U |
Filter bit 0
Definition at line 2428 of file stm32f407xx.h.
| #define CAN_F1R2_FB1 0x00000002U |
Filter bit 1
Definition at line 2429 of file stm32f407xx.h.
| #define CAN_F1R2_FB10 0x00000400U |
Filter bit 10
Definition at line 2438 of file stm32f407xx.h.
| #define CAN_F1R2_FB11 0x00000800U |
Filter bit 11
Definition at line 2439 of file stm32f407xx.h.
| #define CAN_F1R2_FB12 0x00001000U |
Filter bit 12
Definition at line 2440 of file stm32f407xx.h.
| #define CAN_F1R2_FB13 0x00002000U |
Filter bit 13
Definition at line 2441 of file stm32f407xx.h.
| #define CAN_F1R2_FB14 0x00004000U |
Filter bit 14
Definition at line 2442 of file stm32f407xx.h.
| #define CAN_F1R2_FB15 0x00008000U |
Filter bit 15
Definition at line 2443 of file stm32f407xx.h.
| #define CAN_F1R2_FB16 0x00010000U |
Filter bit 16
Definition at line 2444 of file stm32f407xx.h.
| #define CAN_F1R2_FB17 0x00020000U |
Filter bit 17
Definition at line 2445 of file stm32f407xx.h.
| #define CAN_F1R2_FB18 0x00040000U |
Filter bit 18
Definition at line 2446 of file stm32f407xx.h.
| #define CAN_F1R2_FB19 0x00080000U |
Filter bit 19
Definition at line 2447 of file stm32f407xx.h.
| #define CAN_F1R2_FB2 0x00000004U |
Filter bit 2
Definition at line 2430 of file stm32f407xx.h.
| #define CAN_F1R2_FB20 0x00100000U |
Filter bit 20
Definition at line 2448 of file stm32f407xx.h.
| #define CAN_F1R2_FB21 0x00200000U |
Filter bit 21
Definition at line 2449 of file stm32f407xx.h.
| #define CAN_F1R2_FB22 0x00400000U |
Filter bit 22
Definition at line 2450 of file stm32f407xx.h.
| #define CAN_F1R2_FB23 0x00800000U |
Filter bit 23
Definition at line 2451 of file stm32f407xx.h.
| #define CAN_F1R2_FB24 0x01000000U |
Filter bit 24
Definition at line 2452 of file stm32f407xx.h.
| #define CAN_F1R2_FB25 0x02000000U |
Filter bit 25
Definition at line 2453 of file stm32f407xx.h.
| #define CAN_F1R2_FB26 0x04000000U |
Filter bit 26
Definition at line 2454 of file stm32f407xx.h.
| #define CAN_F1R2_FB27 0x08000000U |
Filter bit 27
Definition at line 2455 of file stm32f407xx.h.
| #define CAN_F1R2_FB28 0x10000000U |
Filter bit 28
Definition at line 2456 of file stm32f407xx.h.
| #define CAN_F1R2_FB29 0x20000000U |
Filter bit 29
Definition at line 2457 of file stm32f407xx.h.
| #define CAN_F1R2_FB3 0x00000008U |
Filter bit 3
Definition at line 2431 of file stm32f407xx.h.
| #define CAN_F1R2_FB30 0x40000000U |
Filter bit 30
Definition at line 2458 of file stm32f407xx.h.
| #define CAN_F1R2_FB31 0x80000000U |
Filter bit 31
Definition at line 2459 of file stm32f407xx.h.
| #define CAN_F1R2_FB4 0x00000010U |
Filter bit 4
Definition at line 2432 of file stm32f407xx.h.
| #define CAN_F1R2_FB5 0x00000020U |
Filter bit 5
Definition at line 2433 of file stm32f407xx.h.
| #define CAN_F1R2_FB6 0x00000040U |
Filter bit 6
Definition at line 2434 of file stm32f407xx.h.
| #define CAN_F1R2_FB7 0x00000080U |
Filter bit 7
Definition at line 2435 of file stm32f407xx.h.
| #define CAN_F1R2_FB8 0x00000100U |
Filter bit 8
Definition at line 2436 of file stm32f407xx.h.
| #define CAN_F1R2_FB9 0x00000200U |
Filter bit 9
Definition at line 2437 of file stm32f407xx.h.
| #define CAN_F2R1_FB0 0x00000001U |
Filter bit 0
Definition at line 1986 of file stm32f407xx.h.
| #define CAN_F2R1_FB1 0x00000002U |
Filter bit 1
Definition at line 1987 of file stm32f407xx.h.
| #define CAN_F2R1_FB10 0x00000400U |
Filter bit 10
Definition at line 1996 of file stm32f407xx.h.
| #define CAN_F2R1_FB11 0x00000800U |
Filter bit 11
Definition at line 1997 of file stm32f407xx.h.
| #define CAN_F2R1_FB12 0x00001000U |
Filter bit 12
Definition at line 1998 of file stm32f407xx.h.
| #define CAN_F2R1_FB13 0x00002000U |
Filter bit 13
Definition at line 1999 of file stm32f407xx.h.
| #define CAN_F2R1_FB14 0x00004000U |
Filter bit 14
Definition at line 2000 of file stm32f407xx.h.
| #define CAN_F2R1_FB15 0x00008000U |
Filter bit 15
Definition at line 2001 of file stm32f407xx.h.
| #define CAN_F2R1_FB16 0x00010000U |
Filter bit 16
Definition at line 2002 of file stm32f407xx.h.
| #define CAN_F2R1_FB17 0x00020000U |
Filter bit 17
Definition at line 2003 of file stm32f407xx.h.
| #define CAN_F2R1_FB18 0x00040000U |
Filter bit 18
Definition at line 2004 of file stm32f407xx.h.
| #define CAN_F2R1_FB19 0x00080000U |
Filter bit 19
Definition at line 2005 of file stm32f407xx.h.
| #define CAN_F2R1_FB2 0x00000004U |
Filter bit 2
Definition at line 1988 of file stm32f407xx.h.
| #define CAN_F2R1_FB20 0x00100000U |
Filter bit 20
Definition at line 2006 of file stm32f407xx.h.
| #define CAN_F2R1_FB21 0x00200000U |
Filter bit 21
Definition at line 2007 of file stm32f407xx.h.
| #define CAN_F2R1_FB22 0x00400000U |
Filter bit 22
Definition at line 2008 of file stm32f407xx.h.
| #define CAN_F2R1_FB23 0x00800000U |
Filter bit 23
Definition at line 2009 of file stm32f407xx.h.
| #define CAN_F2R1_FB24 0x01000000U |
Filter bit 24
Definition at line 2010 of file stm32f407xx.h.
| #define CAN_F2R1_FB25 0x02000000U |
Filter bit 25
Definition at line 2011 of file stm32f407xx.h.
| #define CAN_F2R1_FB26 0x04000000U |
Filter bit 26
Definition at line 2012 of file stm32f407xx.h.
| #define CAN_F2R1_FB27 0x08000000U |
Filter bit 27
Definition at line 2013 of file stm32f407xx.h.
| #define CAN_F2R1_FB28 0x10000000U |
Filter bit 28
Definition at line 2014 of file stm32f407xx.h.
| #define CAN_F2R1_FB29 0x20000000U |
Filter bit 29
Definition at line 2015 of file stm32f407xx.h.
| #define CAN_F2R1_FB3 0x00000008U |
Filter bit 3
Definition at line 1989 of file stm32f407xx.h.
| #define CAN_F2R1_FB30 0x40000000U |
Filter bit 30
Definition at line 2016 of file stm32f407xx.h.
| #define CAN_F2R1_FB31 0x80000000U |
Filter bit 31
Definition at line 2017 of file stm32f407xx.h.
| #define CAN_F2R1_FB4 0x00000010U |
Filter bit 4
Definition at line 1990 of file stm32f407xx.h.
| #define CAN_F2R1_FB5 0x00000020U |
Filter bit 5
Definition at line 1991 of file stm32f407xx.h.
| #define CAN_F2R1_FB6 0x00000040U |
Filter bit 6
Definition at line 1992 of file stm32f407xx.h.
| #define CAN_F2R1_FB7 0x00000080U |
Filter bit 7
Definition at line 1993 of file stm32f407xx.h.
| #define CAN_F2R1_FB8 0x00000100U |
Filter bit 8
Definition at line 1994 of file stm32f407xx.h.
| #define CAN_F2R1_FB9 0x00000200U |
Filter bit 9
Definition at line 1995 of file stm32f407xx.h.
| #define CAN_F2R2_FB0 0x00000001U |
Filter bit 0
Definition at line 2462 of file stm32f407xx.h.
| #define CAN_F2R2_FB1 0x00000002U |
Filter bit 1
Definition at line 2463 of file stm32f407xx.h.
| #define CAN_F2R2_FB10 0x00000400U |
Filter bit 10
Definition at line 2472 of file stm32f407xx.h.
| #define CAN_F2R2_FB11 0x00000800U |
Filter bit 11
Definition at line 2473 of file stm32f407xx.h.
| #define CAN_F2R2_FB12 0x00001000U |
Filter bit 12
Definition at line 2474 of file stm32f407xx.h.
| #define CAN_F2R2_FB13 0x00002000U |
Filter bit 13
Definition at line 2475 of file stm32f407xx.h.
| #define CAN_F2R2_FB14 0x00004000U |
Filter bit 14
Definition at line 2476 of file stm32f407xx.h.
| #define CAN_F2R2_FB15 0x00008000U |
Filter bit 15
Definition at line 2477 of file stm32f407xx.h.
| #define CAN_F2R2_FB16 0x00010000U |
Filter bit 16
Definition at line 2478 of file stm32f407xx.h.
| #define CAN_F2R2_FB17 0x00020000U |
Filter bit 17
Definition at line 2479 of file stm32f407xx.h.
| #define CAN_F2R2_FB18 0x00040000U |
Filter bit 18
Definition at line 2480 of file stm32f407xx.h.
| #define CAN_F2R2_FB19 0x00080000U |
Filter bit 19
Definition at line 2481 of file stm32f407xx.h.
| #define CAN_F2R2_FB2 0x00000004U |
Filter bit 2
Definition at line 2464 of file stm32f407xx.h.
| #define CAN_F2R2_FB20 0x00100000U |
Filter bit 20
Definition at line 2482 of file stm32f407xx.h.
| #define CAN_F2R2_FB21 0x00200000U |
Filter bit 21
Definition at line 2483 of file stm32f407xx.h.
| #define CAN_F2R2_FB22 0x00400000U |
Filter bit 22
Definition at line 2484 of file stm32f407xx.h.
| #define CAN_F2R2_FB23 0x00800000U |
Filter bit 23
Definition at line 2485 of file stm32f407xx.h.
| #define CAN_F2R2_FB24 0x01000000U |
Filter bit 24
Definition at line 2486 of file stm32f407xx.h.
| #define CAN_F2R2_FB25 0x02000000U |
Filter bit 25
Definition at line 2487 of file stm32f407xx.h.
| #define CAN_F2R2_FB26 0x04000000U |
Filter bit 26
Definition at line 2488 of file stm32f407xx.h.
| #define CAN_F2R2_FB27 0x08000000U |
Filter bit 27
Definition at line 2489 of file stm32f407xx.h.
| #define CAN_F2R2_FB28 0x10000000U |
Filter bit 28
Definition at line 2490 of file stm32f407xx.h.
| #define CAN_F2R2_FB29 0x20000000U |
Filter bit 29
Definition at line 2491 of file stm32f407xx.h.
| #define CAN_F2R2_FB3 0x00000008U |
Filter bit 3
Definition at line 2465 of file stm32f407xx.h.
| #define CAN_F2R2_FB30 0x40000000U |
Filter bit 30
Definition at line 2492 of file stm32f407xx.h.
| #define CAN_F2R2_FB31 0x80000000U |
Filter bit 31
Definition at line 2493 of file stm32f407xx.h.
| #define CAN_F2R2_FB4 0x00000010U |
Filter bit 4
Definition at line 2466 of file stm32f407xx.h.
| #define CAN_F2R2_FB5 0x00000020U |
Filter bit 5
Definition at line 2467 of file stm32f407xx.h.
| #define CAN_F2R2_FB6 0x00000040U |
Filter bit 6
Definition at line 2468 of file stm32f407xx.h.
| #define CAN_F2R2_FB7 0x00000080U |
Filter bit 7
Definition at line 2469 of file stm32f407xx.h.
| #define CAN_F2R2_FB8 0x00000100U |
Filter bit 8
Definition at line 2470 of file stm32f407xx.h.
| #define CAN_F2R2_FB9 0x00000200U |
Filter bit 9
Definition at line 2471 of file stm32f407xx.h.
| #define CAN_F3R1_FB0 0x00000001U |
Filter bit 0
Definition at line 2020 of file stm32f407xx.h.
| #define CAN_F3R1_FB1 0x00000002U |
Filter bit 1
Definition at line 2021 of file stm32f407xx.h.
| #define CAN_F3R1_FB10 0x00000400U |
Filter bit 10
Definition at line 2030 of file stm32f407xx.h.
| #define CAN_F3R1_FB11 0x00000800U |
Filter bit 11
Definition at line 2031 of file stm32f407xx.h.
| #define CAN_F3R1_FB12 0x00001000U |
Filter bit 12
Definition at line 2032 of file stm32f407xx.h.
| #define CAN_F3R1_FB13 0x00002000U |
Filter bit 13
Definition at line 2033 of file stm32f407xx.h.
| #define CAN_F3R1_FB14 0x00004000U |
Filter bit 14
Definition at line 2034 of file stm32f407xx.h.
| #define CAN_F3R1_FB15 0x00008000U |
Filter bit 15
Definition at line 2035 of file stm32f407xx.h.
| #define CAN_F3R1_FB16 0x00010000U |
Filter bit 16
Definition at line 2036 of file stm32f407xx.h.
| #define CAN_F3R1_FB17 0x00020000U |
Filter bit 17
Definition at line 2037 of file stm32f407xx.h.
| #define CAN_F3R1_FB18 0x00040000U |
Filter bit 18
Definition at line 2038 of file stm32f407xx.h.
| #define CAN_F3R1_FB19 0x00080000U |
Filter bit 19
Definition at line 2039 of file stm32f407xx.h.
| #define CAN_F3R1_FB2 0x00000004U |
Filter bit 2
Definition at line 2022 of file stm32f407xx.h.
| #define CAN_F3R1_FB20 0x00100000U |
Filter bit 20
Definition at line 2040 of file stm32f407xx.h.
| #define CAN_F3R1_FB21 0x00200000U |
Filter bit 21
Definition at line 2041 of file stm32f407xx.h.
| #define CAN_F3R1_FB22 0x00400000U |
Filter bit 22
Definition at line 2042 of file stm32f407xx.h.
| #define CAN_F3R1_FB23 0x00800000U |
Filter bit 23
Definition at line 2043 of file stm32f407xx.h.
| #define CAN_F3R1_FB24 0x01000000U |
Filter bit 24
Definition at line 2044 of file stm32f407xx.h.
| #define CAN_F3R1_FB25 0x02000000U |
Filter bit 25
Definition at line 2045 of file stm32f407xx.h.
| #define CAN_F3R1_FB26 0x04000000U |
Filter bit 26
Definition at line 2046 of file stm32f407xx.h.
| #define CAN_F3R1_FB27 0x08000000U |
Filter bit 27
Definition at line 2047 of file stm32f407xx.h.
| #define CAN_F3R1_FB28 0x10000000U |
Filter bit 28
Definition at line 2048 of file stm32f407xx.h.
| #define CAN_F3R1_FB29 0x20000000U |
Filter bit 29
Definition at line 2049 of file stm32f407xx.h.
| #define CAN_F3R1_FB3 0x00000008U |
Filter bit 3
Definition at line 2023 of file stm32f407xx.h.
| #define CAN_F3R1_FB30 0x40000000U |
Filter bit 30
Definition at line 2050 of file stm32f407xx.h.
| #define CAN_F3R1_FB31 0x80000000U |
Filter bit 31
Definition at line 2051 of file stm32f407xx.h.
| #define CAN_F3R1_FB4 0x00000010U |
Filter bit 4
Definition at line 2024 of file stm32f407xx.h.
| #define CAN_F3R1_FB5 0x00000020U |
Filter bit 5
Definition at line 2025 of file stm32f407xx.h.
| #define CAN_F3R1_FB6 0x00000040U |
Filter bit 6
Definition at line 2026 of file stm32f407xx.h.
| #define CAN_F3R1_FB7 0x00000080U |
Filter bit 7
Definition at line 2027 of file stm32f407xx.h.
| #define CAN_F3R1_FB8 0x00000100U |
Filter bit 8
Definition at line 2028 of file stm32f407xx.h.
| #define CAN_F3R1_FB9 0x00000200U |
Filter bit 9
Definition at line 2029 of file stm32f407xx.h.
| #define CAN_F3R2_FB0 0x00000001U |
Filter bit 0
Definition at line 2496 of file stm32f407xx.h.
| #define CAN_F3R2_FB1 0x00000002U |
Filter bit 1
Definition at line 2497 of file stm32f407xx.h.
| #define CAN_F3R2_FB10 0x00000400U |
Filter bit 10
Definition at line 2506 of file stm32f407xx.h.
| #define CAN_F3R2_FB11 0x00000800U |
Filter bit 11
Definition at line 2507 of file stm32f407xx.h.
| #define CAN_F3R2_FB12 0x00001000U |
Filter bit 12
Definition at line 2508 of file stm32f407xx.h.
| #define CAN_F3R2_FB13 0x00002000U |
Filter bit 13
Definition at line 2509 of file stm32f407xx.h.
| #define CAN_F3R2_FB14 0x00004000U |
Filter bit 14
Definition at line 2510 of file stm32f407xx.h.
| #define CAN_F3R2_FB15 0x00008000U |
Filter bit 15
Definition at line 2511 of file stm32f407xx.h.
| #define CAN_F3R2_FB16 0x00010000U |
Filter bit 16
Definition at line 2512 of file stm32f407xx.h.
| #define CAN_F3R2_FB17 0x00020000U |
Filter bit 17
Definition at line 2513 of file stm32f407xx.h.
| #define CAN_F3R2_FB18 0x00040000U |
Filter bit 18
Definition at line 2514 of file stm32f407xx.h.
| #define CAN_F3R2_FB19 0x00080000U |
Filter bit 19
Definition at line 2515 of file stm32f407xx.h.
| #define CAN_F3R2_FB2 0x00000004U |
Filter bit 2
Definition at line 2498 of file stm32f407xx.h.
| #define CAN_F3R2_FB20 0x00100000U |
Filter bit 20
Definition at line 2516 of file stm32f407xx.h.
| #define CAN_F3R2_FB21 0x00200000U |
Filter bit 21
Definition at line 2517 of file stm32f407xx.h.
| #define CAN_F3R2_FB22 0x00400000U |
Filter bit 22
Definition at line 2518 of file stm32f407xx.h.
| #define CAN_F3R2_FB23 0x00800000U |
Filter bit 23
Definition at line 2519 of file stm32f407xx.h.
| #define CAN_F3R2_FB24 0x01000000U |
Filter bit 24
Definition at line 2520 of file stm32f407xx.h.
| #define CAN_F3R2_FB25 0x02000000U |
Filter bit 25
Definition at line 2521 of file stm32f407xx.h.
| #define CAN_F3R2_FB26 0x04000000U |
Filter bit 26
Definition at line 2522 of file stm32f407xx.h.
| #define CAN_F3R2_FB27 0x08000000U |
Filter bit 27
Definition at line 2523 of file stm32f407xx.h.
| #define CAN_F3R2_FB28 0x10000000U |
Filter bit 28
Definition at line 2524 of file stm32f407xx.h.
| #define CAN_F3R2_FB29 0x20000000U |
Filter bit 29
Definition at line 2525 of file stm32f407xx.h.
| #define CAN_F3R2_FB3 0x00000008U |
Filter bit 3
Definition at line 2499 of file stm32f407xx.h.
| #define CAN_F3R2_FB30 0x40000000U |
Filter bit 30
Definition at line 2526 of file stm32f407xx.h.
| #define CAN_F3R2_FB31 0x80000000U |
Filter bit 31
Definition at line 2527 of file stm32f407xx.h.
| #define CAN_F3R2_FB4 0x00000010U |
Filter bit 4
Definition at line 2500 of file stm32f407xx.h.
| #define CAN_F3R2_FB5 0x00000020U |
Filter bit 5
Definition at line 2501 of file stm32f407xx.h.
| #define CAN_F3R2_FB6 0x00000040U |
Filter bit 6
Definition at line 2502 of file stm32f407xx.h.
| #define CAN_F3R2_FB7 0x00000080U |
Filter bit 7
Definition at line 2503 of file stm32f407xx.h.
| #define CAN_F3R2_FB8 0x00000100U |
Filter bit 8
Definition at line 2504 of file stm32f407xx.h.
| #define CAN_F3R2_FB9 0x00000200U |
Filter bit 9
Definition at line 2505 of file stm32f407xx.h.
| #define CAN_F4R1_FB0 0x00000001U |
Filter bit 0
Definition at line 2054 of file stm32f407xx.h.
| #define CAN_F4R1_FB1 0x00000002U |
Filter bit 1
Definition at line 2055 of file stm32f407xx.h.
| #define CAN_F4R1_FB10 0x00000400U |
Filter bit 10
Definition at line 2064 of file stm32f407xx.h.
| #define CAN_F4R1_FB11 0x00000800U |
Filter bit 11
Definition at line 2065 of file stm32f407xx.h.
| #define CAN_F4R1_FB12 0x00001000U |
Filter bit 12
Definition at line 2066 of file stm32f407xx.h.
| #define CAN_F4R1_FB13 0x00002000U |
Filter bit 13
Definition at line 2067 of file stm32f407xx.h.
| #define CAN_F4R1_FB14 0x00004000U |
Filter bit 14
Definition at line 2068 of file stm32f407xx.h.
| #define CAN_F4R1_FB15 0x00008000U |
Filter bit 15
Definition at line 2069 of file stm32f407xx.h.
| #define CAN_F4R1_FB16 0x00010000U |
Filter bit 16
Definition at line 2070 of file stm32f407xx.h.
| #define CAN_F4R1_FB17 0x00020000U |
Filter bit 17
Definition at line 2071 of file stm32f407xx.h.
| #define CAN_F4R1_FB18 0x00040000U |
Filter bit 18
Definition at line 2072 of file stm32f407xx.h.
| #define CAN_F4R1_FB19 0x00080000U |
Filter bit 19
Definition at line 2073 of file stm32f407xx.h.
| #define CAN_F4R1_FB2 0x00000004U |
Filter bit 2
Definition at line 2056 of file stm32f407xx.h.
| #define CAN_F4R1_FB20 0x00100000U |
Filter bit 20
Definition at line 2074 of file stm32f407xx.h.
| #define CAN_F4R1_FB21 0x00200000U |
Filter bit 21
Definition at line 2075 of file stm32f407xx.h.
| #define CAN_F4R1_FB22 0x00400000U |
Filter bit 22
Definition at line 2076 of file stm32f407xx.h.
| #define CAN_F4R1_FB23 0x00800000U |
Filter bit 23
Definition at line 2077 of file stm32f407xx.h.
| #define CAN_F4R1_FB24 0x01000000U |
Filter bit 24
Definition at line 2078 of file stm32f407xx.h.
| #define CAN_F4R1_FB25 0x02000000U |
Filter bit 25
Definition at line 2079 of file stm32f407xx.h.
| #define CAN_F4R1_FB26 0x04000000U |
Filter bit 26
Definition at line 2080 of file stm32f407xx.h.
| #define CAN_F4R1_FB27 0x08000000U |
Filter bit 27
Definition at line 2081 of file stm32f407xx.h.
| #define CAN_F4R1_FB28 0x10000000U |
Filter bit 28
Definition at line 2082 of file stm32f407xx.h.
| #define CAN_F4R1_FB29 0x20000000U |
Filter bit 29
Definition at line 2083 of file stm32f407xx.h.
| #define CAN_F4R1_FB3 0x00000008U |
Filter bit 3
Definition at line 2057 of file stm32f407xx.h.
| #define CAN_F4R1_FB30 0x40000000U |
Filter bit 30
Definition at line 2084 of file stm32f407xx.h.
| #define CAN_F4R1_FB31 0x80000000U |
Filter bit 31
Definition at line 2085 of file stm32f407xx.h.
| #define CAN_F4R1_FB4 0x00000010U |
Filter bit 4
Definition at line 2058 of file stm32f407xx.h.
| #define CAN_F4R1_FB5 0x00000020U |
Filter bit 5
Definition at line 2059 of file stm32f407xx.h.
| #define CAN_F4R1_FB6 0x00000040U |
Filter bit 6
Definition at line 2060 of file stm32f407xx.h.
| #define CAN_F4R1_FB7 0x00000080U |
Filter bit 7
Definition at line 2061 of file stm32f407xx.h.
| #define CAN_F4R1_FB8 0x00000100U |
Filter bit 8
Definition at line 2062 of file stm32f407xx.h.
| #define CAN_F4R1_FB9 0x00000200U |
Filter bit 9
Definition at line 2063 of file stm32f407xx.h.
| #define CAN_F4R2_FB0 0x00000001U |
Filter bit 0
Definition at line 2530 of file stm32f407xx.h.
| #define CAN_F4R2_FB1 0x00000002U |
Filter bit 1
Definition at line 2531 of file stm32f407xx.h.
| #define CAN_F4R2_FB10 0x00000400U |
Filter bit 10
Definition at line 2540 of file stm32f407xx.h.
| #define CAN_F4R2_FB11 0x00000800U |
Filter bit 11
Definition at line 2541 of file stm32f407xx.h.
| #define CAN_F4R2_FB12 0x00001000U |
Filter bit 12
Definition at line 2542 of file stm32f407xx.h.
| #define CAN_F4R2_FB13 0x00002000U |
Filter bit 13
Definition at line 2543 of file stm32f407xx.h.
| #define CAN_F4R2_FB14 0x00004000U |
Filter bit 14
Definition at line 2544 of file stm32f407xx.h.
| #define CAN_F4R2_FB15 0x00008000U |
Filter bit 15
Definition at line 2545 of file stm32f407xx.h.
| #define CAN_F4R2_FB16 0x00010000U |
Filter bit 16
Definition at line 2546 of file stm32f407xx.h.
| #define CAN_F4R2_FB17 0x00020000U |
Filter bit 17
Definition at line 2547 of file stm32f407xx.h.
| #define CAN_F4R2_FB18 0x00040000U |
Filter bit 18
Definition at line 2548 of file stm32f407xx.h.
| #define CAN_F4R2_FB19 0x00080000U |
Filter bit 19
Definition at line 2549 of file stm32f407xx.h.
| #define CAN_F4R2_FB2 0x00000004U |
Filter bit 2
Definition at line 2532 of file stm32f407xx.h.
| #define CAN_F4R2_FB20 0x00100000U |
Filter bit 20
Definition at line 2550 of file stm32f407xx.h.
| #define CAN_F4R2_FB21 0x00200000U |
Filter bit 21
Definition at line 2551 of file stm32f407xx.h.
| #define CAN_F4R2_FB22 0x00400000U |
Filter bit 22
Definition at line 2552 of file stm32f407xx.h.
| #define CAN_F4R2_FB23 0x00800000U |
Filter bit 23
Definition at line 2553 of file stm32f407xx.h.
| #define CAN_F4R2_FB24 0x01000000U |
Filter bit 24
Definition at line 2554 of file stm32f407xx.h.
| #define CAN_F4R2_FB25 0x02000000U |
Filter bit 25
Definition at line 2555 of file stm32f407xx.h.
| #define CAN_F4R2_FB26 0x04000000U |
Filter bit 26
Definition at line 2556 of file stm32f407xx.h.
| #define CAN_F4R2_FB27 0x08000000U |
Filter bit 27
Definition at line 2557 of file stm32f407xx.h.
| #define CAN_F4R2_FB28 0x10000000U |
Filter bit 28
Definition at line 2558 of file stm32f407xx.h.
| #define CAN_F4R2_FB29 0x20000000U |
Filter bit 29
Definition at line 2559 of file stm32f407xx.h.
| #define CAN_F4R2_FB3 0x00000008U |
Filter bit 3
Definition at line 2533 of file stm32f407xx.h.
| #define CAN_F4R2_FB30 0x40000000U |
Filter bit 30
Definition at line 2560 of file stm32f407xx.h.
| #define CAN_F4R2_FB31 0x80000000U |
Filter bit 31
Definition at line 2561 of file stm32f407xx.h.
| #define CAN_F4R2_FB4 0x00000010U |
Filter bit 4
Definition at line 2534 of file stm32f407xx.h.
| #define CAN_F4R2_FB5 0x00000020U |
Filter bit 5
Definition at line 2535 of file stm32f407xx.h.
| #define CAN_F4R2_FB6 0x00000040U |
Filter bit 6
Definition at line 2536 of file stm32f407xx.h.
| #define CAN_F4R2_FB7 0x00000080U |
Filter bit 7
Definition at line 2537 of file stm32f407xx.h.
| #define CAN_F4R2_FB8 0x00000100U |
Filter bit 8
Definition at line 2538 of file stm32f407xx.h.
| #define CAN_F4R2_FB9 0x00000200U |
Filter bit 9
Definition at line 2539 of file stm32f407xx.h.
| #define CAN_F5R1_FB0 0x00000001U |
Filter bit 0
Definition at line 2088 of file stm32f407xx.h.
| #define CAN_F5R1_FB1 0x00000002U |
Filter bit 1
Definition at line 2089 of file stm32f407xx.h.
| #define CAN_F5R1_FB10 0x00000400U |
Filter bit 10
Definition at line 2098 of file stm32f407xx.h.
| #define CAN_F5R1_FB11 0x00000800U |
Filter bit 11
Definition at line 2099 of file stm32f407xx.h.
| #define CAN_F5R1_FB12 0x00001000U |
Filter bit 12
Definition at line 2100 of file stm32f407xx.h.
| #define CAN_F5R1_FB13 0x00002000U |
Filter bit 13
Definition at line 2101 of file stm32f407xx.h.
| #define CAN_F5R1_FB14 0x00004000U |
Filter bit 14
Definition at line 2102 of file stm32f407xx.h.
| #define CAN_F5R1_FB15 0x00008000U |
Filter bit 15
Definition at line 2103 of file stm32f407xx.h.
| #define CAN_F5R1_FB16 0x00010000U |
Filter bit 16
Definition at line 2104 of file stm32f407xx.h.
| #define CAN_F5R1_FB17 0x00020000U |
Filter bit 17
Definition at line 2105 of file stm32f407xx.h.
| #define CAN_F5R1_FB18 0x00040000U |
Filter bit 18
Definition at line 2106 of file stm32f407xx.h.
| #define CAN_F5R1_FB19 0x00080000U |
Filter bit 19
Definition at line 2107 of file stm32f407xx.h.
| #define CAN_F5R1_FB2 0x00000004U |
Filter bit 2
Definition at line 2090 of file stm32f407xx.h.
| #define CAN_F5R1_FB20 0x00100000U |
Filter bit 20
Definition at line 2108 of file stm32f407xx.h.
| #define CAN_F5R1_FB21 0x00200000U |
Filter bit 21
Definition at line 2109 of file stm32f407xx.h.
| #define CAN_F5R1_FB22 0x00400000U |
Filter bit 22
Definition at line 2110 of file stm32f407xx.h.
| #define CAN_F5R1_FB23 0x00800000U |
Filter bit 23
Definition at line 2111 of file stm32f407xx.h.
| #define CAN_F5R1_FB24 0x01000000U |
Filter bit 24
Definition at line 2112 of file stm32f407xx.h.
| #define CAN_F5R1_FB25 0x02000000U |
Filter bit 25
Definition at line 2113 of file stm32f407xx.h.
| #define CAN_F5R1_FB26 0x04000000U |
Filter bit 26
Definition at line 2114 of file stm32f407xx.h.
| #define CAN_F5R1_FB27 0x08000000U |
Filter bit 27
Definition at line 2115 of file stm32f407xx.h.
| #define CAN_F5R1_FB28 0x10000000U |
Filter bit 28
Definition at line 2116 of file stm32f407xx.h.
| #define CAN_F5R1_FB29 0x20000000U |
Filter bit 29
Definition at line 2117 of file stm32f407xx.h.
| #define CAN_F5R1_FB3 0x00000008U |
Filter bit 3
Definition at line 2091 of file stm32f407xx.h.
| #define CAN_F5R1_FB30 0x40000000U |
Filter bit 30
Definition at line 2118 of file stm32f407xx.h.
| #define CAN_F5R1_FB31 0x80000000U |
Filter bit 31
Definition at line 2119 of file stm32f407xx.h.
| #define CAN_F5R1_FB4 0x00000010U |
Filter bit 4
Definition at line 2092 of file stm32f407xx.h.
| #define CAN_F5R1_FB5 0x00000020U |
Filter bit 5
Definition at line 2093 of file stm32f407xx.h.
| #define CAN_F5R1_FB6 0x00000040U |
Filter bit 6
Definition at line 2094 of file stm32f407xx.h.
| #define CAN_F5R1_FB7 0x00000080U |
Filter bit 7
Definition at line 2095 of file stm32f407xx.h.
| #define CAN_F5R1_FB8 0x00000100U |
Filter bit 8
Definition at line 2096 of file stm32f407xx.h.
| #define CAN_F5R1_FB9 0x00000200U |
Filter bit 9
Definition at line 2097 of file stm32f407xx.h.
| #define CAN_F5R2_FB0 0x00000001U |
Filter bit 0
Definition at line 2564 of file stm32f407xx.h.
| #define CAN_F5R2_FB1 0x00000002U |
Filter bit 1
Definition at line 2565 of file stm32f407xx.h.
| #define CAN_F5R2_FB10 0x00000400U |
Filter bit 10
Definition at line 2574 of file stm32f407xx.h.
| #define CAN_F5R2_FB11 0x00000800U |
Filter bit 11
Definition at line 2575 of file stm32f407xx.h.
| #define CAN_F5R2_FB12 0x00001000U |
Filter bit 12
Definition at line 2576 of file stm32f407xx.h.
| #define CAN_F5R2_FB13 0x00002000U |
Filter bit 13
Definition at line 2577 of file stm32f407xx.h.
| #define CAN_F5R2_FB14 0x00004000U |
Filter bit 14
Definition at line 2578 of file stm32f407xx.h.
| #define CAN_F5R2_FB15 0x00008000U |
Filter bit 15
Definition at line 2579 of file stm32f407xx.h.
| #define CAN_F5R2_FB16 0x00010000U |
Filter bit 16
Definition at line 2580 of file stm32f407xx.h.
| #define CAN_F5R2_FB17 0x00020000U |
Filter bit 17
Definition at line 2581 of file stm32f407xx.h.
| #define CAN_F5R2_FB18 0x00040000U |
Filter bit 18
Definition at line 2582 of file stm32f407xx.h.
| #define CAN_F5R2_FB19 0x00080000U |
Filter bit 19
Definition at line 2583 of file stm32f407xx.h.
| #define CAN_F5R2_FB2 0x00000004U |
Filter bit 2
Definition at line 2566 of file stm32f407xx.h.
| #define CAN_F5R2_FB20 0x00100000U |
Filter bit 20
Definition at line 2584 of file stm32f407xx.h.
| #define CAN_F5R2_FB21 0x00200000U |
Filter bit 21
Definition at line 2585 of file stm32f407xx.h.
| #define CAN_F5R2_FB22 0x00400000U |
Filter bit 22
Definition at line 2586 of file stm32f407xx.h.
| #define CAN_F5R2_FB23 0x00800000U |
Filter bit 23
Definition at line 2587 of file stm32f407xx.h.
| #define CAN_F5R2_FB24 0x01000000U |
Filter bit 24
Definition at line 2588 of file stm32f407xx.h.
| #define CAN_F5R2_FB25 0x02000000U |
Filter bit 25
Definition at line 2589 of file stm32f407xx.h.
| #define CAN_F5R2_FB26 0x04000000U |
Filter bit 26
Definition at line 2590 of file stm32f407xx.h.
| #define CAN_F5R2_FB27 0x08000000U |
Filter bit 27
Definition at line 2591 of file stm32f407xx.h.
| #define CAN_F5R2_FB28 0x10000000U |
Filter bit 28
Definition at line 2592 of file stm32f407xx.h.
| #define CAN_F5R2_FB29 0x20000000U |
Filter bit 29
Definition at line 2593 of file stm32f407xx.h.
| #define CAN_F5R2_FB3 0x00000008U |
Filter bit 3
Definition at line 2567 of file stm32f407xx.h.
| #define CAN_F5R2_FB30 0x40000000U |
Filter bit 30
Definition at line 2594 of file stm32f407xx.h.
| #define CAN_F5R2_FB31 0x80000000U |
Filter bit 31
Definition at line 2595 of file stm32f407xx.h.
| #define CAN_F5R2_FB4 0x00000010U |
Filter bit 4
Definition at line 2568 of file stm32f407xx.h.
| #define CAN_F5R2_FB5 0x00000020U |
Filter bit 5
Definition at line 2569 of file stm32f407xx.h.
| #define CAN_F5R2_FB6 0x00000040U |
Filter bit 6
Definition at line 2570 of file stm32f407xx.h.
| #define CAN_F5R2_FB7 0x00000080U |
Filter bit 7
Definition at line 2571 of file stm32f407xx.h.
| #define CAN_F5R2_FB8 0x00000100U |
Filter bit 8
Definition at line 2572 of file stm32f407xx.h.
| #define CAN_F5R2_FB9 0x00000200U |
Filter bit 9
Definition at line 2573 of file stm32f407xx.h.
| #define CAN_F6R1_FB0 0x00000001U |
Filter bit 0
Definition at line 2122 of file stm32f407xx.h.
| #define CAN_F6R1_FB1 0x00000002U |
Filter bit 1
Definition at line 2123 of file stm32f407xx.h.
| #define CAN_F6R1_FB10 0x00000400U |
Filter bit 10
Definition at line 2132 of file stm32f407xx.h.
| #define CAN_F6R1_FB11 0x00000800U |
Filter bit 11
Definition at line 2133 of file stm32f407xx.h.
| #define CAN_F6R1_FB12 0x00001000U |
Filter bit 12
Definition at line 2134 of file stm32f407xx.h.
| #define CAN_F6R1_FB13 0x00002000U |
Filter bit 13
Definition at line 2135 of file stm32f407xx.h.
| #define CAN_F6R1_FB14 0x00004000U |
Filter bit 14
Definition at line 2136 of file stm32f407xx.h.
| #define CAN_F6R1_FB15 0x00008000U |
Filter bit 15
Definition at line 2137 of file stm32f407xx.h.
| #define CAN_F6R1_FB16 0x00010000U |
Filter bit 16
Definition at line 2138 of file stm32f407xx.h.
| #define CAN_F6R1_FB17 0x00020000U |
Filter bit 17
Definition at line 2139 of file stm32f407xx.h.
| #define CAN_F6R1_FB18 0x00040000U |
Filter bit 18
Definition at line 2140 of file stm32f407xx.h.
| #define CAN_F6R1_FB19 0x00080000U |
Filter bit 19
Definition at line 2141 of file stm32f407xx.h.
| #define CAN_F6R1_FB2 0x00000004U |
Filter bit 2
Definition at line 2124 of file stm32f407xx.h.
| #define CAN_F6R1_FB20 0x00100000U |
Filter bit 20
Definition at line 2142 of file stm32f407xx.h.
| #define CAN_F6R1_FB21 0x00200000U |
Filter bit 21
Definition at line 2143 of file stm32f407xx.h.
| #define CAN_F6R1_FB22 0x00400000U |
Filter bit 22
Definition at line 2144 of file stm32f407xx.h.
| #define CAN_F6R1_FB23 0x00800000U |
Filter bit 23
Definition at line 2145 of file stm32f407xx.h.
| #define CAN_F6R1_FB24 0x01000000U |
Filter bit 24
Definition at line 2146 of file stm32f407xx.h.
| #define CAN_F6R1_FB25 0x02000000U |
Filter bit 25
Definition at line 2147 of file stm32f407xx.h.
| #define CAN_F6R1_FB26 0x04000000U |
Filter bit 26
Definition at line 2148 of file stm32f407xx.h.
| #define CAN_F6R1_FB27 0x08000000U |
Filter bit 27
Definition at line 2149 of file stm32f407xx.h.
| #define CAN_F6R1_FB28 0x10000000U |
Filter bit 28
Definition at line 2150 of file stm32f407xx.h.
| #define CAN_F6R1_FB29 0x20000000U |
Filter bit 29
Definition at line 2151 of file stm32f407xx.h.
| #define CAN_F6R1_FB3 0x00000008U |
Filter bit 3
Definition at line 2125 of file stm32f407xx.h.
| #define CAN_F6R1_FB30 0x40000000U |
Filter bit 30
Definition at line 2152 of file stm32f407xx.h.
| #define CAN_F6R1_FB31 0x80000000U |
Filter bit 31
Definition at line 2153 of file stm32f407xx.h.
| #define CAN_F6R1_FB4 0x00000010U |
Filter bit 4
Definition at line 2126 of file stm32f407xx.h.
| #define CAN_F6R1_FB5 0x00000020U |
Filter bit 5
Definition at line 2127 of file stm32f407xx.h.
| #define CAN_F6R1_FB6 0x00000040U |
Filter bit 6
Definition at line 2128 of file stm32f407xx.h.
| #define CAN_F6R1_FB7 0x00000080U |
Filter bit 7
Definition at line 2129 of file stm32f407xx.h.
| #define CAN_F6R1_FB8 0x00000100U |
Filter bit 8
Definition at line 2130 of file stm32f407xx.h.
| #define CAN_F6R1_FB9 0x00000200U |
Filter bit 9
Definition at line 2131 of file stm32f407xx.h.
| #define CAN_F6R2_FB0 0x00000001U |
Filter bit 0
Definition at line 2598 of file stm32f407xx.h.
| #define CAN_F6R2_FB1 0x00000002U |
Filter bit 1
Definition at line 2599 of file stm32f407xx.h.
| #define CAN_F6R2_FB10 0x00000400U |
Filter bit 10
Definition at line 2608 of file stm32f407xx.h.
| #define CAN_F6R2_FB11 0x00000800U |
Filter bit 11
Definition at line 2609 of file stm32f407xx.h.
| #define CAN_F6R2_FB12 0x00001000U |
Filter bit 12
Definition at line 2610 of file stm32f407xx.h.
| #define CAN_F6R2_FB13 0x00002000U |
Filter bit 13
Definition at line 2611 of file stm32f407xx.h.
| #define CAN_F6R2_FB14 0x00004000U |
Filter bit 14
Definition at line 2612 of file stm32f407xx.h.
| #define CAN_F6R2_FB15 0x00008000U |
Filter bit 15
Definition at line 2613 of file stm32f407xx.h.
| #define CAN_F6R2_FB16 0x00010000U |
Filter bit 16
Definition at line 2614 of file stm32f407xx.h.
| #define CAN_F6R2_FB17 0x00020000U |
Filter bit 17
Definition at line 2615 of file stm32f407xx.h.
| #define CAN_F6R2_FB18 0x00040000U |
Filter bit 18
Definition at line 2616 of file stm32f407xx.h.
| #define CAN_F6R2_FB19 0x00080000U |
Filter bit 19
Definition at line 2617 of file stm32f407xx.h.
| #define CAN_F6R2_FB2 0x00000004U |
Filter bit 2
Definition at line 2600 of file stm32f407xx.h.
| #define CAN_F6R2_FB20 0x00100000U |
Filter bit 20
Definition at line 2618 of file stm32f407xx.h.
| #define CAN_F6R2_FB21 0x00200000U |
Filter bit 21
Definition at line 2619 of file stm32f407xx.h.
| #define CAN_F6R2_FB22 0x00400000U |
Filter bit 22
Definition at line 2620 of file stm32f407xx.h.
| #define CAN_F6R2_FB23 0x00800000U |
Filter bit 23
Definition at line 2621 of file stm32f407xx.h.
| #define CAN_F6R2_FB24 0x01000000U |
Filter bit 24
Definition at line 2622 of file stm32f407xx.h.
| #define CAN_F6R2_FB25 0x02000000U |
Filter bit 25
Definition at line 2623 of file stm32f407xx.h.
| #define CAN_F6R2_FB26 0x04000000U |
Filter bit 26
Definition at line 2624 of file stm32f407xx.h.
| #define CAN_F6R2_FB27 0x08000000U |
Filter bit 27
Definition at line 2625 of file stm32f407xx.h.
| #define CAN_F6R2_FB28 0x10000000U |
Filter bit 28
Definition at line 2626 of file stm32f407xx.h.
| #define CAN_F6R2_FB29 0x20000000U |
Filter bit 29
Definition at line 2627 of file stm32f407xx.h.
| #define CAN_F6R2_FB3 0x00000008U |
Filter bit 3
Definition at line 2601 of file stm32f407xx.h.
| #define CAN_F6R2_FB30 0x40000000U |
Filter bit 30
Definition at line 2628 of file stm32f407xx.h.
| #define CAN_F6R2_FB31 0x80000000U |
Filter bit 31
Definition at line 2629 of file stm32f407xx.h.
| #define CAN_F6R2_FB4 0x00000010U |
Filter bit 4
Definition at line 2602 of file stm32f407xx.h.
| #define CAN_F6R2_FB5 0x00000020U |
Filter bit 5
Definition at line 2603 of file stm32f407xx.h.
| #define CAN_F6R2_FB6 0x00000040U |
Filter bit 6
Definition at line 2604 of file stm32f407xx.h.
| #define CAN_F6R2_FB7 0x00000080U |
Filter bit 7
Definition at line 2605 of file stm32f407xx.h.
| #define CAN_F6R2_FB8 0x00000100U |
Filter bit 8
Definition at line 2606 of file stm32f407xx.h.
| #define CAN_F6R2_FB9 0x00000200U |
Filter bit 9
Definition at line 2607 of file stm32f407xx.h.
| #define CAN_F7R1_FB0 0x00000001U |
Filter bit 0
Definition at line 2156 of file stm32f407xx.h.
| #define CAN_F7R1_FB1 0x00000002U |
Filter bit 1
Definition at line 2157 of file stm32f407xx.h.
| #define CAN_F7R1_FB10 0x00000400U |
Filter bit 10
Definition at line 2166 of file stm32f407xx.h.
| #define CAN_F7R1_FB11 0x00000800U |
Filter bit 11
Definition at line 2167 of file stm32f407xx.h.
| #define CAN_F7R1_FB12 0x00001000U |
Filter bit 12
Definition at line 2168 of file stm32f407xx.h.
| #define CAN_F7R1_FB13 0x00002000U |
Filter bit 13
Definition at line 2169 of file stm32f407xx.h.
| #define CAN_F7R1_FB14 0x00004000U |
Filter bit 14
Definition at line 2170 of file stm32f407xx.h.
| #define CAN_F7R1_FB15 0x00008000U |
Filter bit 15
Definition at line 2171 of file stm32f407xx.h.
| #define CAN_F7R1_FB16 0x00010000U |
Filter bit 16
Definition at line 2172 of file stm32f407xx.h.
| #define CAN_F7R1_FB17 0x00020000U |
Filter bit 17
Definition at line 2173 of file stm32f407xx.h.
| #define CAN_F7R1_FB18 0x00040000U |
Filter bit 18
Definition at line 2174 of file stm32f407xx.h.
| #define CAN_F7R1_FB19 0x00080000U |
Filter bit 19
Definition at line 2175 of file stm32f407xx.h.
| #define CAN_F7R1_FB2 0x00000004U |
Filter bit 2
Definition at line 2158 of file stm32f407xx.h.
| #define CAN_F7R1_FB20 0x00100000U |
Filter bit 20
Definition at line 2176 of file stm32f407xx.h.
| #define CAN_F7R1_FB21 0x00200000U |
Filter bit 21
Definition at line 2177 of file stm32f407xx.h.
| #define CAN_F7R1_FB22 0x00400000U |
Filter bit 22
Definition at line 2178 of file stm32f407xx.h.
| #define CAN_F7R1_FB23 0x00800000U |
Filter bit 23
Definition at line 2179 of file stm32f407xx.h.
| #define CAN_F7R1_FB24 0x01000000U |
Filter bit 24
Definition at line 2180 of file stm32f407xx.h.
| #define CAN_F7R1_FB25 0x02000000U |
Filter bit 25
Definition at line 2181 of file stm32f407xx.h.
| #define CAN_F7R1_FB26 0x04000000U |
Filter bit 26
Definition at line 2182 of file stm32f407xx.h.
| #define CAN_F7R1_FB27 0x08000000U |
Filter bit 27
Definition at line 2183 of file stm32f407xx.h.
| #define CAN_F7R1_FB28 0x10000000U |
Filter bit 28
Definition at line 2184 of file stm32f407xx.h.
| #define CAN_F7R1_FB29 0x20000000U |
Filter bit 29
Definition at line 2185 of file stm32f407xx.h.
| #define CAN_F7R1_FB3 0x00000008U |
Filter bit 3
Definition at line 2159 of file stm32f407xx.h.
| #define CAN_F7R1_FB30 0x40000000U |
Filter bit 30
Definition at line 2186 of file stm32f407xx.h.
| #define CAN_F7R1_FB31 0x80000000U |
Filter bit 31
Definition at line 2187 of file stm32f407xx.h.
| #define CAN_F7R1_FB4 0x00000010U |
Filter bit 4
Definition at line 2160 of file stm32f407xx.h.
| #define CAN_F7R1_FB5 0x00000020U |
Filter bit 5
Definition at line 2161 of file stm32f407xx.h.
| #define CAN_F7R1_FB6 0x00000040U |
Filter bit 6
Definition at line 2162 of file stm32f407xx.h.
| #define CAN_F7R1_FB7 0x00000080U |
Filter bit 7
Definition at line 2163 of file stm32f407xx.h.
| #define CAN_F7R1_FB8 0x00000100U |
Filter bit 8
Definition at line 2164 of file stm32f407xx.h.
| #define CAN_F7R1_FB9 0x00000200U |
Filter bit 9
Definition at line 2165 of file stm32f407xx.h.
| #define CAN_F7R2_FB0 0x00000001U |
Filter bit 0
Definition at line 2632 of file stm32f407xx.h.
| #define CAN_F7R2_FB1 0x00000002U |
Filter bit 1
Definition at line 2633 of file stm32f407xx.h.
| #define CAN_F7R2_FB10 0x00000400U |
Filter bit 10
Definition at line 2642 of file stm32f407xx.h.
| #define CAN_F7R2_FB11 0x00000800U |
Filter bit 11
Definition at line 2643 of file stm32f407xx.h.
| #define CAN_F7R2_FB12 0x00001000U |
Filter bit 12
Definition at line 2644 of file stm32f407xx.h.
| #define CAN_F7R2_FB13 0x00002000U |
Filter bit 13
Definition at line 2645 of file stm32f407xx.h.
| #define CAN_F7R2_FB14 0x00004000U |
Filter bit 14
Definition at line 2646 of file stm32f407xx.h.
| #define CAN_F7R2_FB15 0x00008000U |
Filter bit 15
Definition at line 2647 of file stm32f407xx.h.
| #define CAN_F7R2_FB16 0x00010000U |
Filter bit 16
Definition at line 2648 of file stm32f407xx.h.
| #define CAN_F7R2_FB17 0x00020000U |
Filter bit 17
Definition at line 2649 of file stm32f407xx.h.
| #define CAN_F7R2_FB18 0x00040000U |
Filter bit 18
Definition at line 2650 of file stm32f407xx.h.
| #define CAN_F7R2_FB19 0x00080000U |
Filter bit 19
Definition at line 2651 of file stm32f407xx.h.
| #define CAN_F7R2_FB2 0x00000004U |
Filter bit 2
Definition at line 2634 of file stm32f407xx.h.
| #define CAN_F7R2_FB20 0x00100000U |
Filter bit 20
Definition at line 2652 of file stm32f407xx.h.
| #define CAN_F7R2_FB21 0x00200000U |
Filter bit 21
Definition at line 2653 of file stm32f407xx.h.
| #define CAN_F7R2_FB22 0x00400000U |
Filter bit 22
Definition at line 2654 of file stm32f407xx.h.
| #define CAN_F7R2_FB23 0x00800000U |
Filter bit 23
Definition at line 2655 of file stm32f407xx.h.
| #define CAN_F7R2_FB24 0x01000000U |
Filter bit 24
Definition at line 2656 of file stm32f407xx.h.
| #define CAN_F7R2_FB25 0x02000000U |
Filter bit 25
Definition at line 2657 of file stm32f407xx.h.
| #define CAN_F7R2_FB26 0x04000000U |
Filter bit 26
Definition at line 2658 of file stm32f407xx.h.
| #define CAN_F7R2_FB27 0x08000000U |
Filter bit 27
Definition at line 2659 of file stm32f407xx.h.
| #define CAN_F7R2_FB28 0x10000000U |
Filter bit 28
Definition at line 2660 of file stm32f407xx.h.
| #define CAN_F7R2_FB29 0x20000000U |
Filter bit 29
Definition at line 2661 of file stm32f407xx.h.
| #define CAN_F7R2_FB3 0x00000008U |
Filter bit 3
Definition at line 2635 of file stm32f407xx.h.
| #define CAN_F7R2_FB30 0x40000000U |
Filter bit 30
Definition at line 2662 of file stm32f407xx.h.
| #define CAN_F7R2_FB31 0x80000000U |
Filter bit 31
Definition at line 2663 of file stm32f407xx.h.
| #define CAN_F7R2_FB4 0x00000010U |
Filter bit 4
Definition at line 2636 of file stm32f407xx.h.
| #define CAN_F7R2_FB5 0x00000020U |
Filter bit 5
Definition at line 2637 of file stm32f407xx.h.
| #define CAN_F7R2_FB6 0x00000040U |
Filter bit 6
Definition at line 2638 of file stm32f407xx.h.
| #define CAN_F7R2_FB7 0x00000080U |
Filter bit 7
Definition at line 2639 of file stm32f407xx.h.
| #define CAN_F7R2_FB8 0x00000100U |
Filter bit 8
Definition at line 2640 of file stm32f407xx.h.
| #define CAN_F7R2_FB9 0x00000200U |
Filter bit 9
Definition at line 2641 of file stm32f407xx.h.
| #define CAN_F8R1_FB0 0x00000001U |
Filter bit 0
Definition at line 2190 of file stm32f407xx.h.
| #define CAN_F8R1_FB1 0x00000002U |
Filter bit 1
Definition at line 2191 of file stm32f407xx.h.
| #define CAN_F8R1_FB10 0x00000400U |
Filter bit 10
Definition at line 2200 of file stm32f407xx.h.
| #define CAN_F8R1_FB11 0x00000800U |
Filter bit 11
Definition at line 2201 of file stm32f407xx.h.
| #define CAN_F8R1_FB12 0x00001000U |
Filter bit 12
Definition at line 2202 of file stm32f407xx.h.
| #define CAN_F8R1_FB13 0x00002000U |
Filter bit 13
Definition at line 2203 of file stm32f407xx.h.
| #define CAN_F8R1_FB14 0x00004000U |
Filter bit 14
Definition at line 2204 of file stm32f407xx.h.
| #define CAN_F8R1_FB15 0x00008000U |
Filter bit 15
Definition at line 2205 of file stm32f407xx.h.
| #define CAN_F8R1_FB16 0x00010000U |
Filter bit 16
Definition at line 2206 of file stm32f407xx.h.
| #define CAN_F8R1_FB17 0x00020000U |
Filter bit 17
Definition at line 2207 of file stm32f407xx.h.
| #define CAN_F8R1_FB18 0x00040000U |
Filter bit 18
Definition at line 2208 of file stm32f407xx.h.
| #define CAN_F8R1_FB19 0x00080000U |
Filter bit 19
Definition at line 2209 of file stm32f407xx.h.
| #define CAN_F8R1_FB2 0x00000004U |
Filter bit 2
Definition at line 2192 of file stm32f407xx.h.
| #define CAN_F8R1_FB20 0x00100000U |
Filter bit 20
Definition at line 2210 of file stm32f407xx.h.
| #define CAN_F8R1_FB21 0x00200000U |
Filter bit 21
Definition at line 2211 of file stm32f407xx.h.
| #define CAN_F8R1_FB22 0x00400000U |
Filter bit 22
Definition at line 2212 of file stm32f407xx.h.
| #define CAN_F8R1_FB23 0x00800000U |
Filter bit 23
Definition at line 2213 of file stm32f407xx.h.
| #define CAN_F8R1_FB24 0x01000000U |
Filter bit 24
Definition at line 2214 of file stm32f407xx.h.
| #define CAN_F8R1_FB25 0x02000000U |
Filter bit 25
Definition at line 2215 of file stm32f407xx.h.
| #define CAN_F8R1_FB26 0x04000000U |
Filter bit 26
Definition at line 2216 of file stm32f407xx.h.
| #define CAN_F8R1_FB27 0x08000000U |
Filter bit 27
Definition at line 2217 of file stm32f407xx.h.
| #define CAN_F8R1_FB28 0x10000000U |
Filter bit 28
Definition at line 2218 of file stm32f407xx.h.
| #define CAN_F8R1_FB29 0x20000000U |
Filter bit 29
Definition at line 2219 of file stm32f407xx.h.
| #define CAN_F8R1_FB3 0x00000008U |
Filter bit 3
Definition at line 2193 of file stm32f407xx.h.
| #define CAN_F8R1_FB30 0x40000000U |
Filter bit 30
Definition at line 2220 of file stm32f407xx.h.
| #define CAN_F8R1_FB31 0x80000000U |
Filter bit 31
Definition at line 2221 of file stm32f407xx.h.
| #define CAN_F8R1_FB4 0x00000010U |
Filter bit 4
Definition at line 2194 of file stm32f407xx.h.
| #define CAN_F8R1_FB5 0x00000020U |
Filter bit 5
Definition at line 2195 of file stm32f407xx.h.
| #define CAN_F8R1_FB6 0x00000040U |
Filter bit 6
Definition at line 2196 of file stm32f407xx.h.
| #define CAN_F8R1_FB7 0x00000080U |
Filter bit 7
Definition at line 2197 of file stm32f407xx.h.
| #define CAN_F8R1_FB8 0x00000100U |
Filter bit 8
Definition at line 2198 of file stm32f407xx.h.
| #define CAN_F8R1_FB9 0x00000200U |
Filter bit 9
Definition at line 2199 of file stm32f407xx.h.
| #define CAN_F8R2_FB0 0x00000001U |
Filter bit 0
Definition at line 2666 of file stm32f407xx.h.
| #define CAN_F8R2_FB1 0x00000002U |
Filter bit 1
Definition at line 2667 of file stm32f407xx.h.
| #define CAN_F8R2_FB10 0x00000400U |
Filter bit 10
Definition at line 2676 of file stm32f407xx.h.
| #define CAN_F8R2_FB11 0x00000800U |
Filter bit 11
Definition at line 2677 of file stm32f407xx.h.
| #define CAN_F8R2_FB12 0x00001000U |
Filter bit 12
Definition at line 2678 of file stm32f407xx.h.
| #define CAN_F8R2_FB13 0x00002000U |
Filter bit 13
Definition at line 2679 of file stm32f407xx.h.
| #define CAN_F8R2_FB14 0x00004000U |
Filter bit 14
Definition at line 2680 of file stm32f407xx.h.
| #define CAN_F8R2_FB15 0x00008000U |
Filter bit 15
Definition at line 2681 of file stm32f407xx.h.
| #define CAN_F8R2_FB16 0x00010000U |
Filter bit 16
Definition at line 2682 of file stm32f407xx.h.
| #define CAN_F8R2_FB17 0x00020000U |
Filter bit 17
Definition at line 2683 of file stm32f407xx.h.
| #define CAN_F8R2_FB18 0x00040000U |
Filter bit 18
Definition at line 2684 of file stm32f407xx.h.
| #define CAN_F8R2_FB19 0x00080000U |
Filter bit 19
Definition at line 2685 of file stm32f407xx.h.
| #define CAN_F8R2_FB2 0x00000004U |
Filter bit 2
Definition at line 2668 of file stm32f407xx.h.
| #define CAN_F8R2_FB20 0x00100000U |
Filter bit 20
Definition at line 2686 of file stm32f407xx.h.
| #define CAN_F8R2_FB21 0x00200000U |
Filter bit 21
Definition at line 2687 of file stm32f407xx.h.
| #define CAN_F8R2_FB22 0x00400000U |
Filter bit 22
Definition at line 2688 of file stm32f407xx.h.
| #define CAN_F8R2_FB23 0x00800000U |
Filter bit 23
Definition at line 2689 of file stm32f407xx.h.
| #define CAN_F8R2_FB24 0x01000000U |
Filter bit 24
Definition at line 2690 of file stm32f407xx.h.
| #define CAN_F8R2_FB25 0x02000000U |
Filter bit 25
Definition at line 2691 of file stm32f407xx.h.
| #define CAN_F8R2_FB26 0x04000000U |
Filter bit 26
Definition at line 2692 of file stm32f407xx.h.
| #define CAN_F8R2_FB27 0x08000000U |
Filter bit 27
Definition at line 2693 of file stm32f407xx.h.
| #define CAN_F8R2_FB28 0x10000000U |
Filter bit 28
Definition at line 2694 of file stm32f407xx.h.
| #define CAN_F8R2_FB29 0x20000000U |
Filter bit 29
Definition at line 2695 of file stm32f407xx.h.
| #define CAN_F8R2_FB3 0x00000008U |
Filter bit 3
Definition at line 2669 of file stm32f407xx.h.
| #define CAN_F8R2_FB30 0x40000000U |
Filter bit 30
Definition at line 2696 of file stm32f407xx.h.
| #define CAN_F8R2_FB31 0x80000000U |
Filter bit 31
Definition at line 2697 of file stm32f407xx.h.
| #define CAN_F8R2_FB4 0x00000010U |
Filter bit 4
Definition at line 2670 of file stm32f407xx.h.
| #define CAN_F8R2_FB5 0x00000020U |
Filter bit 5
Definition at line 2671 of file stm32f407xx.h.
| #define CAN_F8R2_FB6 0x00000040U |
Filter bit 6
Definition at line 2672 of file stm32f407xx.h.
| #define CAN_F8R2_FB7 0x00000080U |
Filter bit 7
Definition at line 2673 of file stm32f407xx.h.
| #define CAN_F8R2_FB8 0x00000100U |
Filter bit 8
Definition at line 2674 of file stm32f407xx.h.
| #define CAN_F8R2_FB9 0x00000200U |
Filter bit 9
Definition at line 2675 of file stm32f407xx.h.
| #define CAN_F9R1_FB0 0x00000001U |
Filter bit 0
Definition at line 2224 of file stm32f407xx.h.
| #define CAN_F9R1_FB1 0x00000002U |
Filter bit 1
Definition at line 2225 of file stm32f407xx.h.
| #define CAN_F9R1_FB10 0x00000400U |
Filter bit 10
Definition at line 2234 of file stm32f407xx.h.
| #define CAN_F9R1_FB11 0x00000800U |
Filter bit 11
Definition at line 2235 of file stm32f407xx.h.
| #define CAN_F9R1_FB12 0x00001000U |
Filter bit 12
Definition at line 2236 of file stm32f407xx.h.
| #define CAN_F9R1_FB13 0x00002000U |
Filter bit 13
Definition at line 2237 of file stm32f407xx.h.
| #define CAN_F9R1_FB14 0x00004000U |
Filter bit 14
Definition at line 2238 of file stm32f407xx.h.
| #define CAN_F9R1_FB15 0x00008000U |
Filter bit 15
Definition at line 2239 of file stm32f407xx.h.
| #define CAN_F9R1_FB16 0x00010000U |
Filter bit 16
Definition at line 2240 of file stm32f407xx.h.
| #define CAN_F9R1_FB17 0x00020000U |
Filter bit 17
Definition at line 2241 of file stm32f407xx.h.
| #define CAN_F9R1_FB18 0x00040000U |
Filter bit 18
Definition at line 2242 of file stm32f407xx.h.
| #define CAN_F9R1_FB19 0x00080000U |
Filter bit 19
Definition at line 2243 of file stm32f407xx.h.
| #define CAN_F9R1_FB2 0x00000004U |
Filter bit 2
Definition at line 2226 of file stm32f407xx.h.
| #define CAN_F9R1_FB20 0x00100000U |
Filter bit 20
Definition at line 2244 of file stm32f407xx.h.
| #define CAN_F9R1_FB21 0x00200000U |
Filter bit 21
Definition at line 2245 of file stm32f407xx.h.
| #define CAN_F9R1_FB22 0x00400000U |
Filter bit 22
Definition at line 2246 of file stm32f407xx.h.
| #define CAN_F9R1_FB23 0x00800000U |
Filter bit 23
Definition at line 2247 of file stm32f407xx.h.
| #define CAN_F9R1_FB24 0x01000000U |
Filter bit 24
Definition at line 2248 of file stm32f407xx.h.
| #define CAN_F9R1_FB25 0x02000000U |
Filter bit 25
Definition at line 2249 of file stm32f407xx.h.
| #define CAN_F9R1_FB26 0x04000000U |
Filter bit 26
Definition at line 2250 of file stm32f407xx.h.
| #define CAN_F9R1_FB27 0x08000000U |
Filter bit 27
Definition at line 2251 of file stm32f407xx.h.
| #define CAN_F9R1_FB28 0x10000000U |
Filter bit 28
Definition at line 2252 of file stm32f407xx.h.
| #define CAN_F9R1_FB29 0x20000000U |
Filter bit 29
Definition at line 2253 of file stm32f407xx.h.
| #define CAN_F9R1_FB3 0x00000008U |
Filter bit 3
Definition at line 2227 of file stm32f407xx.h.
| #define CAN_F9R1_FB30 0x40000000U |
Filter bit 30
Definition at line 2254 of file stm32f407xx.h.
| #define CAN_F9R1_FB31 0x80000000U |
Filter bit 31
Definition at line 2255 of file stm32f407xx.h.
| #define CAN_F9R1_FB4 0x00000010U |
Filter bit 4
Definition at line 2228 of file stm32f407xx.h.
| #define CAN_F9R1_FB5 0x00000020U |
Filter bit 5
Definition at line 2229 of file stm32f407xx.h.
| #define CAN_F9R1_FB6 0x00000040U |
Filter bit 6
Definition at line 2230 of file stm32f407xx.h.
| #define CAN_F9R1_FB7 0x00000080U |
Filter bit 7
Definition at line 2231 of file stm32f407xx.h.
| #define CAN_F9R1_FB8 0x00000100U |
Filter bit 8
Definition at line 2232 of file stm32f407xx.h.
| #define CAN_F9R1_FB9 0x00000200U |
Filter bit 9
Definition at line 2233 of file stm32f407xx.h.
| #define CAN_F9R2_FB0 0x00000001U |
Filter bit 0
Definition at line 2700 of file stm32f407xx.h.
| #define CAN_F9R2_FB1 0x00000002U |
Filter bit 1
Definition at line 2701 of file stm32f407xx.h.
| #define CAN_F9R2_FB10 0x00000400U |
Filter bit 10
Definition at line 2710 of file stm32f407xx.h.
| #define CAN_F9R2_FB11 0x00000800U |
Filter bit 11
Definition at line 2711 of file stm32f407xx.h.
| #define CAN_F9R2_FB12 0x00001000U |
Filter bit 12
Definition at line 2712 of file stm32f407xx.h.
| #define CAN_F9R2_FB13 0x00002000U |
Filter bit 13
Definition at line 2713 of file stm32f407xx.h.
| #define CAN_F9R2_FB14 0x00004000U |
Filter bit 14
Definition at line 2714 of file stm32f407xx.h.
| #define CAN_F9R2_FB15 0x00008000U |
Filter bit 15
Definition at line 2715 of file stm32f407xx.h.
| #define CAN_F9R2_FB16 0x00010000U |
Filter bit 16
Definition at line 2716 of file stm32f407xx.h.
| #define CAN_F9R2_FB17 0x00020000U |
Filter bit 17
Definition at line 2717 of file stm32f407xx.h.
| #define CAN_F9R2_FB18 0x00040000U |
Filter bit 18
Definition at line 2718 of file stm32f407xx.h.
| #define CAN_F9R2_FB19 0x00080000U |
Filter bit 19
Definition at line 2719 of file stm32f407xx.h.
| #define CAN_F9R2_FB2 0x00000004U |
Filter bit 2
Definition at line 2702 of file stm32f407xx.h.
| #define CAN_F9R2_FB20 0x00100000U |
Filter bit 20
Definition at line 2720 of file stm32f407xx.h.
| #define CAN_F9R2_FB21 0x00200000U |
Filter bit 21
Definition at line 2721 of file stm32f407xx.h.
| #define CAN_F9R2_FB22 0x00400000U |
Filter bit 22
Definition at line 2722 of file stm32f407xx.h.
| #define CAN_F9R2_FB23 0x00800000U |
Filter bit 23
Definition at line 2723 of file stm32f407xx.h.
| #define CAN_F9R2_FB24 0x01000000U |
Filter bit 24
Definition at line 2724 of file stm32f407xx.h.
| #define CAN_F9R2_FB25 0x02000000U |
Filter bit 25
Definition at line 2725 of file stm32f407xx.h.
| #define CAN_F9R2_FB26 0x04000000U |
Filter bit 26
Definition at line 2726 of file stm32f407xx.h.
| #define CAN_F9R2_FB27 0x08000000U |
Filter bit 27
Definition at line 2727 of file stm32f407xx.h.
| #define CAN_F9R2_FB28 0x10000000U |
Filter bit 28
Definition at line 2728 of file stm32f407xx.h.
| #define CAN_F9R2_FB29 0x20000000U |
Filter bit 29
Definition at line 2729 of file stm32f407xx.h.
| #define CAN_F9R2_FB3 0x00000008U |
Filter bit 3
Definition at line 2703 of file stm32f407xx.h.
| #define CAN_F9R2_FB30 0x40000000U |
Filter bit 30
Definition at line 2730 of file stm32f407xx.h.
| #define CAN_F9R2_FB31 0x80000000U |
Filter bit 31
Definition at line 2731 of file stm32f407xx.h.
| #define CAN_F9R2_FB4 0x00000010U |
Filter bit 4
Definition at line 2704 of file stm32f407xx.h.
| #define CAN_F9R2_FB5 0x00000020U |
Filter bit 5
Definition at line 2705 of file stm32f407xx.h.
| #define CAN_F9R2_FB6 0x00000040U |
Filter bit 6
Definition at line 2706 of file stm32f407xx.h.
| #define CAN_F9R2_FB7 0x00000080U |
Filter bit 7
Definition at line 2707 of file stm32f407xx.h.
| #define CAN_F9R2_FB8 0x00000100U |
Filter bit 8
Definition at line 2708 of file stm32f407xx.h.
| #define CAN_F9R2_FB9 0x00000200U |
Filter bit 9
Definition at line 2709 of file stm32f407xx.h.
| #define CAN_FA1R_FACT 0x0FFFFFFFU |
Filter Active
Definition at line 1887 of file stm32f407xx.h.
| #define CAN_FA1R_FACT0 0x00000001U |
Filter Active bit 0
Definition at line 1888 of file stm32f407xx.h.
| #define CAN_FA1R_FACT1 0x00000002U |
Filter Active bit 1
Definition at line 1889 of file stm32f407xx.h.
| #define CAN_FA1R_FACT10 0x00000400U |
Filter Active bit 10
Definition at line 1898 of file stm32f407xx.h.
| #define CAN_FA1R_FACT11 0x00000800U |
Filter Active bit 11
Definition at line 1899 of file stm32f407xx.h.
| #define CAN_FA1R_FACT12 0x00001000U |
Filter Active bit 12
Definition at line 1900 of file stm32f407xx.h.
| #define CAN_FA1R_FACT13 0x00002000U |
Filter Active bit 13
Definition at line 1901 of file stm32f407xx.h.
| #define CAN_FA1R_FACT14 0x00004000U |
Filter Active bit 14
Definition at line 1902 of file stm32f407xx.h.
| #define CAN_FA1R_FACT15 0x00008000U |
Filter Active bit 15
Definition at line 1903 of file stm32f407xx.h.
| #define CAN_FA1R_FACT16 0x00010000U |
Filter Active bit 16
Definition at line 1904 of file stm32f407xx.h.
| #define CAN_FA1R_FACT17 0x00020000U |
Filter Active bit 17
Definition at line 1905 of file stm32f407xx.h.
| #define CAN_FA1R_FACT18 0x00040000U |
Filter Active bit 18
Definition at line 1906 of file stm32f407xx.h.
| #define CAN_FA1R_FACT19 0x00080000U |
Filter Active bit 19
Definition at line 1907 of file stm32f407xx.h.
| #define CAN_FA1R_FACT2 0x00000004U |
Filter Active bit 2
Definition at line 1890 of file stm32f407xx.h.
| #define CAN_FA1R_FACT20 0x00100000U |
Filter Active bit 20
Definition at line 1908 of file stm32f407xx.h.
| #define CAN_FA1R_FACT21 0x00200000U |
Filter Active bit 21
Definition at line 1909 of file stm32f407xx.h.
| #define CAN_FA1R_FACT22 0x00400000U |
Filter Active bit 22
Definition at line 1910 of file stm32f407xx.h.
| #define CAN_FA1R_FACT23 0x00800000U |
Filter Active bit 23
Definition at line 1911 of file stm32f407xx.h.
| #define CAN_FA1R_FACT24 0x01000000U |
Filter Active bit 24
Definition at line 1912 of file stm32f407xx.h.
| #define CAN_FA1R_FACT25 0x02000000U |
Filter Active bit 25
Definition at line 1913 of file stm32f407xx.h.
| #define CAN_FA1R_FACT26 0x04000000U |
Filter Active bit 26
Definition at line 1914 of file stm32f407xx.h.
| #define CAN_FA1R_FACT27 0x08000000U |
Filter Active bit 27
Definition at line 1915 of file stm32f407xx.h.
| #define CAN_FA1R_FACT3 0x00000008U |
Filter Active bit 3
Definition at line 1891 of file stm32f407xx.h.
| #define CAN_FA1R_FACT4 0x00000010U |
Filter Active bit 4
Definition at line 1892 of file stm32f407xx.h.
| #define CAN_FA1R_FACT5 0x00000020U |
Filter Active bit 5
Definition at line 1893 of file stm32f407xx.h.
| #define CAN_FA1R_FACT6 0x00000040U |
Filter Active bit 6
Definition at line 1894 of file stm32f407xx.h.
| #define CAN_FA1R_FACT7 0x00000080U |
Filter Active bit 7
Definition at line 1895 of file stm32f407xx.h.
| #define CAN_FA1R_FACT8 0x00000100U |
Filter Active bit 8
Definition at line 1896 of file stm32f407xx.h.
| #define CAN_FA1R_FACT9 0x00000200U |
Filter Active bit 9
Definition at line 1897 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA 0x0FFFFFFFU |
Filter FIFO Assignment
Definition at line 1856 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA0 0x00000001U |
Filter FIFO Assignment bit 0
Definition at line 1857 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA1 0x00000002U |
Filter FIFO Assignment bit 1
Definition at line 1858 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA10 0x00000400U |
Filter FIFO Assignment bit 10
Definition at line 1867 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA11 0x00000800U |
Filter FIFO Assignment bit 11
Definition at line 1868 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA12 0x00001000U |
Filter FIFO Assignment bit 12
Definition at line 1869 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA13 0x00002000U |
Filter FIFO Assignment bit 13
Definition at line 1870 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA14 0x00004000U |
Filter FIFO Assignment bit 14
Definition at line 1871 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA15 0x00008000U |
Filter FIFO Assignment bit 15
Definition at line 1872 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA16 0x00010000U |
Filter FIFO Assignment bit 16
Definition at line 1873 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA17 0x00020000U |
Filter FIFO Assignment bit 17
Definition at line 1874 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA18 0x00040000U |
Filter FIFO Assignment bit 18
Definition at line 1875 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA19 0x00080000U |
Filter FIFO Assignment bit 19
Definition at line 1876 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA2 0x00000004U |
Filter FIFO Assignment bit 2
Definition at line 1859 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA20 0x00100000U |
Filter FIFO Assignment bit 20
Definition at line 1877 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA21 0x00200000U |
Filter FIFO Assignment bit 21
Definition at line 1878 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA22 0x00400000U |
Filter FIFO Assignment bit 22
Definition at line 1879 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA23 0x00800000U |
Filter FIFO Assignment bit 23
Definition at line 1880 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA24 0x01000000U |
Filter FIFO Assignment bit 24
Definition at line 1881 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA25 0x02000000U |
Filter FIFO Assignment bit 25
Definition at line 1882 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA26 0x04000000U |
Filter FIFO Assignment bit 26
Definition at line 1883 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA27 0x08000000U |
Filter FIFO Assignment bit 27
Definition at line 1884 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA3 0x00000008U |
Filter FIFO Assignment bit 3
Definition at line 1860 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA4 0x00000010U |
Filter FIFO Assignment bit 4
Definition at line 1861 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA5 0x00000020U |
Filter FIFO Assignment bit 5
Definition at line 1862 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA6 0x00000040U |
Filter FIFO Assignment bit 6
Definition at line 1863 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA7 0x00000080U |
Filter FIFO Assignment bit 7
Definition at line 1864 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA8 0x00000100U |
Filter FIFO Assignment bit 8
Definition at line 1865 of file stm32f407xx.h.
| #define CAN_FFA1R_FFA9 0x00000200U |
Filter FIFO Assignment bit 9
Definition at line 1866 of file stm32f407xx.h.
| #define CAN_FM1R_FBM 0x0FFFFFFFU |
Filter Mode
Definition at line 1794 of file stm32f407xx.h.
| #define CAN_FM1R_FBM0 0x00000001U |
Filter Init Mode bit 0
Definition at line 1795 of file stm32f407xx.h.
| #define CAN_FM1R_FBM1 0x00000002U |
Filter Init Mode bit 1
Definition at line 1796 of file stm32f407xx.h.
| #define CAN_FM1R_FBM10 0x00000400U |
Filter Init Mode bit 10
Definition at line 1805 of file stm32f407xx.h.
| #define CAN_FM1R_FBM11 0x00000800U |
Filter Init Mode bit 11
Definition at line 1806 of file stm32f407xx.h.
| #define CAN_FM1R_FBM12 0x00001000U |
Filter Init Mode bit 12
Definition at line 1807 of file stm32f407xx.h.
| #define CAN_FM1R_FBM13 0x00002000U |
Filter Init Mode bit 13
Definition at line 1808 of file stm32f407xx.h.
| #define CAN_FM1R_FBM14 0x00004000U |
Filter Init Mode bit 14
Definition at line 1809 of file stm32f407xx.h.
| #define CAN_FM1R_FBM15 0x00008000U |
Filter Init Mode bit 15
Definition at line 1810 of file stm32f407xx.h.
| #define CAN_FM1R_FBM16 0x00010000U |
Filter Init Mode bit 16
Definition at line 1811 of file stm32f407xx.h.
| #define CAN_FM1R_FBM17 0x00020000U |
Filter Init Mode bit 17
Definition at line 1812 of file stm32f407xx.h.
| #define CAN_FM1R_FBM18 0x00040000U |
Filter Init Mode bit 18
Definition at line 1813 of file stm32f407xx.h.
| #define CAN_FM1R_FBM19 0x00080000U |
Filter Init Mode bit 19
Definition at line 1814 of file stm32f407xx.h.
| #define CAN_FM1R_FBM2 0x00000004U |
Filter Init Mode bit 2
Definition at line 1797 of file stm32f407xx.h.
| #define CAN_FM1R_FBM20 0x00100000U |
Filter Init Mode bit 20
Definition at line 1815 of file stm32f407xx.h.
| #define CAN_FM1R_FBM21 0x00200000U |
Filter Init Mode bit 21
Definition at line 1816 of file stm32f407xx.h.
| #define CAN_FM1R_FBM22 0x00400000U |
Filter Init Mode bit 22
Definition at line 1817 of file stm32f407xx.h.
| #define CAN_FM1R_FBM23 0x00800000U |
Filter Init Mode bit 23
Definition at line 1818 of file stm32f407xx.h.
| #define CAN_FM1R_FBM24 0x01000000U |
Filter Init Mode bit 24
Definition at line 1819 of file stm32f407xx.h.
| #define CAN_FM1R_FBM25 0x02000000U |
Filter Init Mode bit 25
Definition at line 1820 of file stm32f407xx.h.
| #define CAN_FM1R_FBM26 0x04000000U |
Filter Init Mode bit 26
Definition at line 1821 of file stm32f407xx.h.
| #define CAN_FM1R_FBM27 0x08000000U |
Filter Init Mode bit 27
Definition at line 1822 of file stm32f407xx.h.
| #define CAN_FM1R_FBM3 0x00000008U |
Filter Init Mode bit 3
Definition at line 1798 of file stm32f407xx.h.
| #define CAN_FM1R_FBM4 0x00000010U |
Filter Init Mode bit 4
Definition at line 1799 of file stm32f407xx.h.
| #define CAN_FM1R_FBM5 0x00000020U |
Filter Init Mode bit 5
Definition at line 1800 of file stm32f407xx.h.
| #define CAN_FM1R_FBM6 0x00000040U |
Filter Init Mode bit 6
Definition at line 1801 of file stm32f407xx.h.
| #define CAN_FM1R_FBM7 0x00000080U |
Filter Init Mode bit 7
Definition at line 1802 of file stm32f407xx.h.
| #define CAN_FM1R_FBM8 0x00000100U |
Filter Init Mode bit 8
Definition at line 1803 of file stm32f407xx.h.
| #define CAN_FM1R_FBM9 0x00000200U |
Filter Init Mode bit 9
Definition at line 1804 of file stm32f407xx.h.
| #define CAN_FMR_CAN2SB 0x00003F00U |
CAN2 start bank
Definition at line 1791 of file stm32f407xx.h.
| #define CAN_FMR_FINIT 0x01U |
Filter Init Mode
Definition at line 1790 of file stm32f407xx.h.
| #define CAN_FS1R_FSC 0x0FFFFFFFU |
Filter Scale Configuration
Definition at line 1825 of file stm32f407xx.h.
| #define CAN_FS1R_FSC0 0x00000001U |
Filter Scale Configuration bit 0
Definition at line 1826 of file stm32f407xx.h.
| #define CAN_FS1R_FSC1 0x00000002U |
Filter Scale Configuration bit 1
Definition at line 1827 of file stm32f407xx.h.
| #define CAN_FS1R_FSC10 0x00000400U |
Filter Scale Configuration bit 10
Definition at line 1836 of file stm32f407xx.h.
| #define CAN_FS1R_FSC11 0x00000800U |
Filter Scale Configuration bit 11
Definition at line 1837 of file stm32f407xx.h.
| #define CAN_FS1R_FSC12 0x00001000U |
Filter Scale Configuration bit 12
Definition at line 1838 of file stm32f407xx.h.
| #define CAN_FS1R_FSC13 0x00002000U |
Filter Scale Configuration bit 13
Definition at line 1839 of file stm32f407xx.h.
| #define CAN_FS1R_FSC14 0x00004000U |
Filter Scale Configuration bit 14
Definition at line 1840 of file stm32f407xx.h.
| #define CAN_FS1R_FSC15 0x00008000U |
Filter Scale Configuration bit 15
Definition at line 1841 of file stm32f407xx.h.
| #define CAN_FS1R_FSC16 0x00010000U |
Filter Scale Configuration bit 16
Definition at line 1842 of file stm32f407xx.h.
| #define CAN_FS1R_FSC17 0x00020000U |
Filter Scale Configuration bit 17
Definition at line 1843 of file stm32f407xx.h.
| #define CAN_FS1R_FSC18 0x00040000U |
Filter Scale Configuration bit 18
Definition at line 1844 of file stm32f407xx.h.
| #define CAN_FS1R_FSC19 0x00080000U |
Filter Scale Configuration bit 19
Definition at line 1845 of file stm32f407xx.h.
| #define CAN_FS1R_FSC2 0x00000004U |
Filter Scale Configuration bit 2
Definition at line 1828 of file stm32f407xx.h.
| #define CAN_FS1R_FSC20 0x00100000U |
Filter Scale Configuration bit 20
Definition at line 1846 of file stm32f407xx.h.
| #define CAN_FS1R_FSC21 0x00200000U |
Filter Scale Configuration bit 21
Definition at line 1847 of file stm32f407xx.h.
| #define CAN_FS1R_FSC22 0x00400000U |
Filter Scale Configuration bit 22
Definition at line 1848 of file stm32f407xx.h.
| #define CAN_FS1R_FSC23 0x00800000U |
Filter Scale Configuration bit 23
Definition at line 1849 of file stm32f407xx.h.
| #define CAN_FS1R_FSC24 0x01000000U |
Filter Scale Configuration bit 24
Definition at line 1850 of file stm32f407xx.h.
| #define CAN_FS1R_FSC25 0x02000000U |
Filter Scale Configuration bit 25
Definition at line 1851 of file stm32f407xx.h.
| #define CAN_FS1R_FSC26 0x04000000U |
Filter Scale Configuration bit 26
Definition at line 1852 of file stm32f407xx.h.
| #define CAN_FS1R_FSC27 0x08000000U |
Filter Scale Configuration bit 27
Definition at line 1853 of file stm32f407xx.h.
| #define CAN_FS1R_FSC3 0x00000008U |
Filter Scale Configuration bit 3
Definition at line 1829 of file stm32f407xx.h.
| #define CAN_FS1R_FSC4 0x00000010U |
Filter Scale Configuration bit 4
Definition at line 1830 of file stm32f407xx.h.
| #define CAN_FS1R_FSC5 0x00000020U |
Filter Scale Configuration bit 5
Definition at line 1831 of file stm32f407xx.h.
| #define CAN_FS1R_FSC6 0x00000040U |
Filter Scale Configuration bit 6
Definition at line 1832 of file stm32f407xx.h.
| #define CAN_FS1R_FSC7 0x00000080U |
Filter Scale Configuration bit 7
Definition at line 1833 of file stm32f407xx.h.
| #define CAN_FS1R_FSC8 0x00000100U |
Filter Scale Configuration bit 8
Definition at line 1834 of file stm32f407xx.h.
| #define CAN_FS1R_FSC9 0x00000200U |
Filter Scale Configuration bit 9
Definition at line 1835 of file stm32f407xx.h.
| #define CAN_IER_BOFIE 0x00000400U |
| #define CAN_IER_BOFIE 0x00000400U |
| #define CAN_IER_EPVIE 0x00000200U |
Error Passive Interrupt Enable
Error passive interrupt enable
Definition at line 1632 of file stm32f407xx.h.
| #define CAN_IER_EPVIE 0x00000200U |
Error Passive Interrupt Enable
Error passive interrupt enable
Definition at line 1632 of file stm32f407xx.h.
| #define CAN_IER_ERRIE 0x00008000U |
| #define CAN_IER_ERRIE 0x00008000U |
| #define CAN_IER_EWGIE 0x00000100U |
Error Warning Interrupt Enable
Error warning interrupt enable
Definition at line 1631 of file stm32f407xx.h.
| #define CAN_IER_EWGIE 0x00000100U |
Error Warning Interrupt Enable
Error warning interrupt enable
Definition at line 1631 of file stm32f407xx.h.
| #define CAN_IER_FFIE0 0x00000004U |
FIFO Full Interrupt Enable
Definition at line 1619 of file stm32f407xx.h.
| #define CAN_IER_FFIE1 0x00000020U |
FIFO Full Interrupt Enable
Definition at line 1622 of file stm32f407xx.h.
| #define CAN_IER_FMPIE0 0x00000002U |
FIFO Message Pending Interrupt Enable
Definition at line 1618 of file stm32f407xx.h.
| #define CAN_IER_FMPIE1 0x00000010U |
FIFO Message Pending Interrupt Enable
Definition at line 1621 of file stm32f407xx.h.
| #define CAN_IER_FOVIE0 0x00000008U |
FIFO Overrun Interrupt Enable
Definition at line 1620 of file stm32f407xx.h.
| #define CAN_IER_FOVIE1 0x00000040U |
FIFO Overrun Interrupt Enable
Definition at line 1623 of file stm32f407xx.h.
| #define CAN_IER_LECIE 0x00000800U |
Last Error Code Interrupt Enable
Last error code interrupt enable
Definition at line 1634 of file stm32f407xx.h.
| #define CAN_IER_LECIE 0x00000800U |
Last Error Code Interrupt Enable
Last error code interrupt enable
Definition at line 1634 of file stm32f407xx.h.
| #define CAN_IER_SLKIE 0x00020000U |
Sleep Interrupt Enable
Definition at line 1630 of file stm32f407xx.h.
| #define CAN_IER_TMEIE 0x00000001U |
Transmit Mailbox Empty Interrupt Enable
Definition at line 1617 of file stm32f407xx.h.
| #define CAN_IER_WKUIE 0x00010000U |
Wakeup Interrupt Enable
Definition at line 1629 of file stm32f407xx.h.
| #define CAN_MCR_ABOM 0x00000040U |
Automatic Bus-Off Management
Definition at line 1561 of file stm32f407xx.h.
| #define CAN_MCR_AWUM 0x00000020U |
Automatic Wakeup Mode
Definition at line 1560 of file stm32f407xx.h.
| #define CAN_MCR_DBF 0x00010000U |
bxCAN Debug freeze
Definition at line 1564 of file stm32f407xx.h.
| #define CAN_MCR_INRQ 0x00000001U |
<CAN control and status registers Initialization Request
Definition at line 1555 of file stm32f407xx.h.
| #define CAN_MCR_NART 0x00000010U |
No Automatic Retransmission
Definition at line 1559 of file stm32f407xx.h.
| #define CAN_MCR_RESET 0x00008000U |
bxCAN software master reset
Definition at line 1563 of file stm32f407xx.h.
| #define CAN_MCR_RFLM 0x00000008U |
Receive FIFO Locked Mode
Definition at line 1558 of file stm32f407xx.h.
| #define CAN_MCR_SLEEP 0x00000002U |
Sleep Mode Request
Definition at line 1556 of file stm32f407xx.h.
| #define CAN_MCR_TTCM 0x00000080U |
Time Triggered Communication Mode
Definition at line 1562 of file stm32f407xx.h.
| #define CAN_MCR_TXFP 0x00000004U |
Transmit FIFO Priority
Definition at line 1557 of file stm32f407xx.h.
| #define CAN_MSR_ERRI 0x0004U |
Error Interrupt
Definition at line 1568 of file stm32f407xx.h.
| #define CAN_MSR_INAK 0x0001U |
Initialization Acknowledge
Definition at line 1566 of file stm32f407xx.h.
| #define CAN_MSR_RX 0x0800U |
CAN Rx Signal
Definition at line 1574 of file stm32f407xx.h.
| #define CAN_MSR_RXM 0x0200U |
Receive Mode
Definition at line 1572 of file stm32f407xx.h.
| #define CAN_MSR_SAMP 0x0400U |
Last Sample Point
Definition at line 1573 of file stm32f407xx.h.
| #define CAN_MSR_SLAK 0x0002U |
Sleep Acknowledge
Definition at line 1567 of file stm32f407xx.h.
| #define CAN_MSR_SLAKI 0x0010U |
Sleep Acknowledge Interrupt
Definition at line 1570 of file stm32f407xx.h.
| #define CAN_MSR_TXM 0x0100U |
Transmit Mode
Definition at line 1571 of file stm32f407xx.h.
| #define CAN_MSR_WKUI 0x0008U |
Wakeup Interrupt
Definition at line 1569 of file stm32f407xx.h.
| #define CAN_RDH0R_DATA4 0x000000FFU |
Data byte 4
Definition at line 1760 of file stm32f407xx.h.
| #define CAN_RDH0R_DATA5 0x0000FF00U |
Data byte 5
Definition at line 1761 of file stm32f407xx.h.
| #define CAN_RDH0R_DATA6 0x00FF0000U |
Data byte 6
Definition at line 1762 of file stm32f407xx.h.
| #define CAN_RDH0R_DATA7 0xFF000000U |
Data byte 7
Definition at line 1763 of file stm32f407xx.h.
| #define CAN_RDH1R_DATA4 0x000000FFU |
Data byte 4
Definition at line 1783 of file stm32f407xx.h.
| #define CAN_RDH1R_DATA5 0x0000FF00U |
Data byte 5
Definition at line 1784 of file stm32f407xx.h.
| #define CAN_RDH1R_DATA6 0x00FF0000U |
Data byte 6
Definition at line 1785 of file stm32f407xx.h.
| #define CAN_RDH1R_DATA7 0xFF000000U |
Data byte 7 CAN filter registers
Definition at line 1788 of file stm32f407xx.h.
| #define CAN_RDL0R_DATA0 0x000000FFU |
Data byte 0
Definition at line 1754 of file stm32f407xx.h.
| #define CAN_RDL0R_DATA1 0x0000FF00U |
Data byte 1
Definition at line 1755 of file stm32f407xx.h.
| #define CAN_RDL0R_DATA2 0x00FF0000U |
Data byte 2
Definition at line 1756 of file stm32f407xx.h.
| #define CAN_RDL0R_DATA3 0xFF000000U |
Data byte 3
Definition at line 1757 of file stm32f407xx.h.
| #define CAN_RDL1R_DATA0 0x000000FFU |
Data byte 0
Definition at line 1777 of file stm32f407xx.h.
| #define CAN_RDL1R_DATA1 0x0000FF00U |
Data byte 1
Definition at line 1778 of file stm32f407xx.h.
| #define CAN_RDL1R_DATA2 0x00FF0000U |
Data byte 2
Definition at line 1779 of file stm32f407xx.h.
| #define CAN_RDL1R_DATA3 0xFF000000U |
Data byte 3
Definition at line 1780 of file stm32f407xx.h.
| #define CAN_RDT0R_DLC 0x0000000FU |
Data Length Code
Definition at line 1749 of file stm32f407xx.h.
| #define CAN_RDT0R_FMI 0x0000FF00U |
Filter Match Index
Definition at line 1750 of file stm32f407xx.h.
| #define CAN_RDT0R_TIME 0xFFFF0000U |
Message Time Stamp
Definition at line 1751 of file stm32f407xx.h.
| #define CAN_RDT1R_DLC 0x0000000FU |
Data Length Code
Definition at line 1772 of file stm32f407xx.h.
| #define CAN_RDT1R_FMI 0x0000FF00U |
Filter Match Index
Definition at line 1773 of file stm32f407xx.h.
| #define CAN_RDT1R_TIME 0xFFFF0000U |
Message Time Stamp
Definition at line 1774 of file stm32f407xx.h.
| #define CAN_RF0R_FMP0 0x03U |
FIFO 0 Message Pending
Definition at line 1605 of file stm32f407xx.h.
| #define CAN_RF0R_FOVR0 0x10U |
FIFO 0 Overrun
Definition at line 1607 of file stm32f407xx.h.
| #define CAN_RF0R_FULL0 0x08U |
FIFO 0 Full
Definition at line 1606 of file stm32f407xx.h.
| #define CAN_RF0R_RFOM0 0x20U |
Release FIFO 0 Output Mailbox
Definition at line 1608 of file stm32f407xx.h.
| #define CAN_RF1R_FMP1 0x03U |
FIFO 1 Message Pending
Definition at line 1611 of file stm32f407xx.h.
| #define CAN_RF1R_FOVR1 0x10U |
FIFO 1 Overrun
Definition at line 1613 of file stm32f407xx.h.
| #define CAN_RF1R_FULL1 0x08U |
FIFO 1 Full
Definition at line 1612 of file stm32f407xx.h.
| #define CAN_RF1R_RFOM1 0x20U |
Release FIFO 1 Output Mailbox
Definition at line 1614 of file stm32f407xx.h.
| #define CAN_RI0R_EXID 0x001FFFF8U |
Extended Identifier
Definition at line 1745 of file stm32f407xx.h.
| #define CAN_RI0R_IDE 0x00000004U |
Identifier Extension
Definition at line 1744 of file stm32f407xx.h.
| #define CAN_RI0R_RTR 0x00000002U |
Remote Transmission Request
Definition at line 1743 of file stm32f407xx.h.
| #define CAN_RI0R_STID 0xFFE00000U |
Standard Identifier or Extended Identifier
Definition at line 1746 of file stm32f407xx.h.
| #define CAN_RI1R_EXID 0x001FFFF8U |
Extended identifier
Definition at line 1768 of file stm32f407xx.h.
| #define CAN_RI1R_IDE 0x00000004U |
Identifier Extension
Definition at line 1767 of file stm32f407xx.h.
| #define CAN_RI1R_RTR 0x00000002U |
Remote Transmission Request
Definition at line 1766 of file stm32f407xx.h.
| #define CAN_RI1R_STID 0xFFE00000U |
Standard Identifier or Extended Identifier
Definition at line 1769 of file stm32f407xx.h.
| #define CAN_TDH0R_DATA4 0x000000FFU |
Data byte 4
Definition at line 1689 of file stm32f407xx.h.
| #define CAN_TDH0R_DATA5 0x0000FF00U |
Data byte 5
Definition at line 1690 of file stm32f407xx.h.
| #define CAN_TDH0R_DATA6 0x00FF0000U |
Data byte 6
Definition at line 1691 of file stm32f407xx.h.
| #define CAN_TDH0R_DATA7 0xFF000000U |
Data byte 7
Definition at line 1692 of file stm32f407xx.h.
| #define CAN_TDH1R_DATA4 0x000000FFU |
Data byte 4
Definition at line 1713 of file stm32f407xx.h.
| #define CAN_TDH1R_DATA5 0x0000FF00U |
Data byte 5
Definition at line 1714 of file stm32f407xx.h.
| #define CAN_TDH1R_DATA6 0x00FF0000U |
Data byte 6
Definition at line 1715 of file stm32f407xx.h.
| #define CAN_TDH1R_DATA7 0xFF000000U |
Data byte 7
Definition at line 1716 of file stm32f407xx.h.
| #define CAN_TDH2R_DATA4 0x000000FFU |
Data byte 4
Definition at line 1737 of file stm32f407xx.h.
| #define CAN_TDH2R_DATA5 0x0000FF00U |
Data byte 5
Definition at line 1738 of file stm32f407xx.h.
| #define CAN_TDH2R_DATA6 0x00FF0000U |
Data byte 6
Definition at line 1739 of file stm32f407xx.h.
| #define CAN_TDH2R_DATA7 0xFF000000U |
Data byte 7
Definition at line 1740 of file stm32f407xx.h.
| #define CAN_TDL0R_DATA0 0x000000FFU |
Data byte 0
Definition at line 1683 of file stm32f407xx.h.
| #define CAN_TDL0R_DATA1 0x0000FF00U |
Data byte 1
Definition at line 1684 of file stm32f407xx.h.
| #define CAN_TDL0R_DATA2 0x00FF0000U |
Data byte 2
Definition at line 1685 of file stm32f407xx.h.
| #define CAN_TDL0R_DATA3 0xFF000000U |
Data byte 3
Definition at line 1686 of file stm32f407xx.h.
| #define CAN_TDL1R_DATA0 0x000000FFU |
Data byte 0
Definition at line 1707 of file stm32f407xx.h.
| #define CAN_TDL1R_DATA1 0x0000FF00U |
Data byte 1
Definition at line 1708 of file stm32f407xx.h.
| #define CAN_TDL1R_DATA2 0x00FF0000U |
Data byte 2
Definition at line 1709 of file stm32f407xx.h.
| #define CAN_TDL1R_DATA3 0xFF000000U |
Data byte 3
Definition at line 1710 of file stm32f407xx.h.
| #define CAN_TDL2R_DATA0 0x000000FFU |
Data byte 0
Definition at line 1731 of file stm32f407xx.h.
| #define CAN_TDL2R_DATA1 0x0000FF00U |
Data byte 1
Definition at line 1732 of file stm32f407xx.h.
| #define CAN_TDL2R_DATA2 0x00FF0000U |
Data byte 2
Definition at line 1733 of file stm32f407xx.h.
| #define CAN_TDL2R_DATA3 0xFF000000U |
Data byte 3
Definition at line 1734 of file stm32f407xx.h.
| #define CAN_TDT0R_DLC 0x0000000FU |
Data Length Code
Definition at line 1678 of file stm32f407xx.h.
| #define CAN_TDT0R_TGT 0x00000100U |
Transmit Global Time
Definition at line 1679 of file stm32f407xx.h.
| #define CAN_TDT0R_TIME 0xFFFF0000U |
Message Time Stamp
Definition at line 1680 of file stm32f407xx.h.
| #define CAN_TDT1R_DLC 0x0000000FU |
Data Length Code
Definition at line 1702 of file stm32f407xx.h.
| #define CAN_TDT1R_TGT 0x00000100U |
Transmit Global Time
Definition at line 1703 of file stm32f407xx.h.
| #define CAN_TDT1R_TIME 0xFFFF0000U |
Message Time Stamp
Definition at line 1704 of file stm32f407xx.h.
| #define CAN_TDT2R_DLC 0x0000000FU |
Data Length Code
Definition at line 1726 of file stm32f407xx.h.
| #define CAN_TDT2R_TGT 0x00000100U |
Transmit Global Time
Definition at line 1727 of file stm32f407xx.h.
| #define CAN_TDT2R_TIME 0xFFFF0000U |
Message Time Stamp
Definition at line 1728 of file stm32f407xx.h.
| #define CAN_TI0R_EXID 0x001FFFF8U |
Extended Identifier
Definition at line 1674 of file stm32f407xx.h.
| #define CAN_TI0R_IDE 0x00000004U |
Identifier Extension
Definition at line 1673 of file stm32f407xx.h.
| #define CAN_TI0R_RTR 0x00000002U |
Remote Transmission Request
Definition at line 1672 of file stm32f407xx.h.
| #define CAN_TI0R_STID 0xFFE00000U |
Standard Identifier or Extended Identifier
Definition at line 1675 of file stm32f407xx.h.
| #define CAN_TI0R_TXRQ 0x00000001U |
Transmit Mailbox Request
Definition at line 1671 of file stm32f407xx.h.
| #define CAN_TI1R_EXID 0x001FFFF8U |
Extended Identifier
Definition at line 1698 of file stm32f407xx.h.
| #define CAN_TI1R_IDE 0x00000004U |
Identifier Extension
Definition at line 1697 of file stm32f407xx.h.
| #define CAN_TI1R_RTR 0x00000002U |
Remote Transmission Request
Definition at line 1696 of file stm32f407xx.h.
| #define CAN_TI1R_STID 0xFFE00000U |
Standard Identifier or Extended Identifier
Definition at line 1699 of file stm32f407xx.h.
| #define CAN_TI1R_TXRQ 0x00000001U |
Transmit Mailbox Request
Definition at line 1695 of file stm32f407xx.h.
| #define CAN_TI2R_EXID 0x001FFFF8U |
Extended identifier
Definition at line 1722 of file stm32f407xx.h.
| #define CAN_TI2R_IDE 0x00000004U |
Identifier Extension
Definition at line 1721 of file stm32f407xx.h.
| #define CAN_TI2R_RTR 0x00000002U |
Remote Transmission Request
Definition at line 1720 of file stm32f407xx.h.
| #define CAN_TI2R_STID 0xFFE00000U |
Standard Identifier or Extended Identifier
Definition at line 1723 of file stm32f407xx.h.
| #define CAN_TI2R_TXRQ 0x00000001U |
Transmit Mailbox Request
Definition at line 1719 of file stm32f407xx.h.
| #define CAN_TSR_ABRQ0 0x00000080U |
Abort Request for Mailbox0
Definition at line 1581 of file stm32f407xx.h.
| #define CAN_TSR_ABRQ1 0x00008000U |
Abort Request for Mailbox 1
Definition at line 1586 of file stm32f407xx.h.
| #define CAN_TSR_ABRQ2 0x00800000U |
Abort Request for Mailbox 2
Definition at line 1591 of file stm32f407xx.h.
| #define CAN_TSR_ALST0 0x00000004U |
Arbitration Lost for Mailbox0
Definition at line 1579 of file stm32f407xx.h.
| #define CAN_TSR_ALST1 0x00000400U |
Arbitration Lost for Mailbox1
Definition at line 1584 of file stm32f407xx.h.
| #define CAN_TSR_ALST2 0x00040000U |
Arbitration Lost for mailbox 2
Definition at line 1589 of file stm32f407xx.h.
| #define CAN_TSR_CODE 0x03000000U |
Mailbox Code
Definition at line 1592 of file stm32f407xx.h.
| #define CAN_TSR_LOW 0xE0000000U |
LOW[2:0] bits
Definition at line 1599 of file stm32f407xx.h.
| #define CAN_TSR_LOW0 0x20000000U |
Lowest Priority Flag for Mailbox 0
Definition at line 1600 of file stm32f407xx.h.
| #define CAN_TSR_LOW1 0x40000000U |
Lowest Priority Flag for Mailbox 1
Definition at line 1601 of file stm32f407xx.h.
| #define CAN_TSR_LOW2 0x80000000U |
Lowest Priority Flag for Mailbox 2
Definition at line 1602 of file stm32f407xx.h.
| #define CAN_TSR_RQCP0 0x00000001U |
Request Completed Mailbox0
Definition at line 1577 of file stm32f407xx.h.
| #define CAN_TSR_RQCP1 0x00000100U |
Request Completed Mailbox1
Definition at line 1582 of file stm32f407xx.h.
| #define CAN_TSR_RQCP2 0x00010000U |
Request Completed Mailbox2
Definition at line 1587 of file stm32f407xx.h.
| #define CAN_TSR_TERR0 0x00000008U |
Transmission Error of Mailbox0
Definition at line 1580 of file stm32f407xx.h.
| #define CAN_TSR_TERR1 0x00000800U |
Transmission Error of Mailbox1
Definition at line 1585 of file stm32f407xx.h.
| #define CAN_TSR_TERR2 0x00080000U |
Transmission Error of Mailbox 2
Definition at line 1590 of file stm32f407xx.h.
| #define CAN_TSR_TME 0x1C000000U |
TME[2:0] bits
Definition at line 1594 of file stm32f407xx.h.
| #define CAN_TSR_TME0 0x04000000U |
Transmit Mailbox 0 Empty
Definition at line 1595 of file stm32f407xx.h.
| #define CAN_TSR_TME1 0x08000000U |
Transmit Mailbox 1 Empty
Definition at line 1596 of file stm32f407xx.h.
| #define CAN_TSR_TME2 0x10000000U |
Transmit Mailbox 2 Empty
Definition at line 1597 of file stm32f407xx.h.
| #define CAN_TSR_TXOK0 0x00000002U |
Transmission OK of Mailbox0
Definition at line 1578 of file stm32f407xx.h.
| #define CAN_TSR_TXOK1 0x00000200U |
Transmission OK of Mailbox1
Definition at line 1583 of file stm32f407xx.h.
| #define CAN_TSR_TXOK2 0x00020000U |
Transmission OK of Mailbox 2
Definition at line 1588 of file stm32f407xx.h.
| #define CRC_CR_RESET 0x01U |
RESET bit
Definition at line 2883 of file stm32f407xx.h.
| #define CRC_DR_DR 0xFFFFFFFFU |
Data register bits
Definition at line 2875 of file stm32f407xx.h.
| #define CRC_IDR_IDR 0xFFU |
General-purpose 8-bit data register bits
Definition at line 2879 of file stm32f407xx.h.
| #define DAC_CR_BOFF1 0x00000002U |
DAC channel1 output buffer disable
Definition at line 2893 of file stm32f407xx.h.
| #define DAC_CR_BOFF2 0x00020000U |
DAC channel2 output buffer disable
Definition at line 2914 of file stm32f407xx.h.
| #define DAC_CR_DMAEN1 0x00001000U |
DAC channel1 DMA enable
Definition at line 2911 of file stm32f407xx.h.
| #define DAC_CR_DMAEN2 0x10000000U |
DAC channel2 DMA enabled
Definition at line 2932 of file stm32f407xx.h.
| #define DAC_CR_DMAUDRIE1 0x00002000U |
DAC channel1 DMA underrun interrupt enable
Definition at line 2912 of file stm32f407xx.h.
| #define DAC_CR_DMAUDRIE2 0x20000000U |
DAC channel2 DMA underrun interrupt enable
Definition at line 2933 of file stm32f407xx.h.
| #define DAC_CR_EN1 0x00000001U |
DAC channel1 enable
Definition at line 2892 of file stm32f407xx.h.
| #define DAC_CR_EN2 0x00010000U |
DAC channel2 enable
Definition at line 2913 of file stm32f407xx.h.
| #define DAC_CR_MAMP1 0x00000F00U |
MAMP13:0
Definition at line 2905 of file stm32f407xx.h.
| #define DAC_CR_MAMP1_0 0x00000100U |
Bit 0
Definition at line 2906 of file stm32f407xx.h.
| #define DAC_CR_MAMP1_1 0x00000200U |
Bit 1
Definition at line 2907 of file stm32f407xx.h.
| #define DAC_CR_MAMP1_2 0x00000400U |
Bit 2
Definition at line 2908 of file stm32f407xx.h.
| #define DAC_CR_MAMP1_3 0x00000800U |
Bit 3
Definition at line 2909 of file stm32f407xx.h.
| #define DAC_CR_MAMP2 0x0F000000U |
MAMP23:0
Definition at line 2926 of file stm32f407xx.h.
| #define DAC_CR_MAMP2_0 0x01000000U |
Bit 0
Definition at line 2927 of file stm32f407xx.h.
| #define DAC_CR_MAMP2_1 0x02000000U |
Bit 1
Definition at line 2928 of file stm32f407xx.h.
| #define DAC_CR_MAMP2_2 0x04000000U |
Bit 2
Definition at line 2929 of file stm32f407xx.h.
| #define DAC_CR_MAMP2_3 0x08000000U |
Bit 3
Definition at line 2930 of file stm32f407xx.h.
| #define DAC_CR_TEN1 0x00000004U |
DAC channel1 Trigger enable
Definition at line 2894 of file stm32f407xx.h.
| #define DAC_CR_TEN2 0x00040000U |
DAC channel2 Trigger enable
Definition at line 2915 of file stm32f407xx.h.
| #define DAC_CR_TSEL1 0x00000038U |
TSEL1[2:0] (DAC channel1 Trigger selection)
Definition at line 2896 of file stm32f407xx.h.
| #define DAC_CR_TSEL1_0 0x00000008U |
Bit 0
Definition at line 2897 of file stm32f407xx.h.
| #define DAC_CR_TSEL1_1 0x00000010U |
Bit 1
Definition at line 2898 of file stm32f407xx.h.
| #define DAC_CR_TSEL1_2 0x00000020U |
Bit 2
Definition at line 2899 of file stm32f407xx.h.
| #define DAC_CR_TSEL2 0x00380000U |
TSEL2[2:0] (DAC channel2 Trigger selection)
Definition at line 2917 of file stm32f407xx.h.
| #define DAC_CR_TSEL2_0 0x00080000U |
Bit 0
Definition at line 2918 of file stm32f407xx.h.
| #define DAC_CR_TSEL2_1 0x00100000U |
Bit 1
Definition at line 2919 of file stm32f407xx.h.
| #define DAC_CR_TSEL2_2 0x00200000U |
Bit 2
Definition at line 2920 of file stm32f407xx.h.
| #define DAC_CR_WAVE1 0x000000C0U |
WAVE11:0
Definition at line 2901 of file stm32f407xx.h.
| #define DAC_CR_WAVE1_0 0x00000040U |
Bit 0
Definition at line 2902 of file stm32f407xx.h.
| #define DAC_CR_WAVE1_1 0x00000080U |
Bit 1
Definition at line 2903 of file stm32f407xx.h.
| #define DAC_CR_WAVE2 0x00C00000U |
WAVE21:0
Definition at line 2922 of file stm32f407xx.h.
| #define DAC_CR_WAVE2_0 0x00400000U |
Bit 0
Definition at line 2923 of file stm32f407xx.h.
| #define DAC_CR_WAVE2_1 0x00800000U |
Bit 1
Definition at line 2924 of file stm32f407xx.h.
| #define DAC_DHR12L1_DACC1DHR 0xFFF0U |
DAC channel1 12-bit Left aligned data
Definition at line 2943 of file stm32f407xx.h.
| #define DAC_DHR12L2_DACC2DHR 0xFFF0U |
DAC channel2 12-bit Left aligned data
Definition at line 2952 of file stm32f407xx.h.
| #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U |
DAC channel1 12-bit Left aligned data
Definition at line 2962 of file stm32f407xx.h.
| #define DAC_DHR12LD_DACC2DHR 0xFFF00000U |
DAC channel2 12-bit Left aligned data
Definition at line 2963 of file stm32f407xx.h.
| #define DAC_DHR12R1_DACC1DHR 0x0FFFU |
DAC channel1 12-bit Right aligned data
Definition at line 2940 of file stm32f407xx.h.
| #define DAC_DHR12R2_DACC2DHR 0x0FFFU |
DAC channel2 12-bit Right aligned data
Definition at line 2949 of file stm32f407xx.h.
| #define DAC_DHR12RD_DACC1DHR 0x00000FFFU |
DAC channel1 12-bit Right aligned data
Definition at line 2958 of file stm32f407xx.h.
| #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U |
DAC channel2 12-bit Right aligned data
Definition at line 2959 of file stm32f407xx.h.
| #define DAC_DHR8R1_DACC1DHR 0xFFU |
DAC channel1 8-bit Right aligned data
Definition at line 2946 of file stm32f407xx.h.
| #define DAC_DHR8R2_DACC2DHR 0xFFU |
DAC channel2 8-bit Right aligned data
Definition at line 2955 of file stm32f407xx.h.
| #define DAC_DHR8RD_DACC1DHR 0x00FFU |
DAC channel1 8-bit Right aligned data
Definition at line 2966 of file stm32f407xx.h.
| #define DAC_DHR8RD_DACC2DHR 0xFF00U |
DAC channel2 8-bit Right aligned data
Definition at line 2967 of file stm32f407xx.h.
| #define DAC_DOR1_DACC1DOR 0x0FFFU |
DAC channel1 data output
Definition at line 2970 of file stm32f407xx.h.
| #define DAC_DOR2_DACC2DOR 0x0FFFU |
DAC channel2 data output
Definition at line 2973 of file stm32f407xx.h.
| #define DAC_SR_DMAUDR1 0x00002000U |
DAC channel1 DMA underrun flag
Definition at line 2976 of file stm32f407xx.h.
| #define DAC_SR_DMAUDR2 0x20000000U |
DAC channel2 DMA underrun flag
Definition at line 2977 of file stm32f407xx.h.
| #define DAC_SWTRIGR_SWTRIG1 0x01U |
DAC channel1 software trigger
Definition at line 2936 of file stm32f407xx.h.
| #define DAC_SWTRIGR_SWTRIG2 0x02U |
DAC channel2 software trigger
Definition at line 2937 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U |
Definition at line 6640 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U |
Definition at line 6641 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U |
Definition at line 6637 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U |
Definition at line 6638 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U |
Definition at line 6639 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP |
Definition at line 6643 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U |
Definition at line 6636 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U |
Definition at line 6634 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U |
Definition at line 6631 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U |
Definition at line 6632 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U |
Definition at line 6633 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U |
Definition at line 6625 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U |
Definition at line 6626 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U |
Definition at line 6627 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U |
Definition at line 6628 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U |
Definition at line 6629 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U |
Definition at line 6630 of file stm32f407xx.h.
| #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U |
Definition at line 6635 of file stm32f407xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U |
Definition at line 6649 of file stm32f407xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U |
Definition at line 6650 of file stm32f407xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U |
Definition at line 6646 of file stm32f407xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U |
Definition at line 6647 of file stm32f407xx.h.
| #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U |
Definition at line 6648 of file stm32f407xx.h.
| #define DBGMCU_CR_DBG_SLEEP 0x00000001U |
Definition at line 6615 of file stm32f407xx.h.
| #define DBGMCU_CR_DBG_STANDBY 0x00000004U |
Definition at line 6617 of file stm32f407xx.h.
| #define DBGMCU_CR_DBG_STOP 0x00000002U |
Definition at line 6616 of file stm32f407xx.h.
| #define DBGMCU_CR_TRACE_IOEN 0x00000020U |
Definition at line 6618 of file stm32f407xx.h.
| #define DBGMCU_CR_TRACE_MODE 0x000000C0U |
Definition at line 6620 of file stm32f407xx.h.
| #define DBGMCU_CR_TRACE_MODE_0 0x00000040U |
Bit 0
Definition at line 6621 of file stm32f407xx.h.
| #define DBGMCU_CR_TRACE_MODE_1 0x00000080U |
Bit 1
Definition at line 6622 of file stm32f407xx.h.
| #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU |
Definition at line 6611 of file stm32f407xx.h.
| #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U |
Definition at line 6612 of file stm32f407xx.h.
| #define DCMI_CR_CAPTURE 0x00000001U |
Definition at line 2991 of file stm32f407xx.h.
| #define DCMI_CR_CM 0x00000002U |
Definition at line 2992 of file stm32f407xx.h.
| #define DCMI_CR_CRE 0x00001000U |
Definition at line 3003 of file stm32f407xx.h.
| #define DCMI_CR_CROP 0x00000004U |
Definition at line 2993 of file stm32f407xx.h.
| #define DCMI_CR_EDM_0 0x00000400U |
Definition at line 3001 of file stm32f407xx.h.
| #define DCMI_CR_EDM_1 0x00000800U |
Definition at line 3002 of file stm32f407xx.h.
| #define DCMI_CR_ENABLE 0x00004000U |
Definition at line 3004 of file stm32f407xx.h.
| #define DCMI_CR_ESS 0x00000010U |
Definition at line 2995 of file stm32f407xx.h.
| #define DCMI_CR_FCRC_0 0x00000100U |
Definition at line 2999 of file stm32f407xx.h.
| #define DCMI_CR_FCRC_1 0x00000200U |
Definition at line 3000 of file stm32f407xx.h.
| #define DCMI_CR_HSPOL 0x00000040U |
Definition at line 2997 of file stm32f407xx.h.
| #define DCMI_CR_JPEG 0x00000008U |
Definition at line 2994 of file stm32f407xx.h.
| #define DCMI_CR_PCKPOL 0x00000020U |
Definition at line 2996 of file stm32f407xx.h.
| #define DCMI_CR_VSPOL 0x00000080U |
Definition at line 2998 of file stm32f407xx.h.
| #define DCMI_CWSIZE_CAPCNT 0x00003FFFU |
Definition at line 3075 of file stm32f407xx.h.
| #define DCMI_CWSIZE_VLINE 0x3FFF0000U |
Definition at line 3076 of file stm32f407xx.h.
| #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU |
Definition at line 3071 of file stm32f407xx.h.
| #define DCMI_CWSTRT_VST 0x1FFF0000U |
Definition at line 3072 of file stm32f407xx.h.
| #define DCMI_DR_BYTE0 0x000000FFU |
Definition at line 3079 of file stm32f407xx.h.
| #define DCMI_DR_BYTE1 0x0000FF00U |
Definition at line 3080 of file stm32f407xx.h.
| #define DCMI_DR_BYTE2 0x00FF0000U |
Definition at line 3081 of file stm32f407xx.h.
| #define DCMI_DR_BYTE3 0xFF000000U |
Definition at line 3082 of file stm32f407xx.h.
| #define DCMI_ESCR_FEC 0xFF000000U |
Definition at line 3062 of file stm32f407xx.h.
| #define DCMI_ESCR_FSC 0x000000FFU |
Definition at line 3059 of file stm32f407xx.h.
| #define DCMI_ESCR_LEC 0x00FF0000U |
Definition at line 3061 of file stm32f407xx.h.
| #define DCMI_ESCR_LSC 0x0000FF00U |
Definition at line 3060 of file stm32f407xx.h.
| #define DCMI_ESUR_FEU 0xFF000000U |
Definition at line 3068 of file stm32f407xx.h.
| #define DCMI_ESUR_FSU 0x000000FFU |
Definition at line 3065 of file stm32f407xx.h.
| #define DCMI_ESUR_LEU 0x00FF0000U |
Definition at line 3067 of file stm32f407xx.h.
| #define DCMI_ESUR_LSU 0x0000FF00U |
Definition at line 3066 of file stm32f407xx.h.
| #define DCMI_ICR_ERR_ISC 0x00000004U |
Definition at line 3051 of file stm32f407xx.h.
| #define DCMI_ICR_FRAME_ISC 0x00000001U |
Definition at line 3049 of file stm32f407xx.h.
| #define DCMI_ICR_LINE_ISC 0x00000010U |
Definition at line 3053 of file stm32f407xx.h.
| #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC |
Definition at line 3056 of file stm32f407xx.h.
| #define DCMI_ICR_OVR_ISC 0x00000002U |
Definition at line 3050 of file stm32f407xx.h.
| #define DCMI_ICR_VSYNC_ISC 0x00000008U |
Definition at line 3052 of file stm32f407xx.h.
| #define DCMI_IER_ERR_IE 0x00000004U |
Definition at line 3028 of file stm32f407xx.h.
| #define DCMI_IER_FRAME_IE 0x00000001U |
Definition at line 3026 of file stm32f407xx.h.
| #define DCMI_IER_LINE_IE 0x00000010U |
Definition at line 3030 of file stm32f407xx.h.
| #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE |
Definition at line 3032 of file stm32f407xx.h.
| #define DCMI_IER_OVR_IE 0x00000002U |
Definition at line 3027 of file stm32f407xx.h.
| #define DCMI_IER_VSYNC_IE 0x00000008U |
Definition at line 3029 of file stm32f407xx.h.
| #define DCMI_MIS_ERR_MIS 0x00000004U |
Definition at line 3037 of file stm32f407xx.h.
| #define DCMI_MIS_FRAME_MIS 0x00000001U |
Definition at line 3035 of file stm32f407xx.h.
| #define DCMI_MIS_LINE_MIS 0x00000010U |
Definition at line 3039 of file stm32f407xx.h.
| #define DCMI_MIS_OVR_MIS 0x00000002U |
Definition at line 3036 of file stm32f407xx.h.
| #define DCMI_MIS_VSYNC_MIS 0x00000008U |
Definition at line 3038 of file stm32f407xx.h.
| #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS |
Definition at line 3044 of file stm32f407xx.h.
| #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS |
Definition at line 3042 of file stm32f407xx.h.
| #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS |
Definition at line 3046 of file stm32f407xx.h.
| #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS |
Definition at line 3043 of file stm32f407xx.h.
| #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS |
Definition at line 3045 of file stm32f407xx.h.
| #define DCMI_RIS_ERR_RIS 0x00000004U |
Definition at line 3014 of file stm32f407xx.h.
| #define DCMI_RIS_FRAME_RIS 0x00000001U |
Definition at line 3012 of file stm32f407xx.h.
| #define DCMI_RIS_LINE_RIS 0x00000010U |
Definition at line 3016 of file stm32f407xx.h.
| #define DCMI_RIS_OVR_RIS 0x00000002U |
Definition at line 3013 of file stm32f407xx.h.
| #define DCMI_RIS_VSYNC_RIS 0x00000008U |
Definition at line 3015 of file stm32f407xx.h.
| #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS |
Definition at line 3020 of file stm32f407xx.h.
| #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS |
Definition at line 3018 of file stm32f407xx.h.
| #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS |
Definition at line 3022 of file stm32f407xx.h.
| #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS |
Definition at line 3023 of file stm32f407xx.h.
| #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS |
Definition at line 3019 of file stm32f407xx.h.
| #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS |
Definition at line 3021 of file stm32f407xx.h.
| #define DCMI_SR_FNE 0x00000004U |
Definition at line 3009 of file stm32f407xx.h.
| #define DCMI_SR_HSYNC 0x00000001U |
Definition at line 3007 of file stm32f407xx.h.
| #define DCMI_SR_VSYNC 0x00000002U |
Definition at line 3008 of file stm32f407xx.h.
| #define DMA_HIFCR_CDMEIF4 0x00000004U |
Definition at line 3243 of file stm32f407xx.h.
| #define DMA_HIFCR_CDMEIF5 0x00000100U |
Definition at line 3238 of file stm32f407xx.h.
| #define DMA_HIFCR_CDMEIF6 0x00040000U |
Definition at line 3233 of file stm32f407xx.h.
| #define DMA_HIFCR_CDMEIF7 0x01000000U |
Definition at line 3228 of file stm32f407xx.h.
| #define DMA_HIFCR_CFEIF4 0x00000001U |
Definition at line 3244 of file stm32f407xx.h.
| #define DMA_HIFCR_CFEIF5 0x00000040U |
Definition at line 3239 of file stm32f407xx.h.
| #define DMA_HIFCR_CFEIF6 0x00010000U |
Definition at line 3234 of file stm32f407xx.h.
| #define DMA_HIFCR_CFEIF7 0x00400000U |
Definition at line 3229 of file stm32f407xx.h.
| #define DMA_HIFCR_CHTIF4 0x00000010U |
Definition at line 3241 of file stm32f407xx.h.
| #define DMA_HIFCR_CHTIF5 0x00000400U |
Definition at line 3236 of file stm32f407xx.h.
| #define DMA_HIFCR_CHTIF6 0x00100000U |
Definition at line 3231 of file stm32f407xx.h.
| #define DMA_HIFCR_CHTIF7 0x04000000U |
Definition at line 3226 of file stm32f407xx.h.
| #define DMA_HIFCR_CTCIF4 0x00000020U |
Definition at line 3240 of file stm32f407xx.h.
| #define DMA_HIFCR_CTCIF5 0x00000800U |
Definition at line 3235 of file stm32f407xx.h.
| #define DMA_HIFCR_CTCIF6 0x00200000U |
Definition at line 3230 of file stm32f407xx.h.
| #define DMA_HIFCR_CTCIF7 0x08000000U |
Definition at line 3225 of file stm32f407xx.h.
| #define DMA_HIFCR_CTEIF4 0x00000008U |
Definition at line 3242 of file stm32f407xx.h.
| #define DMA_HIFCR_CTEIF5 0x00000200U |
Definition at line 3237 of file stm32f407xx.h.
| #define DMA_HIFCR_CTEIF6 0x00080000U |
Definition at line 3232 of file stm32f407xx.h.
| #define DMA_HIFCR_CTEIF7 0x02000000U |
Definition at line 3227 of file stm32f407xx.h.
| #define DMA_HISR_DMEIF4 0x00000004U |
Definition at line 3199 of file stm32f407xx.h.
| #define DMA_HISR_DMEIF5 0x00000100U |
Definition at line 3194 of file stm32f407xx.h.
| #define DMA_HISR_DMEIF6 0x00040000U |
Definition at line 3189 of file stm32f407xx.h.
| #define DMA_HISR_DMEIF7 0x01000000U |
Definition at line 3184 of file stm32f407xx.h.
| #define DMA_HISR_FEIF4 0x00000001U |
Definition at line 3200 of file stm32f407xx.h.
| #define DMA_HISR_FEIF5 0x00000040U |
Definition at line 3195 of file stm32f407xx.h.
| #define DMA_HISR_FEIF6 0x00010000U |
Definition at line 3190 of file stm32f407xx.h.
| #define DMA_HISR_FEIF7 0x00400000U |
Definition at line 3185 of file stm32f407xx.h.
| #define DMA_HISR_HTIF4 0x00000010U |
Definition at line 3197 of file stm32f407xx.h.
| #define DMA_HISR_HTIF5 0x00000400U |
Definition at line 3192 of file stm32f407xx.h.
| #define DMA_HISR_HTIF6 0x00100000U |
Definition at line 3187 of file stm32f407xx.h.
| #define DMA_HISR_HTIF7 0x04000000U |
Definition at line 3182 of file stm32f407xx.h.
| #define DMA_HISR_TCIF4 0x00000020U |
Definition at line 3196 of file stm32f407xx.h.
| #define DMA_HISR_TCIF5 0x00000800U |
Definition at line 3191 of file stm32f407xx.h.
| #define DMA_HISR_TCIF6 0x00200000U |
Definition at line 3186 of file stm32f407xx.h.
| #define DMA_HISR_TCIF7 0x08000000U |
Definition at line 3181 of file stm32f407xx.h.
| #define DMA_HISR_TEIF4 0x00000008U |
Definition at line 3198 of file stm32f407xx.h.
| #define DMA_HISR_TEIF5 0x00000200U |
Definition at line 3193 of file stm32f407xx.h.
| #define DMA_HISR_TEIF6 0x00080000U |
Definition at line 3188 of file stm32f407xx.h.
| #define DMA_HISR_TEIF7 0x02000000U |
Definition at line 3183 of file stm32f407xx.h.
| #define DMA_LIFCR_CDMEIF0 0x00000004U |
Definition at line 3221 of file stm32f407xx.h.
| #define DMA_LIFCR_CDMEIF1 0x00000100U |
Definition at line 3216 of file stm32f407xx.h.
| #define DMA_LIFCR_CDMEIF2 0x00040000U |
Definition at line 3211 of file stm32f407xx.h.
| #define DMA_LIFCR_CDMEIF3 0x01000000U |
Definition at line 3206 of file stm32f407xx.h.
| #define DMA_LIFCR_CFEIF0 0x00000001U |
Definition at line 3222 of file stm32f407xx.h.
| #define DMA_LIFCR_CFEIF1 0x00000040U |
Definition at line 3217 of file stm32f407xx.h.
| #define DMA_LIFCR_CFEIF2 0x00010000U |
Definition at line 3212 of file stm32f407xx.h.
| #define DMA_LIFCR_CFEIF3 0x00400000U |
Definition at line 3207 of file stm32f407xx.h.
| #define DMA_LIFCR_CHTIF0 0x00000010U |
Definition at line 3219 of file stm32f407xx.h.
| #define DMA_LIFCR_CHTIF1 0x00000400U |
Definition at line 3214 of file stm32f407xx.h.
| #define DMA_LIFCR_CHTIF2 0x00100000U |
Definition at line 3209 of file stm32f407xx.h.
| #define DMA_LIFCR_CHTIF3 0x04000000U |
Definition at line 3204 of file stm32f407xx.h.
| #define DMA_LIFCR_CTCIF0 0x00000020U |
Definition at line 3218 of file stm32f407xx.h.
| #define DMA_LIFCR_CTCIF1 0x00000800U |
Definition at line 3213 of file stm32f407xx.h.
| #define DMA_LIFCR_CTCIF2 0x00200000U |
Definition at line 3208 of file stm32f407xx.h.
| #define DMA_LIFCR_CTCIF3 0x08000000U |
Definition at line 3203 of file stm32f407xx.h.
| #define DMA_LIFCR_CTEIF0 0x00000008U |
Definition at line 3220 of file stm32f407xx.h.
| #define DMA_LIFCR_CTEIF1 0x00000200U |
Definition at line 3215 of file stm32f407xx.h.
| #define DMA_LIFCR_CTEIF2 0x00080000U |
Definition at line 3210 of file stm32f407xx.h.
| #define DMA_LIFCR_CTEIF3 0x02000000U |
Definition at line 3205 of file stm32f407xx.h.
| #define DMA_LISR_DMEIF0 0x00000004U |
Definition at line 3177 of file stm32f407xx.h.
| #define DMA_LISR_DMEIF1 0x00000100U |
Definition at line 3172 of file stm32f407xx.h.
| #define DMA_LISR_DMEIF2 0x00040000U |
Definition at line 3167 of file stm32f407xx.h.
| #define DMA_LISR_DMEIF3 0x01000000U |
Definition at line 3162 of file stm32f407xx.h.
| #define DMA_LISR_FEIF0 0x00000001U |
Definition at line 3178 of file stm32f407xx.h.
| #define DMA_LISR_FEIF1 0x00000040U |
Definition at line 3173 of file stm32f407xx.h.
| #define DMA_LISR_FEIF2 0x00010000U |
Definition at line 3168 of file stm32f407xx.h.
| #define DMA_LISR_FEIF3 0x00400000U |
Definition at line 3163 of file stm32f407xx.h.
| #define DMA_LISR_HTIF0 0x00000010U |
Definition at line 3175 of file stm32f407xx.h.
| #define DMA_LISR_HTIF1 0x00000400U |
Definition at line 3170 of file stm32f407xx.h.
| #define DMA_LISR_HTIF2 0x00100000U |
Definition at line 3165 of file stm32f407xx.h.
| #define DMA_LISR_HTIF3 0x04000000U |
Definition at line 3160 of file stm32f407xx.h.
| #define DMA_LISR_TCIF0 0x00000020U |
Definition at line 3174 of file stm32f407xx.h.
| #define DMA_LISR_TCIF1 0x00000800U |
Definition at line 3169 of file stm32f407xx.h.
| #define DMA_LISR_TCIF2 0x00200000U |
Definition at line 3164 of file stm32f407xx.h.
| #define DMA_LISR_TCIF3 0x08000000U |
Definition at line 3159 of file stm32f407xx.h.
| #define DMA_LISR_TEIF0 0x00000008U |
Definition at line 3176 of file stm32f407xx.h.
| #define DMA_LISR_TEIF1 0x00000200U |
Definition at line 3171 of file stm32f407xx.h.
| #define DMA_LISR_TEIF2 0x00080000U |
Definition at line 3166 of file stm32f407xx.h.
| #define DMA_LISR_TEIF3 0x02000000U |
Definition at line 3161 of file stm32f407xx.h.
| #define DMA_SxCR_ACK 0x00100000U |
Definition at line 3126 of file stm32f407xx.h.
| #define DMA_SxCR_CHSEL 0x0E000000U |
Definition at line 3090 of file stm32f407xx.h.
| #define DMA_SxCR_CHSEL_0 0x02000000U |
Definition at line 3091 of file stm32f407xx.h.
| #define DMA_SxCR_CHSEL_1 0x04000000U |
Definition at line 3092 of file stm32f407xx.h.
| #define DMA_SxCR_CHSEL_2 0x08000000U |
Definition at line 3093 of file stm32f407xx.h.
| #define DMA_SxCR_CIRC 0x00000100U |
Definition at line 3114 of file stm32f407xx.h.
| #define DMA_SxCR_CT 0x00080000U |
Definition at line 3100 of file stm32f407xx.h.
| #define DMA_SxCR_DBM 0x00040000U |
Definition at line 3101 of file stm32f407xx.h.
| #define DMA_SxCR_DIR 0x000000C0U |
Definition at line 3115 of file stm32f407xx.h.
| #define DMA_SxCR_DIR_0 0x00000040U |
Definition at line 3116 of file stm32f407xx.h.
| #define DMA_SxCR_DIR_1 0x00000080U |
Definition at line 3117 of file stm32f407xx.h.
| #define DMA_SxCR_DMEIE 0x00000002U |
Definition at line 3122 of file stm32f407xx.h.
| #define DMA_SxCR_EN 0x00000001U |
Definition at line 3123 of file stm32f407xx.h.
| #define DMA_SxCR_HTIE 0x00000008U |
Definition at line 3120 of file stm32f407xx.h.
| #define DMA_SxCR_MBURST 0x01800000U |
Definition at line 3094 of file stm32f407xx.h.
| #define DMA_SxCR_MBURST_0 0x00800000U |
Definition at line 3095 of file stm32f407xx.h.
| #define DMA_SxCR_MBURST_1 0x01000000U |
Definition at line 3096 of file stm32f407xx.h.
| #define DMA_SxCR_MINC 0x00000400U |
Definition at line 3112 of file stm32f407xx.h.
| #define DMA_SxCR_MSIZE 0x00006000U |
Definition at line 3106 of file stm32f407xx.h.
| #define DMA_SxCR_MSIZE_0 0x00002000U |
Definition at line 3107 of file stm32f407xx.h.
| #define DMA_SxCR_MSIZE_1 0x00004000U |
Definition at line 3108 of file stm32f407xx.h.
| #define DMA_SxCR_PBURST 0x00600000U |
Definition at line 3097 of file stm32f407xx.h.
| #define DMA_SxCR_PBURST_0 0x00200000U |
Definition at line 3098 of file stm32f407xx.h.
| #define DMA_SxCR_PBURST_1 0x00400000U |
Definition at line 3099 of file stm32f407xx.h.
| #define DMA_SxCR_PFCTRL 0x00000020U |
Definition at line 3118 of file stm32f407xx.h.
| #define DMA_SxCR_PINC 0x00000200U |
Definition at line 3113 of file stm32f407xx.h.
| #define DMA_SxCR_PINCOS 0x00008000U |
Definition at line 3105 of file stm32f407xx.h.
| #define DMA_SxCR_PL 0x00030000U |
Definition at line 3102 of file stm32f407xx.h.
| #define DMA_SxCR_PL_0 0x00010000U |
Definition at line 3103 of file stm32f407xx.h.
| #define DMA_SxCR_PL_1 0x00020000U |
Definition at line 3104 of file stm32f407xx.h.
| #define DMA_SxCR_PSIZE 0x00001800U |
Definition at line 3109 of file stm32f407xx.h.
| #define DMA_SxCR_PSIZE_0 0x00000800U |
Definition at line 3110 of file stm32f407xx.h.
| #define DMA_SxCR_PSIZE_1 0x00001000U |
Definition at line 3111 of file stm32f407xx.h.
| #define DMA_SxCR_TCIE 0x00000010U |
Definition at line 3119 of file stm32f407xx.h.
| #define DMA_SxCR_TEIE 0x00000004U |
Definition at line 3121 of file stm32f407xx.h.
| #define DMA_SxFCR_DMDIS 0x00000004U |
Definition at line 3153 of file stm32f407xx.h.
| #define DMA_SxFCR_FEIE 0x00000080U |
Definition at line 3148 of file stm32f407xx.h.
| #define DMA_SxFCR_FS 0x00000038U |
Definition at line 3149 of file stm32f407xx.h.
| #define DMA_SxFCR_FS_0 0x00000008U |
Definition at line 3150 of file stm32f407xx.h.
| #define DMA_SxFCR_FS_1 0x00000010U |
Definition at line 3151 of file stm32f407xx.h.
| #define DMA_SxFCR_FS_2 0x00000020U |
Definition at line 3152 of file stm32f407xx.h.
| #define DMA_SxFCR_FTH 0x00000003U |
Definition at line 3154 of file stm32f407xx.h.
| #define DMA_SxFCR_FTH_0 0x00000001U |
Definition at line 3155 of file stm32f407xx.h.
| #define DMA_SxFCR_FTH_1 0x00000002U |
Definition at line 3156 of file stm32f407xx.h.
| #define DMA_SxNDT 0x0000FFFFU |
Definition at line 3129 of file stm32f407xx.h.
| #define DMA_SxNDT_0 0x00000001U |
Definition at line 3130 of file stm32f407xx.h.
| #define DMA_SxNDT_1 0x00000002U |
Definition at line 3131 of file stm32f407xx.h.
| #define DMA_SxNDT_10 0x00000400U |
Definition at line 3140 of file stm32f407xx.h.
| #define DMA_SxNDT_11 0x00000800U |
Definition at line 3141 of file stm32f407xx.h.
| #define DMA_SxNDT_12 0x00001000U |
Definition at line 3142 of file stm32f407xx.h.
| #define DMA_SxNDT_13 0x00002000U |
Definition at line 3143 of file stm32f407xx.h.
| #define DMA_SxNDT_14 0x00004000U |
Definition at line 3144 of file stm32f407xx.h.
| #define DMA_SxNDT_15 0x00008000U |
Definition at line 3145 of file stm32f407xx.h.
| #define DMA_SxNDT_2 0x00000004U |
Definition at line 3132 of file stm32f407xx.h.
| #define DMA_SxNDT_3 0x00000008U |
Definition at line 3133 of file stm32f407xx.h.
| #define DMA_SxNDT_4 0x00000010U |
Definition at line 3134 of file stm32f407xx.h.
| #define DMA_SxNDT_5 0x00000020U |
Definition at line 3135 of file stm32f407xx.h.
| #define DMA_SxNDT_6 0x00000040U |
Definition at line 3136 of file stm32f407xx.h.
| #define DMA_SxNDT_7 0x00000080U |
Definition at line 3137 of file stm32f407xx.h.
| #define DMA_SxNDT_8 0x00000100U |
Definition at line 3138 of file stm32f407xx.h.
| #define DMA_SxNDT_9 0x00000200U |
Definition at line 3139 of file stm32f407xx.h.
| #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */ |
Definition at line 6932 of file stm32f407xx.h.
| #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */ |
Definition at line 6969 of file stm32f407xx.h.
| #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */ |
Definition at line 6968 of file stm32f407xx.h.
| #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */ |
Definition at line 6967 of file stm32f407xx.h.
| #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */ |
Definition at line 6948 of file stm32f407xx.h.
| #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */ |
Definition at line 6933 of file stm32f407xx.h.
| #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */ |
Definition at line 6954 of file stm32f407xx.h.
| #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
Definition at line 6959 of file stm32f407xx.h.
| #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
Definition at line 6955 of file stm32f407xx.h.
| #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
Definition at line 6956 of file stm32f407xx.h.
| #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
Definition at line 6960 of file stm32f407xx.h.
| #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
Definition at line 6957 of file stm32f407xx.h.
| #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
Definition at line 6966 of file stm32f407xx.h.
| #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
Definition at line 6963 of file stm32f407xx.h.
| #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
Definition at line 6964 of file stm32f407xx.h.
| #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
Definition at line 6961 of file stm32f407xx.h.
| #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
Definition at line 6965 of file stm32f407xx.h.
| #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
Definition at line 6962 of file stm32f407xx.h.
| #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
Definition at line 6958 of file stm32f407xx.h.
| #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */ |
Definition at line 6935 of file stm32f407xx.h.
| #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
Definition at line 6940 of file stm32f407xx.h.
| #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
Definition at line 6936 of file stm32f407xx.h.
| #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
Definition at line 6937 of file stm32f407xx.h.
| #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
Definition at line 6941 of file stm32f407xx.h.
| #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
Definition at line 6938 of file stm32f407xx.h.
| #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
Definition at line 6947 of file stm32f407xx.h.
| #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
Definition at line 6944 of file stm32f407xx.h.
| #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
Definition at line 6945 of file stm32f407xx.h.
| #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
Definition at line 6942 of file stm32f407xx.h.
| #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
Definition at line 6946 of file stm32f407xx.h.
| #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
Definition at line 6943 of file stm32f407xx.h.
| #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
Definition at line 6939 of file stm32f407xx.h.
| #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */ |
Definition at line 6949 of file stm32f407xx.h.
| #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */ |
Definition at line 6950 of file stm32f407xx.h.
| #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */ |
Definition at line 6951 of file stm32f407xx.h.
| #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */ |
Definition at line 6952 of file stm32f407xx.h.
| #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */ |
Definition at line 6953 of file stm32f407xx.h.
| #define ETH_DMABMR_SR 0x00000001U /* Software reset */ |
Definition at line 6970 of file stm32f407xx.h.
| #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */ |
Definition at line 6934 of file stm32f407xx.h.
| #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */ |
Definition at line 7082 of file stm32f407xx.h.
| #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */ |
Definition at line 7076 of file stm32f407xx.h.
| #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */ |
Definition at line 7079 of file stm32f407xx.h.
| #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */ |
Definition at line 7073 of file stm32f407xx.h.
| #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */ |
Definition at line 7051 of file stm32f407xx.h.
| #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */ |
Definition at line 7052 of file stm32f407xx.h.
| #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */ |
Definition at line 7054 of file stm32f407xx.h.
| #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */ |
Definition at line 7053 of file stm32f407xx.h.
| #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */ |
Definition at line 7050 of file stm32f407xx.h.
| #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */ |
Definition at line 7057 of file stm32f407xx.h.
| #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */ |
Definition at line 7058 of file stm32f407xx.h.
| #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */ |
Definition at line 7060 of file stm32f407xx.h.
| #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */ |
Definition at line 7056 of file stm32f407xx.h.
| #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */ |
Definition at line 7055 of file stm32f407xx.h.
| #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */ |
Definition at line 7062 of file stm32f407xx.h.
| #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */ |
Definition at line 7064 of file stm32f407xx.h.
| #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */ |
Definition at line 7061 of file stm32f407xx.h.
| #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */ |
Definition at line 7063 of file stm32f407xx.h.
| #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */ |
Definition at line 7059 of file stm32f407xx.h.
| #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */ |
Definition at line 7068 of file stm32f407xx.h.
| #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */ |
Definition at line 7070 of file stm32f407xx.h.
| #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */ |
Definition at line 7067 of file stm32f407xx.h.
| #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */ |
Definition at line 7069 of file stm32f407xx.h.
| #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */ |
Definition at line 7026 of file stm32f407xx.h.
| #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */ |
Definition at line 7024 of file stm32f407xx.h.
| #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */ |
Definition at line 7039 of file stm32f407xx.h.
| #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */ |
Definition at line 7028 of file stm32f407xx.h.
| #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */ |
Definition at line 7040 of file stm32f407xx.h.
| #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */ |
Definition at line 7046 of file stm32f407xx.h.
| #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */ |
Definition at line 7025 of file stm32f407xx.h.
| #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */ |
Definition at line 7041 of file stm32f407xx.h.
| #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
Definition at line 7045 of file stm32f407xx.h.
| #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
Definition at line 7043 of file stm32f407xx.h.
| #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
Definition at line 7042 of file stm32f407xx.h.
| #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
Definition at line 7044 of file stm32f407xx.h.
| #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */ |
Definition at line 7047 of file stm32f407xx.h.
| #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */ |
Definition at line 7038 of file stm32f407xx.h.
| #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */ |
Definition at line 7027 of file stm32f407xx.h.
| #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */ |
Definition at line 7029 of file stm32f407xx.h.
| #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
Definition at line 7031 of file stm32f407xx.h.
| #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
Definition at line 7037 of file stm32f407xx.h.
| #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
Definition at line 7032 of file stm32f407xx.h.
| #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
Definition at line 7036 of file stm32f407xx.h.
| #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
Definition at line 7033 of file stm32f407xx.h.
| #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
Definition at line 7035 of file stm32f407xx.h.
| #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
Definition at line 7034 of file stm32f407xx.h.
| #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
Definition at line 7030 of file stm32f407xx.h.
| #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */ |
Definition at line 6979 of file stm32f407xx.h.
| #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */ |
Definition at line 6976 of file stm32f407xx.h.
| #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */ |
Definition at line 7008 of file stm32f407xx.h.
| #define ETH_DMASR_EBS 0x03800000U /* Error bits status */ |
Definition at line 6988 of file stm32f407xx.h.
| #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */ |
Definition at line 6992 of file stm32f407xx.h.
| #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */ |
Definition at line 6990 of file stm32f407xx.h.
| #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */ |
Definition at line 6991 of file stm32f407xx.h.
| #define ETH_DMASR_ERS 0x00004000U /* Early receive status */ |
Definition at line 7009 of file stm32f407xx.h.
| #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */ |
Definition at line 7011 of file stm32f407xx.h.
| #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */ |
Definition at line 7010 of file stm32f407xx.h.
| #define ETH_DMASR_MMCS 0x08000000U /* MMC status */ |
Definition at line 6987 of file stm32f407xx.h.
| #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */ |
Definition at line 7007 of file stm32f407xx.h.
| #define ETH_DMASR_PMTS 0x10000000U /* PMT status */ |
Definition at line 6986 of file stm32f407xx.h.
| #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */ |
Definition at line 7014 of file stm32f407xx.h.
| #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */ |
Definition at line 7017 of file stm32f407xx.h.
| #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */ |
Definition at line 7000 of file stm32f407xx.h.
| #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */ |
Definition at line 7005 of file stm32f407xx.h.
| #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */ |
Definition at line 7002 of file stm32f407xx.h.
| #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */ |
Definition at line 7006 of file stm32f407xx.h.
| #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */ |
Definition at line 7001 of file stm32f407xx.h.
| #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */ |
Definition at line 7004 of file stm32f407xx.h.
| #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */ |
Definition at line 7003 of file stm32f407xx.h.
| #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */ |
Definition at line 7013 of file stm32f407xx.h.
| #define ETH_DMASR_RS 0x00000040U /* Receive status */ |
Definition at line 7015 of file stm32f407xx.h.
| #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */ |
Definition at line 7012 of file stm32f407xx.h.
| #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */ |
Definition at line 7019 of file stm32f407xx.h.
| #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */ |
Definition at line 7018 of file stm32f407xx.h.
| #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */ |
Definition at line 6993 of file stm32f407xx.h.
| #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */ |
Definition at line 6999 of file stm32f407xx.h.
| #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */ |
Definition at line 6995 of file stm32f407xx.h.
| #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */ |
Definition at line 6997 of file stm32f407xx.h.
| #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */ |
Definition at line 6994 of file stm32f407xx.h.
| #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */ |
Definition at line 6998 of file stm32f407xx.h.
| #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */ |
Definition at line 6996 of file stm32f407xx.h.
| #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */ |
Definition at line 7020 of file stm32f407xx.h.
| #define ETH_DMASR_TS 0x00000001U /* Transmit status */ |
Definition at line 7021 of file stm32f407xx.h.
| #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */ |
Definition at line 6985 of file stm32f407xx.h.
| #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */ |
Definition at line 7016 of file stm32f407xx.h.
| #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */ |
Definition at line 6982 of file stm32f407xx.h.
| #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */ |
Definition at line 6973 of file stm32f407xx.h.
| #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */ |
Definition at line 6775 of file stm32f407xx.h.
| #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */ |
Definition at line 6778 of file stm32f407xx.h.
| #define ETH_MACA1HR_AE 0x80000000U /* Address enable */ |
Definition at line 6781 of file stm32f407xx.h.
| #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */ |
Definition at line 6790 of file stm32f407xx.h.
| #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
Definition at line 6783 of file stm32f407xx.h.
| #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
Definition at line 6784 of file stm32f407xx.h.
| #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
Definition at line 6785 of file stm32f407xx.h.
| #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
Definition at line 6788 of file stm32f407xx.h.
| #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
Definition at line 6787 of file stm32f407xx.h.
| #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
Definition at line 6786 of file stm32f407xx.h.
| #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */ |
Definition at line 6789 of file stm32f407xx.h.
| #define ETH_MACA1HR_SA 0x40000000U /* Source address */ |
Definition at line 6782 of file stm32f407xx.h.
| #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */ |
Definition at line 6793 of file stm32f407xx.h.
| #define ETH_MACA2HR_AE 0x80000000U /* Address enable */ |
Definition at line 6796 of file stm32f407xx.h.
| #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */ |
Definition at line 6805 of file stm32f407xx.h.
| #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */ |
Definition at line 6798 of file stm32f407xx.h.
| #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
Definition at line 6799 of file stm32f407xx.h.
| #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
Definition at line 6800 of file stm32f407xx.h.
| #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
Definition at line 6803 of file stm32f407xx.h.
| #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
Definition at line 6802 of file stm32f407xx.h.
| #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
Definition at line 6801 of file stm32f407xx.h.
| #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ |
Definition at line 6804 of file stm32f407xx.h.
| #define ETH_MACA2HR_SA 0x40000000U /* Source address */ |
Definition at line 6797 of file stm32f407xx.h.
| #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */ |
Definition at line 6808 of file stm32f407xx.h.
| #define ETH_MACA3HR_AE 0x80000000U /* Address enable */ |
Definition at line 6811 of file stm32f407xx.h.
| #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */ |
Definition at line 6820 of file stm32f407xx.h.
| #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */ |
Definition at line 6813 of file stm32f407xx.h.
| #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
Definition at line 6814 of file stm32f407xx.h.
| #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
Definition at line 6815 of file stm32f407xx.h.
| #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
Definition at line 6818 of file stm32f407xx.h.
| #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
Definition at line 6817 of file stm32f407xx.h.
| #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
Definition at line 6816 of file stm32f407xx.h.
| #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ |
Definition at line 6819 of file stm32f407xx.h.
| #define ETH_MACA3HR_SA 0x40000000U /* Source address */ |
Definition at line 6812 of file stm32f407xx.h.
| #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */ |
Definition at line 6823 of file stm32f407xx.h.
| #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */ |
Definition at line 6676 of file stm32f407xx.h.
| #define ETH_MACCR_BL |
Definition at line 6677 of file stm32f407xx.h.
| #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */ |
Definition at line 6681 of file stm32f407xx.h.
| #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */ |
Definition at line 6678 of file stm32f407xx.h.
| #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */ |
Definition at line 6680 of file stm32f407xx.h.
| #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */ |
Definition at line 6679 of file stm32f407xx.h.
| #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */ |
Definition at line 6669 of file stm32f407xx.h.
| #define ETH_MACCR_DC 0x00000010U /* Defferal check */ |
Definition at line 6682 of file stm32f407xx.h.
| #define ETH_MACCR_DM 0x00000800U /* Duplex mode */ |
Definition at line 6673 of file stm32f407xx.h.
| #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */ |
Definition at line 6670 of file stm32f407xx.h.
| #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */ |
Definition at line 6660 of file stm32f407xx.h.
| #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */ |
Definition at line 6668 of file stm32f407xx.h.
| #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */ |
Definition at line 6667 of file stm32f407xx.h.
| #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */ |
Definition at line 6666 of file stm32f407xx.h.
| #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */ |
Definition at line 6665 of file stm32f407xx.h.
| #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */ |
Definition at line 6664 of file stm32f407xx.h.
| #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */ |
Definition at line 6663 of file stm32f407xx.h.
| #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */ |
Definition at line 6662 of file stm32f407xx.h.
| #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */ |
Definition at line 6661 of file stm32f407xx.h.
| #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */ |
Definition at line 6674 of file stm32f407xx.h.
| #define ETH_MACCR_JD 0x00400000U /* Jabber disable */ |
Definition at line 6659 of file stm32f407xx.h.
| #define ETH_MACCR_LM 0x00001000U /* loopback mode */ |
Definition at line 6672 of file stm32f407xx.h.
| #define ETH_MACCR_RD 0x00000200U /* Retry disable */ |
Definition at line 6675 of file stm32f407xx.h.
| #define ETH_MACCR_RE 0x00000004U /* Receiver enable */ |
Definition at line 6684 of file stm32f407xx.h.
| #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */ |
Definition at line 6671 of file stm32f407xx.h.
| #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */ |
Definition at line 6683 of file stm32f407xx.h.
| #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */ |
Definition at line 6658 of file stm32f407xx.h.
| #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */ |
Definition at line 6734 of file stm32f407xx.h.
| #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */ |
Definition at line 6726 of file stm32f407xx.h.
| #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */ |
Definition at line 6729 of file stm32f407xx.h.
| #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */ |
Definition at line 6730 of file stm32f407xx.h.
| #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */ |
Definition at line 6728 of file stm32f407xx.h.
| #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */ |
Definition at line 6727 of file stm32f407xx.h.
| #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */ |
Definition at line 6724 of file stm32f407xx.h.
| #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */ |
Definition at line 6732 of file stm32f407xx.h.
| #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */ |
Definition at line 6733 of file stm32f407xx.h.
| #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */ |
Definition at line 6731 of file stm32f407xx.h.
| #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */ |
Definition at line 6725 of file stm32f407xx.h.
| #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */ |
Definition at line 6695 of file stm32f407xx.h.
| #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */ |
Definition at line 6697 of file stm32f407xx.h.
| #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */ |
Definition at line 6698 of file stm32f407xx.h.
| #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */ |
Definition at line 6688 of file stm32f407xx.h.
| #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */ |
Definition at line 6699 of file stm32f407xx.h.
| #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */ |
Definition at line 6696 of file stm32f407xx.h.
| #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */ |
Definition at line 6691 of file stm32f407xx.h.
| #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */ |
Definition at line 6692 of file stm32f407xx.h.
| #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */ |
Definition at line 6693 of file stm32f407xx.h.
| #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */ |
Definition at line 6694 of file stm32f407xx.h.
| #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */ |
Definition at line 6700 of file stm32f407xx.h.
| #define ETH_MACFFR_RA 0x80000000U /* Receive all */ |
Definition at line 6687 of file stm32f407xx.h.
| #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */ |
Definition at line 6689 of file stm32f407xx.h.
| #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */ |
Definition at line 6690 of file stm32f407xx.h.
| #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */ |
Definition at line 6703 of file stm32f407xx.h.
| #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */ |
Definition at line 6706 of file stm32f407xx.h.
| #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */ |
Definition at line 6772 of file stm32f407xx.h.
| #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */ |
Definition at line 6771 of file stm32f407xx.h.
| #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */ |
Definition at line 6711 of file stm32f407xx.h.
| #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ |
Definition at line 6716 of file stm32f407xx.h.
| #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
Definition at line 6714 of file stm32f407xx.h.
| #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
Definition at line 6715 of file stm32f407xx.h.
| #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ |
Definition at line 6712 of file stm32f407xx.h.
| #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ |
Definition at line 6713 of file stm32f407xx.h.
| #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */ |
Definition at line 6718 of file stm32f407xx.h.
| #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */ |
Definition at line 6710 of file stm32f407xx.h.
| #define ETH_MACMIIAR_MW 0x00000002U /* MII write */ |
Definition at line 6717 of file stm32f407xx.h.
| #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */ |
Definition at line 6709 of file stm32f407xx.h.
| #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */ |
Definition at line 6721 of file stm32f407xx.h.
| #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */ |
Definition at line 6756 of file stm32f407xx.h.
| #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */ |
Definition at line 6760 of file stm32f407xx.h.
| #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */ |
Definition at line 6758 of file stm32f407xx.h.
| #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */ |
Definition at line 6761 of file stm32f407xx.h.
| #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */ |
Definition at line 6759 of file stm32f407xx.h.
| #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */ |
Definition at line 6755 of file stm32f407xx.h.
| #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */ |
Definition at line 6757 of file stm32f407xx.h.
| #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */ |
Definition at line 6741 of file stm32f407xx.h.
| #define ETH_MACSR_MMCS 0x00000010U /* MMC status */ |
Definition at line 6767 of file stm32f407xx.h.
| #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */ |
Definition at line 6765 of file stm32f407xx.h.
| #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */ |
Definition at line 6766 of file stm32f407xx.h.
| #define ETH_MACSR_PMTS 0x00000008U /* PMT status */ |
Definition at line 6768 of file stm32f407xx.h.
| #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */ |
Definition at line 6764 of file stm32f407xx.h.
| #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */ |
Definition at line 6737 of file stm32f407xx.h.
| #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */ |
Definition at line 6738 of file stm32f407xx.h.
| #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */ |
Definition at line 6835 of file stm32f407xx.h.
| #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */ |
Definition at line 6834 of file stm32f407xx.h.
| #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */ |
Definition at line 6832 of file stm32f407xx.h.
| #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */ |
Definition at line 6830 of file stm32f407xx.h.
| #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */ |
Definition at line 6831 of file stm32f407xx.h.
| #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */ |
Definition at line 6833 of file stm32f407xx.h.
| #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */ |
Definition at line 6870 of file stm32f407xx.h.
| #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */ |
Definition at line 6867 of file stm32f407xx.h.
| #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */ |
Definition at line 6873 of file stm32f407xx.h.
| #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
Definition at line 6849 of file stm32f407xx.h.
| #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
Definition at line 6850 of file stm32f407xx.h.
| #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
Definition at line 6848 of file stm32f407xx.h.
| #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */ |
Definition at line 6839 of file stm32f407xx.h.
| #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */ |
Definition at line 6840 of file stm32f407xx.h.
| #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */ |
Definition at line 6838 of file stm32f407xx.h.
| #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */ |
Definition at line 6864 of file stm32f407xx.h.
| #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
Definition at line 6861 of file stm32f407xx.h.
| #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
Definition at line 6858 of file stm32f407xx.h.
| #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
Definition at line 6853 of file stm32f407xx.h.
| #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
Definition at line 6854 of file stm32f407xx.h.
| #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
Definition at line 6855 of file stm32f407xx.h.
| #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */ |
Definition at line 6844 of file stm32f407xx.h.
| #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */ |
Definition at line 6843 of file stm32f407xx.h.
| #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */ |
Definition at line 6845 of file stm32f407xx.h.
| #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */ |
Definition at line 6898 of file stm32f407xx.h.
| #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */ |
Definition at line 6915 of file stm32f407xx.h.
| #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */ |
Definition at line 6890 of file stm32f407xx.h.
| #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */ |
Definition at line 6880 of file stm32f407xx.h.
| #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */ |
Definition at line 6895 of file stm32f407xx.h.
| #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */ |
Definition at line 6894 of file stm32f407xx.h.
| #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */ |
Definition at line 6891 of file stm32f407xx.h.
| #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */ |
Definition at line 6893 of file stm32f407xx.h.
| #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */ |
Definition at line 6892 of file stm32f407xx.h.
| #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */ |
Definition at line 6901 of file stm32f407xx.h.
| #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */ |
Definition at line 6908 of file stm32f407xx.h.
| #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */ |
Definition at line 6904 of file stm32f407xx.h.
| #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */ |
Definition at line 6905 of file stm32f407xx.h.
| #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */ |
Definition at line 6911 of file stm32f407xx.h.
| #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */ |
Definition at line 6912 of file stm32f407xx.h.
| #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */ |
Definition at line 6886 of file stm32f407xx.h.
| #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */ |
Definition at line 6888 of file stm32f407xx.h.
| #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */ |
Definition at line 6882 of file stm32f407xx.h.
| #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */ |
Definition at line 6883 of file stm32f407xx.h.
| #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */ |
Definition at line 6884 of file stm32f407xx.h.
| #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */ |
Definition at line 6881 of file stm32f407xx.h.
| #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */ |
Definition at line 6925 of file stm32f407xx.h.
| #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */ |
Definition at line 6885 of file stm32f407xx.h.
| #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */ |
Definition at line 6887 of file stm32f407xx.h.
| #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */ |
Definition at line 6924 of file stm32f407xx.h.
| #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */ |
Definition at line 6918 of file stm32f407xx.h.
| #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */ |
Definition at line 6921 of file stm32f407xx.h.
| #define EXTI_EMR_MR0 0x00000001U |
Event Mask on line 0
Definition at line 3278 of file stm32f407xx.h.
| #define EXTI_EMR_MR1 0x00000002U |
Event Mask on line 1
Definition at line 3279 of file stm32f407xx.h.
| #define EXTI_EMR_MR10 0x00000400U |
Event Mask on line 10
Definition at line 3288 of file stm32f407xx.h.
| #define EXTI_EMR_MR11 0x00000800U |
Event Mask on line 11
Definition at line 3289 of file stm32f407xx.h.
| #define EXTI_EMR_MR12 0x00001000U |
Event Mask on line 12
Definition at line 3290 of file stm32f407xx.h.
| #define EXTI_EMR_MR13 0x00002000U |
Event Mask on line 13
Definition at line 3291 of file stm32f407xx.h.
| #define EXTI_EMR_MR14 0x00004000U |
Event Mask on line 14
Definition at line 3292 of file stm32f407xx.h.
| #define EXTI_EMR_MR15 0x00008000U |
Event Mask on line 15
Definition at line 3293 of file stm32f407xx.h.
| #define EXTI_EMR_MR16 0x00010000U |
Event Mask on line 16
Definition at line 3294 of file stm32f407xx.h.
| #define EXTI_EMR_MR17 0x00020000U |
Event Mask on line 17
Definition at line 3295 of file stm32f407xx.h.
| #define EXTI_EMR_MR18 0x00040000U |
Event Mask on line 18
Definition at line 3296 of file stm32f407xx.h.
| #define EXTI_EMR_MR19 0x00080000U |
Event Mask on line 19
Definition at line 3297 of file stm32f407xx.h.
| #define EXTI_EMR_MR2 0x00000004U |
Event Mask on line 2
Definition at line 3280 of file stm32f407xx.h.
| #define EXTI_EMR_MR20 0x00100000U |
Event Mask on line 20
Definition at line 3298 of file stm32f407xx.h.
| #define EXTI_EMR_MR21 0x00200000U |
Event Mask on line 21
Definition at line 3299 of file stm32f407xx.h.
| #define EXTI_EMR_MR22 0x00400000U |
Event Mask on line 22
Definition at line 3300 of file stm32f407xx.h.
| #define EXTI_EMR_MR3 0x00000008U |
Event Mask on line 3
Definition at line 3281 of file stm32f407xx.h.
| #define EXTI_EMR_MR4 0x00000010U |
Event Mask on line 4
Definition at line 3282 of file stm32f407xx.h.
| #define EXTI_EMR_MR5 0x00000020U |
Event Mask on line 5
Definition at line 3283 of file stm32f407xx.h.
| #define EXTI_EMR_MR6 0x00000040U |
Event Mask on line 6
Definition at line 3284 of file stm32f407xx.h.
| #define EXTI_EMR_MR7 0x00000080U |
Event Mask on line 7
Definition at line 3285 of file stm32f407xx.h.
| #define EXTI_EMR_MR8 0x00000100U |
Event Mask on line 8
Definition at line 3286 of file stm32f407xx.h.
| #define EXTI_EMR_MR9 0x00000200U |
Event Mask on line 9
Definition at line 3287 of file stm32f407xx.h.
| #define EXTI_FTSR_TR0 0x00000001U |
Falling trigger event configuration bit of line 0
Definition at line 3328 of file stm32f407xx.h.
| #define EXTI_FTSR_TR1 0x00000002U |
Falling trigger event configuration bit of line 1
Definition at line 3329 of file stm32f407xx.h.
| #define EXTI_FTSR_TR10 0x00000400U |
Falling trigger event configuration bit of line 10
Definition at line 3338 of file stm32f407xx.h.
| #define EXTI_FTSR_TR11 0x00000800U |
Falling trigger event configuration bit of line 11
Definition at line 3339 of file stm32f407xx.h.
| #define EXTI_FTSR_TR12 0x00001000U |
Falling trigger event configuration bit of line 12
Definition at line 3340 of file stm32f407xx.h.
| #define EXTI_FTSR_TR13 0x00002000U |
Falling trigger event configuration bit of line 13
Definition at line 3341 of file stm32f407xx.h.
| #define EXTI_FTSR_TR14 0x00004000U |
Falling trigger event configuration bit of line 14
Definition at line 3342 of file stm32f407xx.h.
| #define EXTI_FTSR_TR15 0x00008000U |
Falling trigger event configuration bit of line 15
Definition at line 3343 of file stm32f407xx.h.
| #define EXTI_FTSR_TR16 0x00010000U |
Falling trigger event configuration bit of line 16
Definition at line 3344 of file stm32f407xx.h.
| #define EXTI_FTSR_TR17 0x00020000U |
Falling trigger event configuration bit of line 17
Definition at line 3345 of file stm32f407xx.h.
| #define EXTI_FTSR_TR18 0x00040000U |
Falling trigger event configuration bit of line 18
Definition at line 3346 of file stm32f407xx.h.
| #define EXTI_FTSR_TR19 0x00080000U |
Falling trigger event configuration bit of line 19
Definition at line 3347 of file stm32f407xx.h.
| #define EXTI_FTSR_TR2 0x00000004U |
Falling trigger event configuration bit of line 2
Definition at line 3330 of file stm32f407xx.h.
| #define EXTI_FTSR_TR20 0x00100000U |
Falling trigger event configuration bit of line 20
Definition at line 3348 of file stm32f407xx.h.
| #define EXTI_FTSR_TR21 0x00200000U |
Falling trigger event configuration bit of line 21
Definition at line 3349 of file stm32f407xx.h.
| #define EXTI_FTSR_TR22 0x00400000U |
Falling trigger event configuration bit of line 22
Definition at line 3350 of file stm32f407xx.h.
| #define EXTI_FTSR_TR3 0x00000008U |
Falling trigger event configuration bit of line 3
Definition at line 3331 of file stm32f407xx.h.
| #define EXTI_FTSR_TR4 0x00000010U |
Falling trigger event configuration bit of line 4
Definition at line 3332 of file stm32f407xx.h.
| #define EXTI_FTSR_TR5 0x00000020U |
Falling trigger event configuration bit of line 5
Definition at line 3333 of file stm32f407xx.h.
| #define EXTI_FTSR_TR6 0x00000040U |
Falling trigger event configuration bit of line 6
Definition at line 3334 of file stm32f407xx.h.
| #define EXTI_FTSR_TR7 0x00000080U |
Falling trigger event configuration bit of line 7
Definition at line 3335 of file stm32f407xx.h.
| #define EXTI_FTSR_TR8 0x00000100U |
Falling trigger event configuration bit of line 8
Definition at line 3336 of file stm32f407xx.h.
| #define EXTI_FTSR_TR9 0x00000200U |
Falling trigger event configuration bit of line 9
Definition at line 3337 of file stm32f407xx.h.
| #define EXTI_IMR_MR0 0x00000001U |
Interrupt Mask on line 0
Definition at line 3253 of file stm32f407xx.h.
| #define EXTI_IMR_MR1 0x00000002U |
Interrupt Mask on line 1
Definition at line 3254 of file stm32f407xx.h.
| #define EXTI_IMR_MR10 0x00000400U |
Interrupt Mask on line 10
Definition at line 3263 of file stm32f407xx.h.
| #define EXTI_IMR_MR11 0x00000800U |
Interrupt Mask on line 11
Definition at line 3264 of file stm32f407xx.h.
| #define EXTI_IMR_MR12 0x00001000U |
Interrupt Mask on line 12
Definition at line 3265 of file stm32f407xx.h.
| #define EXTI_IMR_MR13 0x00002000U |
Interrupt Mask on line 13
Definition at line 3266 of file stm32f407xx.h.
| #define EXTI_IMR_MR14 0x00004000U |
Interrupt Mask on line 14
Definition at line 3267 of file stm32f407xx.h.
| #define EXTI_IMR_MR15 0x00008000U |
Interrupt Mask on line 15
Definition at line 3268 of file stm32f407xx.h.
| #define EXTI_IMR_MR16 0x00010000U |
Interrupt Mask on line 16
Definition at line 3269 of file stm32f407xx.h.
| #define EXTI_IMR_MR17 0x00020000U |
Interrupt Mask on line 17
Definition at line 3270 of file stm32f407xx.h.
| #define EXTI_IMR_MR18 0x00040000U |
Interrupt Mask on line 18
Definition at line 3271 of file stm32f407xx.h.
| #define EXTI_IMR_MR19 0x00080000U |
Interrupt Mask on line 19
Definition at line 3272 of file stm32f407xx.h.
| #define EXTI_IMR_MR2 0x00000004U |
Interrupt Mask on line 2
Definition at line 3255 of file stm32f407xx.h.
| #define EXTI_IMR_MR20 0x00100000U |
Interrupt Mask on line 20
Definition at line 3273 of file stm32f407xx.h.
| #define EXTI_IMR_MR21 0x00200000U |
Interrupt Mask on line 21
Definition at line 3274 of file stm32f407xx.h.
| #define EXTI_IMR_MR22 0x00400000U |
Interrupt Mask on line 22
Definition at line 3275 of file stm32f407xx.h.
| #define EXTI_IMR_MR3 0x00000008U |
Interrupt Mask on line 3
Definition at line 3256 of file stm32f407xx.h.
| #define EXTI_IMR_MR4 0x00000010U |
Interrupt Mask on line 4
Definition at line 3257 of file stm32f407xx.h.
| #define EXTI_IMR_MR5 0x00000020U |
Interrupt Mask on line 5
Definition at line 3258 of file stm32f407xx.h.
| #define EXTI_IMR_MR6 0x00000040U |
Interrupt Mask on line 6
Definition at line 3259 of file stm32f407xx.h.
| #define EXTI_IMR_MR7 0x00000080U |
Interrupt Mask on line 7
Definition at line 3260 of file stm32f407xx.h.
| #define EXTI_IMR_MR8 0x00000100U |
Interrupt Mask on line 8
Definition at line 3261 of file stm32f407xx.h.
| #define EXTI_IMR_MR9 0x00000200U |
Interrupt Mask on line 9
Definition at line 3262 of file stm32f407xx.h.
| #define EXTI_PR_PR0 0x00000001U |
Pending bit for line 0
Definition at line 3378 of file stm32f407xx.h.
| #define EXTI_PR_PR1 0x00000002U |
Pending bit for line 1
Definition at line 3379 of file stm32f407xx.h.
| #define EXTI_PR_PR10 0x00000400U |
Pending bit for line 10
Definition at line 3388 of file stm32f407xx.h.
| #define EXTI_PR_PR11 0x00000800U |
Pending bit for line 11
Definition at line 3389 of file stm32f407xx.h.
| #define EXTI_PR_PR12 0x00001000U |
Pending bit for line 12
Definition at line 3390 of file stm32f407xx.h.
| #define EXTI_PR_PR13 0x00002000U |
Pending bit for line 13
Definition at line 3391 of file stm32f407xx.h.
| #define EXTI_PR_PR14 0x00004000U |
Pending bit for line 14
Definition at line 3392 of file stm32f407xx.h.
| #define EXTI_PR_PR15 0x00008000U |
Pending bit for line 15
Definition at line 3393 of file stm32f407xx.h.
| #define EXTI_PR_PR16 0x00010000U |
Pending bit for line 16
Definition at line 3394 of file stm32f407xx.h.
| #define EXTI_PR_PR17 0x00020000U |
Pending bit for line 17
Definition at line 3395 of file stm32f407xx.h.
| #define EXTI_PR_PR18 0x00040000U |
Pending bit for line 18
Definition at line 3396 of file stm32f407xx.h.
| #define EXTI_PR_PR19 0x00080000U |
Pending bit for line 19
Definition at line 3397 of file stm32f407xx.h.
| #define EXTI_PR_PR2 0x00000004U |
Pending bit for line 2
Definition at line 3380 of file stm32f407xx.h.
| #define EXTI_PR_PR20 0x00100000U |
Pending bit for line 20
Definition at line 3398 of file stm32f407xx.h.
| #define EXTI_PR_PR21 0x00200000U |
Pending bit for line 21
Definition at line 3399 of file stm32f407xx.h.
| #define EXTI_PR_PR22 0x00400000U |
Pending bit for line 22
Definition at line 3400 of file stm32f407xx.h.
| #define EXTI_PR_PR3 0x00000008U |
Pending bit for line 3
Definition at line 3381 of file stm32f407xx.h.
| #define EXTI_PR_PR4 0x00000010U |
Pending bit for line 4
Definition at line 3382 of file stm32f407xx.h.
| #define EXTI_PR_PR5 0x00000020U |
Pending bit for line 5
Definition at line 3383 of file stm32f407xx.h.
| #define EXTI_PR_PR6 0x00000040U |
Pending bit for line 6
Definition at line 3384 of file stm32f407xx.h.
| #define EXTI_PR_PR7 0x00000080U |
Pending bit for line 7
Definition at line 3385 of file stm32f407xx.h.
| #define EXTI_PR_PR8 0x00000100U |
Pending bit for line 8
Definition at line 3386 of file stm32f407xx.h.
| #define EXTI_PR_PR9 0x00000200U |
Pending bit for line 9
Definition at line 3387 of file stm32f407xx.h.
| #define EXTI_RTSR_TR0 0x00000001U |
Rising trigger event configuration bit of line 0
Definition at line 3303 of file stm32f407xx.h.
| #define EXTI_RTSR_TR1 0x00000002U |
Rising trigger event configuration bit of line 1
Definition at line 3304 of file stm32f407xx.h.
| #define EXTI_RTSR_TR10 0x00000400U |
Rising trigger event configuration bit of line 10
Definition at line 3313 of file stm32f407xx.h.
| #define EXTI_RTSR_TR11 0x00000800U |
Rising trigger event configuration bit of line 11
Definition at line 3314 of file stm32f407xx.h.
| #define EXTI_RTSR_TR12 0x00001000U |
Rising trigger event configuration bit of line 12
Definition at line 3315 of file stm32f407xx.h.
| #define EXTI_RTSR_TR13 0x00002000U |
Rising trigger event configuration bit of line 13
Definition at line 3316 of file stm32f407xx.h.
| #define EXTI_RTSR_TR14 0x00004000U |
Rising trigger event configuration bit of line 14
Definition at line 3317 of file stm32f407xx.h.
| #define EXTI_RTSR_TR15 0x00008000U |
Rising trigger event configuration bit of line 15
Definition at line 3318 of file stm32f407xx.h.
| #define EXTI_RTSR_TR16 0x00010000U |
Rising trigger event configuration bit of line 16
Definition at line 3319 of file stm32f407xx.h.
| #define EXTI_RTSR_TR17 0x00020000U |
Rising trigger event configuration bit of line 17
Definition at line 3320 of file stm32f407xx.h.
| #define EXTI_RTSR_TR18 0x00040000U |
Rising trigger event configuration bit of line 18
Definition at line 3321 of file stm32f407xx.h.
| #define EXTI_RTSR_TR19 0x00080000U |
Rising trigger event configuration bit of line 19
Definition at line 3322 of file stm32f407xx.h.
| #define EXTI_RTSR_TR2 0x00000004U |
Rising trigger event configuration bit of line 2
Definition at line 3305 of file stm32f407xx.h.
| #define EXTI_RTSR_TR20 0x00100000U |
Rising trigger event configuration bit of line 20
Definition at line 3323 of file stm32f407xx.h.
| #define EXTI_RTSR_TR21 0x00200000U |
Rising trigger event configuration bit of line 21
Definition at line 3324 of file stm32f407xx.h.
| #define EXTI_RTSR_TR22 0x00400000U |
Rising trigger event configuration bit of line 22
Definition at line 3325 of file stm32f407xx.h.
| #define EXTI_RTSR_TR3 0x00000008U |
Rising trigger event configuration bit of line 3
Definition at line 3306 of file stm32f407xx.h.
| #define EXTI_RTSR_TR4 0x00000010U |
Rising trigger event configuration bit of line 4
Definition at line 3307 of file stm32f407xx.h.
| #define EXTI_RTSR_TR5 0x00000020U |
Rising trigger event configuration bit of line 5
Definition at line 3308 of file stm32f407xx.h.
| #define EXTI_RTSR_TR6 0x00000040U |
Rising trigger event configuration bit of line 6
Definition at line 3309 of file stm32f407xx.h.
| #define EXTI_RTSR_TR7 0x00000080U |
Rising trigger event configuration bit of line 7
Definition at line 3310 of file stm32f407xx.h.
| #define EXTI_RTSR_TR8 0x00000100U |
Rising trigger event configuration bit of line 8
Definition at line 3311 of file stm32f407xx.h.
| #define EXTI_RTSR_TR9 0x00000200U |
Rising trigger event configuration bit of line 9
Definition at line 3312 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER0 0x00000001U |
Software Interrupt on line 0
Definition at line 3353 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER1 0x00000002U |
Software Interrupt on line 1
Definition at line 3354 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER10 0x00000400U |
Software Interrupt on line 10
Definition at line 3363 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER11 0x00000800U |
Software Interrupt on line 11
Definition at line 3364 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER12 0x00001000U |
Software Interrupt on line 12
Definition at line 3365 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER13 0x00002000U |
Software Interrupt on line 13
Definition at line 3366 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER14 0x00004000U |
Software Interrupt on line 14
Definition at line 3367 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER15 0x00008000U |
Software Interrupt on line 15
Definition at line 3368 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER16 0x00010000U |
Software Interrupt on line 16
Definition at line 3369 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER17 0x00020000U |
Software Interrupt on line 17
Definition at line 3370 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER18 0x00040000U |
Software Interrupt on line 18
Definition at line 3371 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER19 0x00080000U |
Software Interrupt on line 19
Definition at line 3372 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER2 0x00000004U |
Software Interrupt on line 2
Definition at line 3355 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER20 0x00100000U |
Software Interrupt on line 20
Definition at line 3373 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER21 0x00200000U |
Software Interrupt on line 21
Definition at line 3374 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER22 0x00400000U |
Software Interrupt on line 22
Definition at line 3375 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER3 0x00000008U |
Software Interrupt on line 3
Definition at line 3356 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER4 0x00000010U |
Software Interrupt on line 4
Definition at line 3357 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER5 0x00000020U |
Software Interrupt on line 5
Definition at line 3358 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER6 0x00000040U |
Software Interrupt on line 6
Definition at line 3359 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER7 0x00000080U |
Software Interrupt on line 7
Definition at line 3360 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER8 0x00000100U |
Software Interrupt on line 8
Definition at line 3361 of file stm32f407xx.h.
| #define EXTI_SWIER_SWIER9 0x00000200U |
Software Interrupt on line 9
Definition at line 3362 of file stm32f407xx.h.
| #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U |
Definition at line 3423 of file stm32f407xx.h.
| #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U |
Definition at line 3424 of file stm32f407xx.h.
| #define FLASH_ACR_DCEN 0x00000400U |
Definition at line 3420 of file stm32f407xx.h.
| #define FLASH_ACR_DCRST 0x00001000U |
Definition at line 3422 of file stm32f407xx.h.
| #define FLASH_ACR_ICEN 0x00000200U |
Definition at line 3419 of file stm32f407xx.h.
| #define FLASH_ACR_ICRST 0x00000800U |
Definition at line 3421 of file stm32f407xx.h.
| #define FLASH_ACR_LATENCY 0x0000000FU |
Definition at line 3408 of file stm32f407xx.h.
| #define FLASH_ACR_LATENCY_0WS 0x00000000U |
Definition at line 3409 of file stm32f407xx.h.
| #define FLASH_ACR_LATENCY_1WS 0x00000001U |
Definition at line 3410 of file stm32f407xx.h.
| #define FLASH_ACR_LATENCY_2WS 0x00000002U |
Definition at line 3411 of file stm32f407xx.h.
| #define FLASH_ACR_LATENCY_3WS 0x00000003U |
Definition at line 3412 of file stm32f407xx.h.
| #define FLASH_ACR_LATENCY_4WS 0x00000004U |
Definition at line 3413 of file stm32f407xx.h.
| #define FLASH_ACR_LATENCY_5WS 0x00000005U |
Definition at line 3414 of file stm32f407xx.h.
| #define FLASH_ACR_LATENCY_6WS 0x00000006U |
Definition at line 3415 of file stm32f407xx.h.
| #define FLASH_ACR_LATENCY_7WS 0x00000007U |
Definition at line 3416 of file stm32f407xx.h.
| #define FLASH_ACR_PRFTEN 0x00000100U |
Definition at line 3418 of file stm32f407xx.h.
| #define FLASH_CR_EOPIE 0x01000000U |
Definition at line 3449 of file stm32f407xx.h.
| #define FLASH_CR_LOCK 0x80000000U |
Definition at line 3450 of file stm32f407xx.h.
| #define FLASH_CR_MER 0x00000004U |
Definition at line 3438 of file stm32f407xx.h.
| #define FLASH_CR_PG 0x00000001U |
Definition at line 3436 of file stm32f407xx.h.
| #define FLASH_CR_PSIZE 0x00000300U |
Definition at line 3445 of file stm32f407xx.h.
| #define FLASH_CR_PSIZE_0 0x00000100U |
Definition at line 3446 of file stm32f407xx.h.
| #define FLASH_CR_PSIZE_1 0x00000200U |
Definition at line 3447 of file stm32f407xx.h.
| #define FLASH_CR_SER 0x00000002U |
Definition at line 3437 of file stm32f407xx.h.
| #define FLASH_CR_SNB 0x000000F8U |
Definition at line 3439 of file stm32f407xx.h.
| #define FLASH_CR_SNB_0 0x00000008U |
Definition at line 3440 of file stm32f407xx.h.
| #define FLASH_CR_SNB_1 0x00000010U |
Definition at line 3441 of file stm32f407xx.h.
| #define FLASH_CR_SNB_2 0x00000020U |
Definition at line 3442 of file stm32f407xx.h.
| #define FLASH_CR_SNB_3 0x00000040U |
Definition at line 3443 of file stm32f407xx.h.
| #define FLASH_CR_SNB_4 0x00000080U |
Definition at line 3444 of file stm32f407xx.h.
| #define FLASH_CR_STRT 0x00010000U |
Definition at line 3448 of file stm32f407xx.h.
| #define FLASH_OPTCR1_nWRP 0x0FFF0000U |
Definition at line 3486 of file stm32f407xx.h.
| #define FLASH_OPTCR1_nWRP_0 0x00010000U |
Definition at line 3487 of file stm32f407xx.h.
| #define FLASH_OPTCR1_nWRP_1 0x00020000U |
Definition at line 3488 of file stm32f407xx.h.
| #define FLASH_OPTCR1_nWRP_10 0x04000000U |
Definition at line 3497 of file stm32f407xx.h.
| #define FLASH_OPTCR1_nWRP_11 0x08000000U |
Definition at line 3498 of file stm32f407xx.h.
| #define FLASH_OPTCR1_nWRP_2 0x00040000U |
Definition at line 3489 of file stm32f407xx.h.
| #define FLASH_OPTCR1_nWRP_3 0x00080000U |
Definition at line 3490 of file stm32f407xx.h.
| #define FLASH_OPTCR1_nWRP_4 0x00100000U |
Definition at line 3491 of file stm32f407xx.h.
| #define FLASH_OPTCR1_nWRP_5 0x00200000U |
Definition at line 3492 of file stm32f407xx.h.
| #define FLASH_OPTCR1_nWRP_6 0x00400000U |
Definition at line 3493 of file stm32f407xx.h.
| #define FLASH_OPTCR1_nWRP_7 0x00800000U |
Definition at line 3494 of file stm32f407xx.h.
| #define FLASH_OPTCR1_nWRP_8 0x01000000U |
Definition at line 3495 of file stm32f407xx.h.
| #define FLASH_OPTCR1_nWRP_9 0x02000000U |
Definition at line 3496 of file stm32f407xx.h.
| #define FLASH_OPTCR_BOR_LEV 0x0000000CU |
Definition at line 3457 of file stm32f407xx.h.
| #define FLASH_OPTCR_BOR_LEV_0 0x00000004U |
Definition at line 3455 of file stm32f407xx.h.
| #define FLASH_OPTCR_BOR_LEV_1 0x00000008U |
Definition at line 3456 of file stm32f407xx.h.
| #define FLASH_OPTCR_nRST_STDBY 0x00000080U |
Definition at line 3461 of file stm32f407xx.h.
| #define FLASH_OPTCR_nRST_STOP 0x00000040U |
Definition at line 3460 of file stm32f407xx.h.
| #define FLASH_OPTCR_nWRP 0x0FFF0000U |
Definition at line 3471 of file stm32f407xx.h.
| #define FLASH_OPTCR_nWRP_0 0x00010000U |
Definition at line 3472 of file stm32f407xx.h.
| #define FLASH_OPTCR_nWRP_1 0x00020000U |
Definition at line 3473 of file stm32f407xx.h.
| #define FLASH_OPTCR_nWRP_10 0x04000000U |
Definition at line 3482 of file stm32f407xx.h.
| #define FLASH_OPTCR_nWRP_11 0x08000000U |
Definition at line 3483 of file stm32f407xx.h.
| #define FLASH_OPTCR_nWRP_2 0x00040000U |
Definition at line 3474 of file stm32f407xx.h.
| #define FLASH_OPTCR_nWRP_3 0x00080000U |
Definition at line 3475 of file stm32f407xx.h.
| #define FLASH_OPTCR_nWRP_4 0x00100000U |
Definition at line 3476 of file stm32f407xx.h.
| #define FLASH_OPTCR_nWRP_5 0x00200000U |
Definition at line 3477 of file stm32f407xx.h.
| #define FLASH_OPTCR_nWRP_6 0x00400000U |
Definition at line 3478 of file stm32f407xx.h.
| #define FLASH_OPTCR_nWRP_7 0x00800000U |
Definition at line 3479 of file stm32f407xx.h.
| #define FLASH_OPTCR_nWRP_8 0x01000000U |
Definition at line 3480 of file stm32f407xx.h.
| #define FLASH_OPTCR_nWRP_9 0x02000000U |
Definition at line 3481 of file stm32f407xx.h.
| #define FLASH_OPTCR_OPTLOCK 0x00000001U |
Definition at line 3453 of file stm32f407xx.h.
| #define FLASH_OPTCR_OPTSTRT 0x00000002U |
Definition at line 3454 of file stm32f407xx.h.
| #define FLASH_OPTCR_RDP 0x0000FF00U |
Definition at line 3462 of file stm32f407xx.h.
| #define FLASH_OPTCR_RDP_0 0x00000100U |
Definition at line 3463 of file stm32f407xx.h.
| #define FLASH_OPTCR_RDP_1 0x00000200U |
Definition at line 3464 of file stm32f407xx.h.
| #define FLASH_OPTCR_RDP_2 0x00000400U |
Definition at line 3465 of file stm32f407xx.h.
| #define FLASH_OPTCR_RDP_3 0x00000800U |
Definition at line 3466 of file stm32f407xx.h.
| #define FLASH_OPTCR_RDP_4 0x00001000U |
Definition at line 3467 of file stm32f407xx.h.
| #define FLASH_OPTCR_RDP_5 0x00002000U |
Definition at line 3468 of file stm32f407xx.h.
| #define FLASH_OPTCR_RDP_6 0x00004000U |
Definition at line 3469 of file stm32f407xx.h.
| #define FLASH_OPTCR_RDP_7 0x00008000U |
Definition at line 3470 of file stm32f407xx.h.
| #define FLASH_OPTCR_WDG_SW 0x00000020U |
Definition at line 3459 of file stm32f407xx.h.
| #define FLASH_SR_BSY 0x00010000U |
Definition at line 3433 of file stm32f407xx.h.
| #define FLASH_SR_EOP 0x00000001U |
Definition at line 3427 of file stm32f407xx.h.
| #define FLASH_SR_PGAERR 0x00000020U |
Definition at line 3430 of file stm32f407xx.h.
| #define FLASH_SR_PGPERR 0x00000040U |
Definition at line 3431 of file stm32f407xx.h.
| #define FLASH_SR_PGSERR 0x00000080U |
Definition at line 3432 of file stm32f407xx.h.
| #define FLASH_SR_SOP 0x00000002U |
Definition at line 3428 of file stm32f407xx.h.
| #define FLASH_SR_WRPERR 0x00000010U |
Definition at line 3429 of file stm32f407xx.h.
| #define FSMC_BCR1_ASYNCWAIT 0x00008000U |
Asynchronous wait
Definition at line 3525 of file stm32f407xx.h.
| #define FSMC_BCR1_BURSTEN 0x00000100U |
Burst enable bit
Definition at line 3518 of file stm32f407xx.h.
| #define FSMC_BCR1_CBURSTRW 0x00080000U |
Write burst enable
Definition at line 3530 of file stm32f407xx.h.
| #define FSMC_BCR1_CPSIZE 0x00070000U |
CRAM page size
Definition at line 3526 of file stm32f407xx.h.
| #define FSMC_BCR1_CPSIZE_0 0x00010000U |
Bit 0
Definition at line 3527 of file stm32f407xx.h.
| #define FSMC_BCR1_CPSIZE_1 0x00020000U |
Bit 1
Definition at line 3528 of file stm32f407xx.h.
| #define FSMC_BCR1_CPSIZE_2 0x00040000U |
Bit 2
Definition at line 3529 of file stm32f407xx.h.
| #define FSMC_BCR1_EXTMOD 0x00004000U |
Extended mode enable
Definition at line 3524 of file stm32f407xx.h.
| #define FSMC_BCR1_FACCEN 0x00000040U |
Flash access enable
Definition at line 3517 of file stm32f407xx.h.
| #define FSMC_BCR1_MBKEN 0x00000001U |
Memory bank enable bit
Definition at line 3506 of file stm32f407xx.h.
| #define FSMC_BCR1_MTYP 0x0000000CU |
MTYP[1:0] bits (Memory type)
Definition at line 3509 of file stm32f407xx.h.
| #define FSMC_BCR1_MTYP_0 0x00000004U |
Bit 0
Definition at line 3510 of file stm32f407xx.h.
| #define FSMC_BCR1_MTYP_1 0x00000008U |
Bit 1
Definition at line 3511 of file stm32f407xx.h.
| #define FSMC_BCR1_MUXEN 0x00000002U |
Address/data multiplexing enable bit
Definition at line 3507 of file stm32f407xx.h.
| #define FSMC_BCR1_MWID 0x00000030U |
MWID[1:0] bits (Memory data bus width)
Definition at line 3513 of file stm32f407xx.h.
| #define FSMC_BCR1_MWID_0 0x00000010U |
Bit 0
Definition at line 3514 of file stm32f407xx.h.
| #define FSMC_BCR1_MWID_1 0x00000020U |
Bit 1
Definition at line 3515 of file stm32f407xx.h.
| #define FSMC_BCR1_WAITCFG 0x00000800U |
Wait timing configuration
Definition at line 3521 of file stm32f407xx.h.
| #define FSMC_BCR1_WAITEN 0x00002000U |
Wait enable bit
Definition at line 3523 of file stm32f407xx.h.
| #define FSMC_BCR1_WAITPOL 0x00000200U |
Wait signal polarity bit
Definition at line 3519 of file stm32f407xx.h.
| #define FSMC_BCR1_WRAPMOD 0x00000400U |
Wrapped burst mode support
Definition at line 3520 of file stm32f407xx.h.
| #define FSMC_BCR1_WREN 0x00001000U |
Write enable bit
Definition at line 3522 of file stm32f407xx.h.
| #define FSMC_BCR2_ASYNCWAIT 0x00008000U |
Asynchronous wait
Definition at line 3552 of file stm32f407xx.h.
| #define FSMC_BCR2_BURSTEN 0x00000100U |
Burst enable bit
Definition at line 3545 of file stm32f407xx.h.
| #define FSMC_BCR2_CBURSTRW 0x00080000U |
Write burst enable
Definition at line 3557 of file stm32f407xx.h.
| #define FSMC_BCR2_CPSIZE 0x00070000U |
CRAM page size
Definition at line 3553 of file stm32f407xx.h.
| #define FSMC_BCR2_CPSIZE_0 0x00010000U |
Bit 0
Definition at line 3554 of file stm32f407xx.h.
| #define FSMC_BCR2_CPSIZE_1 0x00020000U |
Bit 1
Definition at line 3555 of file stm32f407xx.h.
| #define FSMC_BCR2_CPSIZE_2 0x00040000U |
Bit 2
Definition at line 3556 of file stm32f407xx.h.
| #define FSMC_BCR2_EXTMOD 0x00004000U |
Extended mode enable
Definition at line 3551 of file stm32f407xx.h.
| #define FSMC_BCR2_FACCEN 0x00000040U |
Flash access enable
Definition at line 3544 of file stm32f407xx.h.
| #define FSMC_BCR2_MBKEN 0x00000001U |
Memory bank enable bit
Definition at line 3533 of file stm32f407xx.h.
| #define FSMC_BCR2_MTYP 0x0000000CU |
MTYP[1:0] bits (Memory type)
Definition at line 3536 of file stm32f407xx.h.
| #define FSMC_BCR2_MTYP_0 0x00000004U |
Bit 0
Definition at line 3537 of file stm32f407xx.h.
| #define FSMC_BCR2_MTYP_1 0x00000008U |
Bit 1
Definition at line 3538 of file stm32f407xx.h.
| #define FSMC_BCR2_MUXEN 0x00000002U |
Address/data multiplexing enable bit
Definition at line 3534 of file stm32f407xx.h.
| #define FSMC_BCR2_MWID 0x00000030U |
MWID[1:0] bits (Memory data bus width)
Definition at line 3540 of file stm32f407xx.h.
| #define FSMC_BCR2_MWID_0 0x00000010U |
Bit 0
Definition at line 3541 of file stm32f407xx.h.
| #define FSMC_BCR2_MWID_1 0x00000020U |
Bit 1
Definition at line 3542 of file stm32f407xx.h.
| #define FSMC_BCR2_WAITCFG 0x00000800U |
Wait timing configuration
Definition at line 3548 of file stm32f407xx.h.
| #define FSMC_BCR2_WAITEN 0x00002000U |
Wait enable bit
Definition at line 3550 of file stm32f407xx.h.
| #define FSMC_BCR2_WAITPOL 0x00000200U |
Wait signal polarity bit
Definition at line 3546 of file stm32f407xx.h.
| #define FSMC_BCR2_WRAPMOD 0x00000400U |
Wrapped burst mode support
Definition at line 3547 of file stm32f407xx.h.
| #define FSMC_BCR2_WREN 0x00001000U |
Write enable bit
Definition at line 3549 of file stm32f407xx.h.
| #define FSMC_BCR3_ASYNCWAIT 0x00008000U |
Asynchronous wait
Definition at line 3579 of file stm32f407xx.h.
| #define FSMC_BCR3_BURSTEN 0x00000100U |
Burst enable bit
Definition at line 3572 of file stm32f407xx.h.
| #define FSMC_BCR3_CBURSTRW 0x00080000U |
Write burst enable
Definition at line 3584 of file stm32f407xx.h.
| #define FSMC_BCR3_CPSIZE 0x00070000U |
CRAM page size
Definition at line 3580 of file stm32f407xx.h.
| #define FSMC_BCR3_CPSIZE_0 0x00010000U |
Bit 0
Definition at line 3581 of file stm32f407xx.h.
| #define FSMC_BCR3_CPSIZE_1 0x00020000U |
Bit 1
Definition at line 3582 of file stm32f407xx.h.
| #define FSMC_BCR3_CPSIZE_2 0x00040000U |
Bit 2
Definition at line 3583 of file stm32f407xx.h.
| #define FSMC_BCR3_EXTMOD 0x00004000U |
Extended mode enable
Definition at line 3578 of file stm32f407xx.h.
| #define FSMC_BCR3_FACCEN 0x00000040U |
Flash access enable
Definition at line 3571 of file stm32f407xx.h.
| #define FSMC_BCR3_MBKEN 0x00000001U |
Memory bank enable bit
Definition at line 3560 of file stm32f407xx.h.
| #define FSMC_BCR3_MTYP 0x0000000CU |
MTYP[1:0] bits (Memory type)
Definition at line 3563 of file stm32f407xx.h.
| #define FSMC_BCR3_MTYP_0 0x00000004U |
Bit 0
Definition at line 3564 of file stm32f407xx.h.
| #define FSMC_BCR3_MTYP_1 0x00000008U |
Bit 1
Definition at line 3565 of file stm32f407xx.h.
| #define FSMC_BCR3_MUXEN 0x00000002U |
Address/data multiplexing enable bit
Definition at line 3561 of file stm32f407xx.h.
| #define FSMC_BCR3_MWID 0x00000030U |
MWID[1:0] bits (Memory data bus width)
Definition at line 3567 of file stm32f407xx.h.
| #define FSMC_BCR3_MWID_0 0x00000010U |
Bit 0
Definition at line 3568 of file stm32f407xx.h.
| #define FSMC_BCR3_MWID_1 0x00000020U |
Bit 1
Definition at line 3569 of file stm32f407xx.h.
| #define FSMC_BCR3_WAITCFG 0x00000800U |
Wait timing configuration
Definition at line 3575 of file stm32f407xx.h.
| #define FSMC_BCR3_WAITEN 0x00002000U |
Wait enable bit
Definition at line 3577 of file stm32f407xx.h.
| #define FSMC_BCR3_WAITPOL 0x00000200U |
Wait signal polarity bit
Definition at line 3573 of file stm32f407xx.h.
| #define FSMC_BCR3_WRAPMOD 0x00000400U |
Wrapped burst mode support
Definition at line 3574 of file stm32f407xx.h.
| #define FSMC_BCR3_WREN 0x00001000U |
Write enable bit
Definition at line 3576 of file stm32f407xx.h.
| #define FSMC_BCR4_ASYNCWAIT 0x00008000U |
Asynchronous wait
Definition at line 3606 of file stm32f407xx.h.
| #define FSMC_BCR4_BURSTEN 0x00000100U |
Burst enable bit
Definition at line 3599 of file stm32f407xx.h.
| #define FSMC_BCR4_CBURSTRW 0x00080000U |
Write burst enable
Definition at line 3611 of file stm32f407xx.h.
| #define FSMC_BCR4_CPSIZE 0x00070000U |
CRAM page size
Definition at line 3607 of file stm32f407xx.h.
| #define FSMC_BCR4_CPSIZE_0 0x00010000U |
Bit 0
Definition at line 3608 of file stm32f407xx.h.
| #define FSMC_BCR4_CPSIZE_1 0x00020000U |
Bit 1
Definition at line 3609 of file stm32f407xx.h.
| #define FSMC_BCR4_CPSIZE_2 0x00040000U |
Bit 2
Definition at line 3610 of file stm32f407xx.h.
| #define FSMC_BCR4_EXTMOD 0x00004000U |
Extended mode enable
Definition at line 3605 of file stm32f407xx.h.
| #define FSMC_BCR4_FACCEN 0x00000040U |
Flash access enable
Definition at line 3598 of file stm32f407xx.h.
| #define FSMC_BCR4_MBKEN 0x00000001U |
Memory bank enable bit
Definition at line 3587 of file stm32f407xx.h.
| #define FSMC_BCR4_MTYP 0x0000000CU |
MTYP[1:0] bits (Memory type)
Definition at line 3590 of file stm32f407xx.h.
| #define FSMC_BCR4_MTYP_0 0x00000004U |
Bit 0
Definition at line 3591 of file stm32f407xx.h.
| #define FSMC_BCR4_MTYP_1 0x00000008U |
Bit 1
Definition at line 3592 of file stm32f407xx.h.
| #define FSMC_BCR4_MUXEN 0x00000002U |
Address/data multiplexing enable bit
Definition at line 3588 of file stm32f407xx.h.
| #define FSMC_BCR4_MWID 0x00000030U |
MWID[1:0] bits (Memory data bus width)
Definition at line 3594 of file stm32f407xx.h.
| #define FSMC_BCR4_MWID_0 0x00000010U |
Bit 0
Definition at line 3595 of file stm32f407xx.h.
| #define FSMC_BCR4_MWID_1 0x00000020U |
Bit 1
Definition at line 3596 of file stm32f407xx.h.
| #define FSMC_BCR4_WAITCFG 0x00000800U |
Wait timing configuration
Definition at line 3602 of file stm32f407xx.h.
| #define FSMC_BCR4_WAITEN 0x00002000U |
Wait enable bit
Definition at line 3604 of file stm32f407xx.h.
| #define FSMC_BCR4_WAITPOL 0x00000200U |
Wait signal polarity bit
Definition at line 3600 of file stm32f407xx.h.
| #define FSMC_BCR4_WRAPMOD 0x00000400U |
Wrapped burst mode support
Definition at line 3601 of file stm32f407xx.h.
| #define FSMC_BCR4_WREN 0x00001000U |
Write enable bit
Definition at line 3603 of file stm32f407xx.h.
| #define FSMC_BTR1_ACCMOD 0x30000000U |
ACCMOD[1:0] bits (Access mode)
Definition at line 3654 of file stm32f407xx.h.
| #define FSMC_BTR1_ACCMOD_0 0x10000000U |
Bit 0
Definition at line 3655 of file stm32f407xx.h.
| #define FSMC_BTR1_ACCMOD_1 0x20000000U |
Bit 1
Definition at line 3656 of file stm32f407xx.h.
| #define FSMC_BTR1_ADDHLD 0x000000F0U |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3620 of file stm32f407xx.h.
| #define FSMC_BTR1_ADDHLD_0 0x00000010U |
Bit 0
Definition at line 3621 of file stm32f407xx.h.
| #define FSMC_BTR1_ADDHLD_1 0x00000020U |
Bit 1
Definition at line 3622 of file stm32f407xx.h.
| #define FSMC_BTR1_ADDHLD_2 0x00000040U |
Bit 2
Definition at line 3623 of file stm32f407xx.h.
| #define FSMC_BTR1_ADDHLD_3 0x00000080U |
Bit 3
Definition at line 3624 of file stm32f407xx.h.
| #define FSMC_BTR1_ADDSET 0x0000000FU |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3614 of file stm32f407xx.h.
| #define FSMC_BTR1_ADDSET_0 0x00000001U |
Bit 0
Definition at line 3615 of file stm32f407xx.h.
| #define FSMC_BTR1_ADDSET_1 0x00000002U |
Bit 1
Definition at line 3616 of file stm32f407xx.h.
| #define FSMC_BTR1_ADDSET_2 0x00000004U |
Bit 2
Definition at line 3617 of file stm32f407xx.h.
| #define FSMC_BTR1_ADDSET_3 0x00000008U |
Bit 3
Definition at line 3618 of file stm32f407xx.h.
| #define FSMC_BTR1_BUSTURN 0x000F0000U |
BUSTURN[3:0] bits (Bus turnaround phase duration)
Definition at line 3636 of file stm32f407xx.h.
| #define FSMC_BTR1_BUSTURN_0 0x00010000U |
Bit 0
Definition at line 3637 of file stm32f407xx.h.
| #define FSMC_BTR1_BUSTURN_1 0x00020000U |
Bit 1
Definition at line 3638 of file stm32f407xx.h.
| #define FSMC_BTR1_BUSTURN_2 0x00040000U |
Bit 2
Definition at line 3639 of file stm32f407xx.h.
| #define FSMC_BTR1_BUSTURN_3 0x00080000U |
Bit 3
Definition at line 3640 of file stm32f407xx.h.
| #define FSMC_BTR1_CLKDIV 0x00F00000U |
CLKDIV[3:0] bits (Clock divide ratio)
Definition at line 3642 of file stm32f407xx.h.
| #define FSMC_BTR1_CLKDIV_0 0x00100000U |
Bit 0
Definition at line 3643 of file stm32f407xx.h.
| #define FSMC_BTR1_CLKDIV_1 0x00200000U |
Bit 1
Definition at line 3644 of file stm32f407xx.h.
| #define FSMC_BTR1_CLKDIV_2 0x00400000U |
Bit 2
Definition at line 3645 of file stm32f407xx.h.
| #define FSMC_BTR1_CLKDIV_3 0x00800000U |
Bit 3
Definition at line 3646 of file stm32f407xx.h.
| #define FSMC_BTR1_DATAST 0x0000FF00U |
DATAST [7:0] bits (Data-phase duration)
Definition at line 3626 of file stm32f407xx.h.
| #define FSMC_BTR1_DATAST_0 0x00000100U |
Bit 0
Definition at line 3627 of file stm32f407xx.h.
| #define FSMC_BTR1_DATAST_1 0x00000200U |
Bit 1
Definition at line 3628 of file stm32f407xx.h.
| #define FSMC_BTR1_DATAST_2 0x00000400U |
Bit 2
Definition at line 3629 of file stm32f407xx.h.
| #define FSMC_BTR1_DATAST_3 0x00000800U |
Bit 3
Definition at line 3630 of file stm32f407xx.h.
| #define FSMC_BTR1_DATAST_4 0x00001000U |
Bit 4
Definition at line 3631 of file stm32f407xx.h.
| #define FSMC_BTR1_DATAST_5 0x00002000U |
Bit 5
Definition at line 3632 of file stm32f407xx.h.
| #define FSMC_BTR1_DATAST_6 0x00004000U |
Bit 6
Definition at line 3633 of file stm32f407xx.h.
| #define FSMC_BTR1_DATAST_7 0x00008000U |
Bit 7
Definition at line 3634 of file stm32f407xx.h.
| #define FSMC_BTR1_DATLAT 0x0F000000U |
DATLA[3:0] bits (Data latency)
Definition at line 3648 of file stm32f407xx.h.
| #define FSMC_BTR1_DATLAT_0 0x01000000U |
Bit 0
Definition at line 3649 of file stm32f407xx.h.
| #define FSMC_BTR1_DATLAT_1 0x02000000U |
Bit 1
Definition at line 3650 of file stm32f407xx.h.
| #define FSMC_BTR1_DATLAT_2 0x04000000U |
Bit 2
Definition at line 3651 of file stm32f407xx.h.
| #define FSMC_BTR1_DATLAT_3 0x08000000U |
Bit 3
Definition at line 3652 of file stm32f407xx.h.
| #define FSMC_BTR2_ACCMOD 0x30000000U |
ACCMOD[1:0] bits (Access mode)
Definition at line 3699 of file stm32f407xx.h.
| #define FSMC_BTR2_ACCMOD_0 0x10000000U |
Bit 0
Definition at line 3700 of file stm32f407xx.h.
| #define FSMC_BTR2_ACCMOD_1 0x20000000U |
Bit 1
Definition at line 3701 of file stm32f407xx.h.
| #define FSMC_BTR2_ADDHLD 0x000000F0U |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3665 of file stm32f407xx.h.
| #define FSMC_BTR2_ADDHLD_0 0x00000010U |
Bit 0
Definition at line 3666 of file stm32f407xx.h.
| #define FSMC_BTR2_ADDHLD_1 0x00000020U |
Bit 1
Definition at line 3667 of file stm32f407xx.h.
| #define FSMC_BTR2_ADDHLD_2 0x00000040U |
Bit 2
Definition at line 3668 of file stm32f407xx.h.
| #define FSMC_BTR2_ADDHLD_3 0x00000080U |
Bit 3
Definition at line 3669 of file stm32f407xx.h.
| #define FSMC_BTR2_ADDSET 0x0000000FU |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3659 of file stm32f407xx.h.
| #define FSMC_BTR2_ADDSET_0 0x00000001U |
Bit 0
Definition at line 3660 of file stm32f407xx.h.
| #define FSMC_BTR2_ADDSET_1 0x00000002U |
Bit 1
Definition at line 3661 of file stm32f407xx.h.
| #define FSMC_BTR2_ADDSET_2 0x00000004U |
Bit 2
Definition at line 3662 of file stm32f407xx.h.
| #define FSMC_BTR2_ADDSET_3 0x00000008U |
Bit 3
Definition at line 3663 of file stm32f407xx.h.
| #define FSMC_BTR2_BUSTURN 0x000F0000U |
BUSTURN[3:0] bits (Bus turnaround phase duration)
Definition at line 3681 of file stm32f407xx.h.
| #define FSMC_BTR2_BUSTURN_0 0x00010000U |
Bit 0
Definition at line 3682 of file stm32f407xx.h.
| #define FSMC_BTR2_BUSTURN_1 0x00020000U |
Bit 1
Definition at line 3683 of file stm32f407xx.h.
| #define FSMC_BTR2_BUSTURN_2 0x00040000U |
Bit 2
Definition at line 3684 of file stm32f407xx.h.
| #define FSMC_BTR2_BUSTURN_3 0x00080000U |
Bit 3
Definition at line 3685 of file stm32f407xx.h.
| #define FSMC_BTR2_CLKDIV 0x00F00000U |
CLKDIV[3:0] bits (Clock divide ratio)
Definition at line 3687 of file stm32f407xx.h.
| #define FSMC_BTR2_CLKDIV_0 0x00100000U |
Bit 0
Definition at line 3688 of file stm32f407xx.h.
| #define FSMC_BTR2_CLKDIV_1 0x00200000U |
Bit 1
Definition at line 3689 of file stm32f407xx.h.
| #define FSMC_BTR2_CLKDIV_2 0x00400000U |
Bit 2
Definition at line 3690 of file stm32f407xx.h.
| #define FSMC_BTR2_CLKDIV_3 0x00800000U |
Bit 3
Definition at line 3691 of file stm32f407xx.h.
| #define FSMC_BTR2_DATAST 0x0000FF00U |
DATAST [7:0] bits (Data-phase duration)
Definition at line 3671 of file stm32f407xx.h.
| #define FSMC_BTR2_DATAST_0 0x00000100U |
Bit 0
Definition at line 3672 of file stm32f407xx.h.
| #define FSMC_BTR2_DATAST_1 0x00000200U |
Bit 1
Definition at line 3673 of file stm32f407xx.h.
| #define FSMC_BTR2_DATAST_2 0x00000400U |
Bit 2
Definition at line 3674 of file stm32f407xx.h.
| #define FSMC_BTR2_DATAST_3 0x00000800U |
Bit 3
Definition at line 3675 of file stm32f407xx.h.
| #define FSMC_BTR2_DATAST_4 0x00001000U |
Bit 4
Definition at line 3676 of file stm32f407xx.h.
| #define FSMC_BTR2_DATAST_5 0x00002000U |
Bit 5
Definition at line 3677 of file stm32f407xx.h.
| #define FSMC_BTR2_DATAST_6 0x00004000U |
Bit 6
Definition at line 3678 of file stm32f407xx.h.
| #define FSMC_BTR2_DATAST_7 0x00008000U |
Bit 7
Definition at line 3679 of file stm32f407xx.h.
| #define FSMC_BTR2_DATLAT 0x0F000000U |
DATLA[3:0] bits (Data latency)
Definition at line 3693 of file stm32f407xx.h.
| #define FSMC_BTR2_DATLAT_0 0x01000000U |
Bit 0
Definition at line 3694 of file stm32f407xx.h.
| #define FSMC_BTR2_DATLAT_1 0x02000000U |
Bit 1
Definition at line 3695 of file stm32f407xx.h.
| #define FSMC_BTR2_DATLAT_2 0x04000000U |
Bit 2
Definition at line 3696 of file stm32f407xx.h.
| #define FSMC_BTR2_DATLAT_3 0x08000000U |
Bit 3
Definition at line 3697 of file stm32f407xx.h.
| #define FSMC_BTR3_ACCMOD 0x30000000U |
ACCMOD[1:0] bits (Access mode)
Definition at line 3744 of file stm32f407xx.h.
| #define FSMC_BTR3_ACCMOD_0 0x10000000U |
Bit 0
Definition at line 3745 of file stm32f407xx.h.
| #define FSMC_BTR3_ACCMOD_1 0x20000000U |
Bit 1
Definition at line 3746 of file stm32f407xx.h.
| #define FSMC_BTR3_ADDHLD 0x000000F0U |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3710 of file stm32f407xx.h.
| #define FSMC_BTR3_ADDHLD_0 0x00000010U |
Bit 0
Definition at line 3711 of file stm32f407xx.h.
| #define FSMC_BTR3_ADDHLD_1 0x00000020U |
Bit 1
Definition at line 3712 of file stm32f407xx.h.
| #define FSMC_BTR3_ADDHLD_2 0x00000040U |
Bit 2
Definition at line 3713 of file stm32f407xx.h.
| #define FSMC_BTR3_ADDHLD_3 0x00000080U |
Bit 3
Definition at line 3714 of file stm32f407xx.h.
| #define FSMC_BTR3_ADDSET 0x0000000FU |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3704 of file stm32f407xx.h.
| #define FSMC_BTR3_ADDSET_0 0x00000001U |
Bit 0
Definition at line 3705 of file stm32f407xx.h.
| #define FSMC_BTR3_ADDSET_1 0x00000002U |
Bit 1
Definition at line 3706 of file stm32f407xx.h.
| #define FSMC_BTR3_ADDSET_2 0x00000004U |
Bit 2
Definition at line 3707 of file stm32f407xx.h.
| #define FSMC_BTR3_ADDSET_3 0x00000008U |
Bit 3
Definition at line 3708 of file stm32f407xx.h.
| #define FSMC_BTR3_BUSTURN 0x000F0000U |
BUSTURN[3:0] bits (Bus turnaround phase duration)
Definition at line 3726 of file stm32f407xx.h.
| #define FSMC_BTR3_BUSTURN_0 0x00010000U |
Bit 0
Definition at line 3727 of file stm32f407xx.h.
| #define FSMC_BTR3_BUSTURN_1 0x00020000U |
Bit 1
Definition at line 3728 of file stm32f407xx.h.
| #define FSMC_BTR3_BUSTURN_2 0x00040000U |
Bit 2
Definition at line 3729 of file stm32f407xx.h.
| #define FSMC_BTR3_BUSTURN_3 0x00080000U |
Bit 3
Definition at line 3730 of file stm32f407xx.h.
| #define FSMC_BTR3_CLKDIV 0x00F00000U |
CLKDIV[3:0] bits (Clock divide ratio)
Definition at line 3732 of file stm32f407xx.h.
| #define FSMC_BTR3_CLKDIV_0 0x00100000U |
Bit 0
Definition at line 3733 of file stm32f407xx.h.
| #define FSMC_BTR3_CLKDIV_1 0x00200000U |
Bit 1
Definition at line 3734 of file stm32f407xx.h.
| #define FSMC_BTR3_CLKDIV_2 0x00400000U |
Bit 2
Definition at line 3735 of file stm32f407xx.h.
| #define FSMC_BTR3_CLKDIV_3 0x00800000U |
Bit 3
Definition at line 3736 of file stm32f407xx.h.
| #define FSMC_BTR3_DATAST 0x0000FF00U |
DATAST [7:0] bits (Data-phase duration)
Definition at line 3716 of file stm32f407xx.h.
| #define FSMC_BTR3_DATAST_0 0x00000100U |
Bit 0
Definition at line 3717 of file stm32f407xx.h.
| #define FSMC_BTR3_DATAST_1 0x00000200U |
Bit 1
Definition at line 3718 of file stm32f407xx.h.
| #define FSMC_BTR3_DATAST_2 0x00000400U |
Bit 2
Definition at line 3719 of file stm32f407xx.h.
| #define FSMC_BTR3_DATAST_3 0x00000800U |
Bit 3
Definition at line 3720 of file stm32f407xx.h.
| #define FSMC_BTR3_DATAST_4 0x00001000U |
Bit 4
Definition at line 3721 of file stm32f407xx.h.
| #define FSMC_BTR3_DATAST_5 0x00002000U |
Bit 5
Definition at line 3722 of file stm32f407xx.h.
| #define FSMC_BTR3_DATAST_6 0x00004000U |
Bit 6
Definition at line 3723 of file stm32f407xx.h.
| #define FSMC_BTR3_DATAST_7 0x00008000U |
Bit 7
Definition at line 3724 of file stm32f407xx.h.
| #define FSMC_BTR3_DATLAT 0x0F000000U |
DATLA[3:0] bits (Data latency)
Definition at line 3738 of file stm32f407xx.h.
| #define FSMC_BTR3_DATLAT_0 0x01000000U |
Bit 0
Definition at line 3739 of file stm32f407xx.h.
| #define FSMC_BTR3_DATLAT_1 0x02000000U |
Bit 1
Definition at line 3740 of file stm32f407xx.h.
| #define FSMC_BTR3_DATLAT_2 0x04000000U |
Bit 2
Definition at line 3741 of file stm32f407xx.h.
| #define FSMC_BTR3_DATLAT_3 0x08000000U |
Bit 3
Definition at line 3742 of file stm32f407xx.h.
| #define FSMC_BTR4_ACCMOD 0x30000000U |
ACCMOD[1:0] bits (Access mode)
Definition at line 3789 of file stm32f407xx.h.
| #define FSMC_BTR4_ACCMOD_0 0x10000000U |
Bit 0
Definition at line 3790 of file stm32f407xx.h.
| #define FSMC_BTR4_ACCMOD_1 0x20000000U |
Bit 1
Definition at line 3791 of file stm32f407xx.h.
| #define FSMC_BTR4_ADDHLD 0x000000F0U |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3755 of file stm32f407xx.h.
| #define FSMC_BTR4_ADDHLD_0 0x00000010U |
Bit 0
Definition at line 3756 of file stm32f407xx.h.
| #define FSMC_BTR4_ADDHLD_1 0x00000020U |
Bit 1
Definition at line 3757 of file stm32f407xx.h.
| #define FSMC_BTR4_ADDHLD_2 0x00000040U |
Bit 2
Definition at line 3758 of file stm32f407xx.h.
| #define FSMC_BTR4_ADDHLD_3 0x00000080U |
Bit 3
Definition at line 3759 of file stm32f407xx.h.
| #define FSMC_BTR4_ADDSET 0x0000000FU |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3749 of file stm32f407xx.h.
| #define FSMC_BTR4_ADDSET_0 0x00000001U |
Bit 0
Definition at line 3750 of file stm32f407xx.h.
| #define FSMC_BTR4_ADDSET_1 0x00000002U |
Bit 1
Definition at line 3751 of file stm32f407xx.h.
| #define FSMC_BTR4_ADDSET_2 0x00000004U |
Bit 2
Definition at line 3752 of file stm32f407xx.h.
| #define FSMC_BTR4_ADDSET_3 0x00000008U |
Bit 3
Definition at line 3753 of file stm32f407xx.h.
| #define FSMC_BTR4_BUSTURN 0x000F0000U |
BUSTURN[3:0] bits (Bus turnaround phase duration)
Definition at line 3771 of file stm32f407xx.h.
| #define FSMC_BTR4_BUSTURN_0 0x00010000U |
Bit 0
Definition at line 3772 of file stm32f407xx.h.
| #define FSMC_BTR4_BUSTURN_1 0x00020000U |
Bit 1
Definition at line 3773 of file stm32f407xx.h.
| #define FSMC_BTR4_BUSTURN_2 0x00040000U |
Bit 2
Definition at line 3774 of file stm32f407xx.h.
| #define FSMC_BTR4_BUSTURN_3 0x00080000U |
Bit 3
Definition at line 3775 of file stm32f407xx.h.
| #define FSMC_BTR4_CLKDIV 0x00F00000U |
CLKDIV[3:0] bits (Clock divide ratio)
Definition at line 3777 of file stm32f407xx.h.
| #define FSMC_BTR4_CLKDIV_0 0x00100000U |
Bit 0
Definition at line 3778 of file stm32f407xx.h.
| #define FSMC_BTR4_CLKDIV_1 0x00200000U |
Bit 1
Definition at line 3779 of file stm32f407xx.h.
| #define FSMC_BTR4_CLKDIV_2 0x00400000U |
Bit 2
Definition at line 3780 of file stm32f407xx.h.
| #define FSMC_BTR4_CLKDIV_3 0x00800000U |
Bit 3
Definition at line 3781 of file stm32f407xx.h.
| #define FSMC_BTR4_DATAST 0x0000FF00U |
DATAST [3:0] bits (Data-phase duration)
Definition at line 3761 of file stm32f407xx.h.
| #define FSMC_BTR4_DATAST_0 0x00000100U |
Bit 0
Definition at line 3762 of file stm32f407xx.h.
| #define FSMC_BTR4_DATAST_1 0x00000200U |
Bit 1
Definition at line 3763 of file stm32f407xx.h.
| #define FSMC_BTR4_DATAST_2 0x00000400U |
Bit 2
Definition at line 3764 of file stm32f407xx.h.
| #define FSMC_BTR4_DATAST_3 0x00000800U |
Bit 3
Definition at line 3765 of file stm32f407xx.h.
| #define FSMC_BTR4_DATAST_4 0x00001000U |
Bit 4
Definition at line 3766 of file stm32f407xx.h.
| #define FSMC_BTR4_DATAST_5 0x00002000U |
Bit 5
Definition at line 3767 of file stm32f407xx.h.
| #define FSMC_BTR4_DATAST_6 0x00004000U |
Bit 6
Definition at line 3768 of file stm32f407xx.h.
| #define FSMC_BTR4_DATAST_7 0x00008000U |
Bit 7
Definition at line 3769 of file stm32f407xx.h.
| #define FSMC_BTR4_DATLAT 0x0F000000U |
DATLA[3:0] bits (Data latency)
Definition at line 3783 of file stm32f407xx.h.
| #define FSMC_BTR4_DATLAT_0 0x01000000U |
Bit 0
Definition at line 3784 of file stm32f407xx.h.
| #define FSMC_BTR4_DATLAT_1 0x02000000U |
Bit 1
Definition at line 3785 of file stm32f407xx.h.
| #define FSMC_BTR4_DATLAT_2 0x04000000U |
Bit 2
Definition at line 3786 of file stm32f407xx.h.
| #define FSMC_BTR4_DATLAT_3 0x08000000U |
Bit 3
Definition at line 3787 of file stm32f407xx.h.
| #define FSMC_BWTR1_ACCMOD 0x30000000U |
ACCMOD[1:0] bits (Access mode)
Definition at line 3822 of file stm32f407xx.h.
| #define FSMC_BWTR1_ACCMOD_0 0x10000000U |
Bit 0
Definition at line 3823 of file stm32f407xx.h.
| #define FSMC_BWTR1_ACCMOD_1 0x20000000U |
Bit 1
Definition at line 3824 of file stm32f407xx.h.
| #define FSMC_BWTR1_ADDHLD 0x000000F0U |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3800 of file stm32f407xx.h.
| #define FSMC_BWTR1_ADDHLD_0 0x00000010U |
Bit 0
Definition at line 3801 of file stm32f407xx.h.
| #define FSMC_BWTR1_ADDHLD_1 0x00000020U |
Bit 1
Definition at line 3802 of file stm32f407xx.h.
| #define FSMC_BWTR1_ADDHLD_2 0x00000040U |
Bit 2
Definition at line 3803 of file stm32f407xx.h.
| #define FSMC_BWTR1_ADDHLD_3 0x00000080U |
Bit 3
Definition at line 3804 of file stm32f407xx.h.
| #define FSMC_BWTR1_ADDSET 0x0000000FU |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3794 of file stm32f407xx.h.
| #define FSMC_BWTR1_ADDSET_0 0x00000001U |
Bit 0
Definition at line 3795 of file stm32f407xx.h.
| #define FSMC_BWTR1_ADDSET_1 0x00000002U |
Bit 1
Definition at line 3796 of file stm32f407xx.h.
| #define FSMC_BWTR1_ADDSET_2 0x00000004U |
Bit 2
Definition at line 3797 of file stm32f407xx.h.
| #define FSMC_BWTR1_ADDSET_3 0x00000008U |
Bit 3
Definition at line 3798 of file stm32f407xx.h.
| #define FSMC_BWTR1_BUSTURN 0x000F0000U |
BUSTURN[3:0] bits (Bus turnaround duration)
Definition at line 3816 of file stm32f407xx.h.
| #define FSMC_BWTR1_BUSTURN_0 0x00010000U |
Bit 0
Definition at line 3817 of file stm32f407xx.h.
| #define FSMC_BWTR1_BUSTURN_1 0x00020000U |
Bit 1
Definition at line 3818 of file stm32f407xx.h.
| #define FSMC_BWTR1_BUSTURN_2 0x00040000U |
Bit 2
Definition at line 3819 of file stm32f407xx.h.
| #define FSMC_BWTR1_BUSTURN_3 0x00080000U |
Bit 3
Definition at line 3820 of file stm32f407xx.h.
| #define FSMC_BWTR1_DATAST 0x0000FF00U |
DATAST [7:0] bits (Data-phase duration)
Definition at line 3806 of file stm32f407xx.h.
| #define FSMC_BWTR1_DATAST_0 0x00000100U |
Bit 0
Definition at line 3807 of file stm32f407xx.h.
| #define FSMC_BWTR1_DATAST_1 0x00000200U |
Bit 1
Definition at line 3808 of file stm32f407xx.h.
| #define FSMC_BWTR1_DATAST_2 0x00000400U |
Bit 2
Definition at line 3809 of file stm32f407xx.h.
| #define FSMC_BWTR1_DATAST_3 0x00000800U |
Bit 3
Definition at line 3810 of file stm32f407xx.h.
| #define FSMC_BWTR1_DATAST_4 0x00001000U |
Bit 4
Definition at line 3811 of file stm32f407xx.h.
| #define FSMC_BWTR1_DATAST_5 0x00002000U |
Bit 5
Definition at line 3812 of file stm32f407xx.h.
| #define FSMC_BWTR1_DATAST_6 0x00004000U |
Bit 6
Definition at line 3813 of file stm32f407xx.h.
| #define FSMC_BWTR1_DATAST_7 0x00008000U |
Bit 7
Definition at line 3814 of file stm32f407xx.h.
| #define FSMC_BWTR2_ACCMOD 0x30000000U |
ACCMOD[1:0] bits (Access mode)
Definition at line 3855 of file stm32f407xx.h.
| #define FSMC_BWTR2_ACCMOD_0 0x10000000U |
Bit 0
Definition at line 3856 of file stm32f407xx.h.
| #define FSMC_BWTR2_ACCMOD_1 0x20000000U |
Bit 1
Definition at line 3857 of file stm32f407xx.h.
| #define FSMC_BWTR2_ADDHLD 0x000000F0U |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3833 of file stm32f407xx.h.
| #define FSMC_BWTR2_ADDHLD_0 0x00000010U |
Bit 0
Definition at line 3834 of file stm32f407xx.h.
| #define FSMC_BWTR2_ADDHLD_1 0x00000020U |
Bit 1
Definition at line 3835 of file stm32f407xx.h.
| #define FSMC_BWTR2_ADDHLD_2 0x00000040U |
Bit 2
Definition at line 3836 of file stm32f407xx.h.
| #define FSMC_BWTR2_ADDHLD_3 0x00000080U |
Bit 3
Definition at line 3837 of file stm32f407xx.h.
| #define FSMC_BWTR2_ADDSET 0x0000000FU |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3827 of file stm32f407xx.h.
| #define FSMC_BWTR2_ADDSET_0 0x00000001U |
Bit 0
Definition at line 3828 of file stm32f407xx.h.
| #define FSMC_BWTR2_ADDSET_1 0x00000002U |
Bit 1
Definition at line 3829 of file stm32f407xx.h.
| #define FSMC_BWTR2_ADDSET_2 0x00000004U |
Bit 2
Definition at line 3830 of file stm32f407xx.h.
| #define FSMC_BWTR2_ADDSET_3 0x00000008U |
Bit 3
Definition at line 3831 of file stm32f407xx.h.
| #define FSMC_BWTR2_BUSTURN 0x000F0000U |
BUSTURN[3:0] bits (Bus turnaround duration)
Definition at line 3849 of file stm32f407xx.h.
| #define FSMC_BWTR2_BUSTURN_0 0x00010000U |
Bit 0
Definition at line 3850 of file stm32f407xx.h.
| #define FSMC_BWTR2_BUSTURN_1 0x00020000U |
Bit 1
Definition at line 3851 of file stm32f407xx.h.
| #define FSMC_BWTR2_BUSTURN_2 0x00040000U |
Bit 2
Definition at line 3852 of file stm32f407xx.h.
| #define FSMC_BWTR2_BUSTURN_3 0x00080000U |
Bit 3
Definition at line 3853 of file stm32f407xx.h.
| #define FSMC_BWTR2_DATAST 0x0000FF00U |
DATAST [7:0] bits (Data-phase duration)
Definition at line 3839 of file stm32f407xx.h.
| #define FSMC_BWTR2_DATAST_0 0x00000100U |
Bit 0
Definition at line 3840 of file stm32f407xx.h.
| #define FSMC_BWTR2_DATAST_1 0x00000200U |
Bit 1
Definition at line 3841 of file stm32f407xx.h.
| #define FSMC_BWTR2_DATAST_2 0x00000400U |
Bit 2
Definition at line 3842 of file stm32f407xx.h.
| #define FSMC_BWTR2_DATAST_3 0x00000800U |
Bit 3
Definition at line 3843 of file stm32f407xx.h.
| #define FSMC_BWTR2_DATAST_4 0x00001000U |
Bit 4
Definition at line 3844 of file stm32f407xx.h.
| #define FSMC_BWTR2_DATAST_5 0x00002000U |
Bit 5
Definition at line 3845 of file stm32f407xx.h.
| #define FSMC_BWTR2_DATAST_6 0x00004000U |
Bit 6
Definition at line 3846 of file stm32f407xx.h.
| #define FSMC_BWTR2_DATAST_7 0x00008000U |
Bit 7
Definition at line 3847 of file stm32f407xx.h.
| #define FSMC_BWTR3_ACCMOD 0x30000000U |
ACCMOD[1:0] bits (Access mode)
Definition at line 3888 of file stm32f407xx.h.
| #define FSMC_BWTR3_ACCMOD_0 0x10000000U |
Bit 0
Definition at line 3889 of file stm32f407xx.h.
| #define FSMC_BWTR3_ACCMOD_1 0x20000000U |
Bit 1
Definition at line 3890 of file stm32f407xx.h.
| #define FSMC_BWTR3_ADDHLD 0x000000F0U |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3866 of file stm32f407xx.h.
| #define FSMC_BWTR3_ADDHLD_0 0x00000010U |
Bit 0
Definition at line 3867 of file stm32f407xx.h.
| #define FSMC_BWTR3_ADDHLD_1 0x00000020U |
Bit 1
Definition at line 3868 of file stm32f407xx.h.
| #define FSMC_BWTR3_ADDHLD_2 0x00000040U |
Bit 2
Definition at line 3869 of file stm32f407xx.h.
| #define FSMC_BWTR3_ADDHLD_3 0x00000080U |
Bit 3
Definition at line 3870 of file stm32f407xx.h.
| #define FSMC_BWTR3_ADDSET 0x0000000FU |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3860 of file stm32f407xx.h.
| #define FSMC_BWTR3_ADDSET_0 0x00000001U |
Bit 0
Definition at line 3861 of file stm32f407xx.h.
| #define FSMC_BWTR3_ADDSET_1 0x00000002U |
Bit 1
Definition at line 3862 of file stm32f407xx.h.
| #define FSMC_BWTR3_ADDSET_2 0x00000004U |
Bit 2
Definition at line 3863 of file stm32f407xx.h.
| #define FSMC_BWTR3_ADDSET_3 0x00000008U |
Bit 3
Definition at line 3864 of file stm32f407xx.h.
| #define FSMC_BWTR3_BUSTURN 0x000F0000U |
BUSTURN[3:0] bits (Bus turnaround duration)
Definition at line 3882 of file stm32f407xx.h.
| #define FSMC_BWTR3_BUSTURN_0 0x00010000U |
Bit 0
Definition at line 3883 of file stm32f407xx.h.
| #define FSMC_BWTR3_BUSTURN_1 0x00020000U |
Bit 1
Definition at line 3884 of file stm32f407xx.h.
| #define FSMC_BWTR3_BUSTURN_2 0x00040000U |
Bit 2
Definition at line 3885 of file stm32f407xx.h.
| #define FSMC_BWTR3_BUSTURN_3 0x00080000U |
Bit 3
Definition at line 3886 of file stm32f407xx.h.
| #define FSMC_BWTR3_DATAST 0x0000FF00U |
DATAST [7:0] bits (Data-phase duration)
Definition at line 3872 of file stm32f407xx.h.
| #define FSMC_BWTR3_DATAST_0 0x00000100U |
Bit 0
Definition at line 3873 of file stm32f407xx.h.
| #define FSMC_BWTR3_DATAST_1 0x00000200U |
Bit 1
Definition at line 3874 of file stm32f407xx.h.
| #define FSMC_BWTR3_DATAST_2 0x00000400U |
Bit 2
Definition at line 3875 of file stm32f407xx.h.
| #define FSMC_BWTR3_DATAST_3 0x00000800U |
Bit 3
Definition at line 3876 of file stm32f407xx.h.
| #define FSMC_BWTR3_DATAST_4 0x00001000U |
Bit 4
Definition at line 3877 of file stm32f407xx.h.
| #define FSMC_BWTR3_DATAST_5 0x00002000U |
Bit 5
Definition at line 3878 of file stm32f407xx.h.
| #define FSMC_BWTR3_DATAST_6 0x00004000U |
Bit 6
Definition at line 3879 of file stm32f407xx.h.
| #define FSMC_BWTR3_DATAST_7 0x00008000U |
Bit 7
Definition at line 3880 of file stm32f407xx.h.
| #define FSMC_BWTR4_ACCMOD 0x30000000U |
ACCMOD[1:0] bits (Access mode)
Definition at line 3921 of file stm32f407xx.h.
| #define FSMC_BWTR4_ACCMOD_0 0x10000000U |
Bit 0
Definition at line 3922 of file stm32f407xx.h.
| #define FSMC_BWTR4_ACCMOD_1 0x20000000U |
Bit 1
Definition at line 3923 of file stm32f407xx.h.
| #define FSMC_BWTR4_ADDHLD 0x000000F0U |
ADDHLD[3:0] bits (Address-hold phase duration)
Definition at line 3899 of file stm32f407xx.h.
| #define FSMC_BWTR4_ADDHLD_0 0x00000010U |
Bit 0
Definition at line 3900 of file stm32f407xx.h.
| #define FSMC_BWTR4_ADDHLD_1 0x00000020U |
Bit 1
Definition at line 3901 of file stm32f407xx.h.
| #define FSMC_BWTR4_ADDHLD_2 0x00000040U |
Bit 2
Definition at line 3902 of file stm32f407xx.h.
| #define FSMC_BWTR4_ADDHLD_3 0x00000080U |
Bit 3
Definition at line 3903 of file stm32f407xx.h.
| #define FSMC_BWTR4_ADDSET 0x0000000FU |
ADDSET[3:0] bits (Address setup phase duration)
Definition at line 3893 of file stm32f407xx.h.
| #define FSMC_BWTR4_ADDSET_0 0x00000001U |
Bit 0
Definition at line 3894 of file stm32f407xx.h.
| #define FSMC_BWTR4_ADDSET_1 0x00000002U |
Bit 1
Definition at line 3895 of file stm32f407xx.h.
| #define FSMC_BWTR4_ADDSET_2 0x00000004U |
Bit 2
Definition at line 3896 of file stm32f407xx.h.
| #define FSMC_BWTR4_ADDSET_3 0x00000008U |
Bit 3
Definition at line 3897 of file stm32f407xx.h.
| #define FSMC_BWTR4_BUSTURN 0x000F0000U |
BUSTURN[3:0] bits (Bus turnaround duration)
Definition at line 3915 of file stm32f407xx.h.
| #define FSMC_BWTR4_BUSTURN_0 0x00010000U |
Bit 0
Definition at line 3916 of file stm32f407xx.h.
| #define FSMC_BWTR4_BUSTURN_1 0x00020000U |
Bit 1
Definition at line 3917 of file stm32f407xx.h.
| #define FSMC_BWTR4_BUSTURN_2 0x00040000U |
Bit 2
Definition at line 3918 of file stm32f407xx.h.
| #define FSMC_BWTR4_BUSTURN_3 0x00080000U |
Bit 3
Definition at line 3919 of file stm32f407xx.h.
| #define FSMC_BWTR4_DATAST 0x0000FF00U |
DATAST [3:0] bits (Data-phase duration)
Definition at line 3905 of file stm32f407xx.h.
| #define FSMC_BWTR4_DATAST_0 0x00000100U |
Bit 0
Definition at line 3906 of file stm32f407xx.h.
| #define FSMC_BWTR4_DATAST_1 0x00000200U |
Bit 1
Definition at line 3907 of file stm32f407xx.h.
| #define FSMC_BWTR4_DATAST_2 0x00000400U |
Bit 2
Definition at line 3908 of file stm32f407xx.h.
| #define FSMC_BWTR4_DATAST_3 0x00000800U |
Bit 3
Definition at line 3909 of file stm32f407xx.h.
| #define FSMC_BWTR4_DATAST_4 0x00001000U |
Bit 4
Definition at line 3910 of file stm32f407xx.h.
| #define FSMC_BWTR4_DATAST_5 0x00002000U |
Bit 5
Definition at line 3911 of file stm32f407xx.h.
| #define FSMC_BWTR4_DATAST_6 0x00004000U |
Bit 6
Definition at line 3912 of file stm32f407xx.h.
| #define FSMC_BWTR4_DATAST_7 0x00008000U |
Bit 7
Definition at line 3913 of file stm32f407xx.h.
| #define FSMC_ECCR2_ECC2 0xFFFFFFFFU |
ECC result
Definition at line 4324 of file stm32f407xx.h.
| #define FSMC_ECCR3_ECC3 0xFFFFFFFFU |
ECC result
Definition at line 4327 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHIZ2 0xFF000000U |
ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time)
Definition at line 4190 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHIZ2_0 0x01000000U |
Bit 0
Definition at line 4191 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHIZ2_1 0x02000000U |
Bit 1
Definition at line 4192 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHIZ2_2 0x04000000U |
Bit 2
Definition at line 4193 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHIZ2_3 0x08000000U |
Bit 3
Definition at line 4194 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHIZ2_4 0x10000000U |
Bit 4
Definition at line 4195 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHIZ2_5 0x20000000U |
Bit 5
Definition at line 4196 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHIZ2_6 0x40000000U |
Bit 6
Definition at line 4197 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHIZ2_7 0x80000000U |
Bit 7
Definition at line 4198 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHOLD2 0x00FF0000U |
ATTHOLD2[7:0] bits (Attribute memory 2 hold time)
Definition at line 4180 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHOLD2_0 0x00010000U |
Bit 0
Definition at line 4181 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHOLD2_1 0x00020000U |
Bit 1
Definition at line 4182 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHOLD2_2 0x00040000U |
Bit 2
Definition at line 4183 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHOLD2_3 0x00080000U |
Bit 3
Definition at line 4184 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHOLD2_4 0x00100000U |
Bit 4
Definition at line 4185 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHOLD2_5 0x00200000U |
Bit 5
Definition at line 4186 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHOLD2_6 0x00400000U |
Bit 6
Definition at line 4187 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTHOLD2_7 0x00800000U |
Bit 7
Definition at line 4188 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTSET2 0x000000FFU |
ATTSET2[7:0] bits (Attribute memory 2 setup time)
Definition at line 4160 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTSET2_0 0x00000001U |
Bit 0
Definition at line 4161 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTSET2_1 0x00000002U |
Bit 1
Definition at line 4162 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTSET2_2 0x00000004U |
Bit 2
Definition at line 4163 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTSET2_3 0x00000008U |
Bit 3
Definition at line 4164 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTSET2_4 0x00000010U |
Bit 4
Definition at line 4165 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTSET2_5 0x00000020U |
Bit 5
Definition at line 4166 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTSET2_6 0x00000040U |
Bit 6
Definition at line 4167 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTSET2_7 0x00000080U |
Bit 7
Definition at line 4168 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTWAIT2 0x0000FF00U |
ATTWAIT2[7:0] bits (Attribute memory 2 wait time)
Definition at line 4170 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTWAIT2_0 0x00000100U |
Bit 0
Definition at line 4171 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTWAIT2_1 0x00000200U |
Bit 1
Definition at line 4172 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTWAIT2_2 0x00000400U |
Bit 2
Definition at line 4173 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTWAIT2_3 0x00000800U |
Bit 3
Definition at line 4174 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTWAIT2_4 0x00001000U |
Bit 4
Definition at line 4175 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTWAIT2_5 0x00002000U |
Bit 5
Definition at line 4176 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTWAIT2_6 0x00004000U |
Bit 6
Definition at line 4177 of file stm32f407xx.h.
| #define FSMC_PATT2_ATTWAIT2_7 0x00008000U |
Bit 7
Definition at line 4178 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHIZ3 0xFF000000U |
ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time)
Definition at line 4231 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHIZ3_0 0x01000000U |
Bit 0
Definition at line 4232 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHIZ3_1 0x02000000U |
Bit 1
Definition at line 4233 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHIZ3_2 0x04000000U |
Bit 2
Definition at line 4234 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHIZ3_3 0x08000000U |
Bit 3
Definition at line 4235 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHIZ3_4 0x10000000U |
Bit 4
Definition at line 4236 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHIZ3_5 0x20000000U |
Bit 5
Definition at line 4237 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHIZ3_6 0x40000000U |
Bit 6
Definition at line 4238 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHIZ3_7 0x80000000U |
Bit 7
Definition at line 4239 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHOLD3 0x00FF0000U |
ATTHOLD3[7:0] bits (Attribute memory 3 hold time)
Definition at line 4221 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHOLD3_0 0x00010000U |
Bit 0
Definition at line 4222 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHOLD3_1 0x00020000U |
Bit 1
Definition at line 4223 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHOLD3_2 0x00040000U |
Bit 2
Definition at line 4224 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHOLD3_3 0x00080000U |
Bit 3
Definition at line 4225 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHOLD3_4 0x00100000U |
Bit 4
Definition at line 4226 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHOLD3_5 0x00200000U |
Bit 5
Definition at line 4227 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHOLD3_6 0x00400000U |
Bit 6
Definition at line 4228 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTHOLD3_7 0x00800000U |
Bit 7
Definition at line 4229 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTSET3 0x000000FFU |
ATTSET3[7:0] bits (Attribute memory 3 setup time)
Definition at line 4201 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTSET3_0 0x00000001U |
Bit 0
Definition at line 4202 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTSET3_1 0x00000002U |
Bit 1
Definition at line 4203 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTSET3_2 0x00000004U |
Bit 2
Definition at line 4204 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTSET3_3 0x00000008U |
Bit 3
Definition at line 4205 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTSET3_4 0x00000010U |
Bit 4
Definition at line 4206 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTSET3_5 0x00000020U |
Bit 5
Definition at line 4207 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTSET3_6 0x00000040U |
Bit 6
Definition at line 4208 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTSET3_7 0x00000080U |
Bit 7
Definition at line 4209 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTWAIT3 0x0000FF00U |
ATTWAIT3[7:0] bits (Attribute memory 3 wait time)
Definition at line 4211 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTWAIT3_0 0x00000100U |
Bit 0
Definition at line 4212 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTWAIT3_1 0x00000200U |
Bit 1
Definition at line 4213 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTWAIT3_2 0x00000400U |
Bit 2
Definition at line 4214 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTWAIT3_3 0x00000800U |
Bit 3
Definition at line 4215 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTWAIT3_4 0x00001000U |
Bit 4
Definition at line 4216 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTWAIT3_5 0x00002000U |
Bit 5
Definition at line 4217 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTWAIT3_6 0x00004000U |
Bit 6
Definition at line 4218 of file stm32f407xx.h.
| #define FSMC_PATT3_ATTWAIT3_7 0x00008000U |
Bit 7
Definition at line 4219 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHIZ4 0xFF000000U |
ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time)
Definition at line 4272 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHIZ4_0 0x01000000U |
Bit 0
Definition at line 4273 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHIZ4_1 0x02000000U |
Bit 1
Definition at line 4274 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHIZ4_2 0x04000000U |
Bit 2
Definition at line 4275 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHIZ4_3 0x08000000U |
Bit 3
Definition at line 4276 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHIZ4_4 0x10000000U |
Bit 4
Definition at line 4277 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHIZ4_5 0x20000000U |
Bit 5
Definition at line 4278 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHIZ4_6 0x40000000U |
Bit 6
Definition at line 4279 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHIZ4_7 0x80000000U |
Bit 7
Definition at line 4280 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHOLD4 0x00FF0000U |
ATTHOLD4[7:0] bits (Attribute memory 4 hold time)
Definition at line 4262 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHOLD4_0 0x00010000U |
Bit 0
Definition at line 4263 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHOLD4_1 0x00020000U |
Bit 1
Definition at line 4264 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHOLD4_2 0x00040000U |
Bit 2
Definition at line 4265 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHOLD4_3 0x00080000U |
Bit 3
Definition at line 4266 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHOLD4_4 0x00100000U |
Bit 4
Definition at line 4267 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHOLD4_5 0x00200000U |
Bit 5
Definition at line 4268 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHOLD4_6 0x00400000U |
Bit 6
Definition at line 4269 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTHOLD4_7 0x00800000U |
Bit 7
Definition at line 4270 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTSET4 0x000000FFU |
ATTSET4[7:0] bits (Attribute memory 4 setup time)
Definition at line 4242 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTSET4_0 0x00000001U |
Bit 0
Definition at line 4243 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTSET4_1 0x00000002U |
Bit 1
Definition at line 4244 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTSET4_2 0x00000004U |
Bit 2
Definition at line 4245 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTSET4_3 0x00000008U |
Bit 3
Definition at line 4246 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTSET4_4 0x00000010U |
Bit 4
Definition at line 4247 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTSET4_5 0x00000020U |
Bit 5
Definition at line 4248 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTSET4_6 0x00000040U |
Bit 6
Definition at line 4249 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTSET4_7 0x00000080U |
Bit 7
Definition at line 4250 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTWAIT4 0x0000FF00U |
ATTWAIT4[7:0] bits (Attribute memory 4 wait time)
Definition at line 4252 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTWAIT4_0 0x00000100U |
Bit 0
Definition at line 4253 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTWAIT4_1 0x00000200U |
Bit 1
Definition at line 4254 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTWAIT4_2 0x00000400U |
Bit 2
Definition at line 4255 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTWAIT4_3 0x00000800U |
Bit 3
Definition at line 4256 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTWAIT4_4 0x00001000U |
Bit 4
Definition at line 4257 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTWAIT4_5 0x00002000U |
Bit 5
Definition at line 4258 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTWAIT4_6 0x00004000U |
Bit 6
Definition at line 4259 of file stm32f407xx.h.
| #define FSMC_PATT4_ATTWAIT4_7 0x00008000U |
Bit 7
Definition at line 4260 of file stm32f407xx.h.
| #define FSMC_PCR2_ECCEN 0x00000040U |
ECC computation logic enable bit
Definition at line 3934 of file stm32f407xx.h.
| #define FSMC_PCR2_ECCPS 0x000E0000U |
ECCPS[1:0] bits (ECC page size)
Definition at line 3948 of file stm32f407xx.h.
| #define FSMC_PCR2_ECCPS_0 0x00020000U |
Bit 0
Definition at line 3949 of file stm32f407xx.h.
| #define FSMC_PCR2_ECCPS_1 0x00040000U |
Bit 1
Definition at line 3950 of file stm32f407xx.h.
| #define FSMC_PCR2_ECCPS_2 0x00080000U |
Bit 2
Definition at line 3951 of file stm32f407xx.h.
| #define FSMC_PCR2_PBKEN 0x00000004U |
PC Card/NAND Flash memory bank enable bit
Definition at line 3927 of file stm32f407xx.h.
| #define FSMC_PCR2_PTYP 0x00000008U |
Memory type
Definition at line 3928 of file stm32f407xx.h.
| #define FSMC_PCR2_PWAITEN 0x00000002U |
Wait feature enable bit
Definition at line 3926 of file stm32f407xx.h.
| #define FSMC_PCR2_PWID 0x00000030U |
PWID[1:0] bits (NAND Flash databus width)
Definition at line 3930 of file stm32f407xx.h.
| #define FSMC_PCR2_PWID_0 0x00000010U |
Bit 0
Definition at line 3931 of file stm32f407xx.h.
| #define FSMC_PCR2_PWID_1 0x00000020U |
Bit 1
Definition at line 3932 of file stm32f407xx.h.
| #define FSMC_PCR2_TAR 0x0001E000U |
TAR[3:0] bits (ALE to RE delay)
Definition at line 3942 of file stm32f407xx.h.
| #define FSMC_PCR2_TAR_0 0x00002000U |
Bit 0
Definition at line 3943 of file stm32f407xx.h.
| #define FSMC_PCR2_TAR_1 0x00004000U |
Bit 1
Definition at line 3944 of file stm32f407xx.h.
| #define FSMC_PCR2_TAR_2 0x00008000U |
Bit 2
Definition at line 3945 of file stm32f407xx.h.
| #define FSMC_PCR2_TAR_3 0x00010000U |
Bit 3
Definition at line 3946 of file stm32f407xx.h.
| #define FSMC_PCR2_TCLR 0x00001E00U |
TCLR[3:0] bits (CLE to RE delay)
Definition at line 3936 of file stm32f407xx.h.
| #define FSMC_PCR2_TCLR_0 0x00000200U |
Bit 0
Definition at line 3937 of file stm32f407xx.h.
| #define FSMC_PCR2_TCLR_1 0x00000400U |
Bit 1
Definition at line 3938 of file stm32f407xx.h.
| #define FSMC_PCR2_TCLR_2 0x00000800U |
Bit 2
Definition at line 3939 of file stm32f407xx.h.
| #define FSMC_PCR2_TCLR_3 0x00001000U |
Bit 3
Definition at line 3940 of file stm32f407xx.h.
| #define FSMC_PCR3_ECCEN 0x00000040U |
ECC computation logic enable bit
Definition at line 3962 of file stm32f407xx.h.
| #define FSMC_PCR3_ECCPS 0x000E0000U |
ECCPS[2:0] bits (ECC page size)
Definition at line 3976 of file stm32f407xx.h.
| #define FSMC_PCR3_ECCPS_0 0x00020000U |
Bit 0
Definition at line 3977 of file stm32f407xx.h.
| #define FSMC_PCR3_ECCPS_1 0x00040000U |
Bit 1
Definition at line 3978 of file stm32f407xx.h.
| #define FSMC_PCR3_ECCPS_2 0x00080000U |
Bit 2
Definition at line 3979 of file stm32f407xx.h.
| #define FSMC_PCR3_PBKEN 0x00000004U |
PC Card/NAND Flash memory bank enable bit
Definition at line 3955 of file stm32f407xx.h.
| #define FSMC_PCR3_PTYP 0x00000008U |
Memory type
Definition at line 3956 of file stm32f407xx.h.
| #define FSMC_PCR3_PWAITEN 0x00000002U |
Wait feature enable bit
Definition at line 3954 of file stm32f407xx.h.
| #define FSMC_PCR3_PWID 0x00000030U |
PWID[1:0] bits (NAND Flash databus width)
Definition at line 3958 of file stm32f407xx.h.
| #define FSMC_PCR3_PWID_0 0x00000010U |
Bit 0
Definition at line 3959 of file stm32f407xx.h.
| #define FSMC_PCR3_PWID_1 0x00000020U |
Bit 1
Definition at line 3960 of file stm32f407xx.h.
| #define FSMC_PCR3_TAR 0x0001E000U |
TAR[3:0] bits (ALE to RE delay)
Definition at line 3970 of file stm32f407xx.h.
| #define FSMC_PCR3_TAR_0 0x00002000U |
Bit 0
Definition at line 3971 of file stm32f407xx.h.
| #define FSMC_PCR3_TAR_1 0x00004000U |
Bit 1
Definition at line 3972 of file stm32f407xx.h.
| #define FSMC_PCR3_TAR_2 0x00008000U |
Bit 2
Definition at line 3973 of file stm32f407xx.h.
| #define FSMC_PCR3_TAR_3 0x00010000U |
Bit 3
Definition at line 3974 of file stm32f407xx.h.
| #define FSMC_PCR3_TCLR 0x00001E00U |
TCLR[3:0] bits (CLE to RE delay)
Definition at line 3964 of file stm32f407xx.h.
| #define FSMC_PCR3_TCLR_0 0x00000200U |
Bit 0
Definition at line 3965 of file stm32f407xx.h.
| #define FSMC_PCR3_TCLR_1 0x00000400U |
Bit 1
Definition at line 3966 of file stm32f407xx.h.
| #define FSMC_PCR3_TCLR_2 0x00000800U |
Bit 2
Definition at line 3967 of file stm32f407xx.h.
| #define FSMC_PCR3_TCLR_3 0x00001000U |
Bit 3
Definition at line 3968 of file stm32f407xx.h.
| #define FSMC_PCR4_ECCEN 0x00000040U |
ECC computation logic enable bit
Definition at line 3990 of file stm32f407xx.h.
| #define FSMC_PCR4_ECCPS 0x000E0000U |
ECCPS[2:0] bits (ECC page size)
Definition at line 4004 of file stm32f407xx.h.
| #define FSMC_PCR4_ECCPS_0 0x00020000U |
Bit 0
Definition at line 4005 of file stm32f407xx.h.
| #define FSMC_PCR4_ECCPS_1 0x00040000U |
Bit 1
Definition at line 4006 of file stm32f407xx.h.
| #define FSMC_PCR4_ECCPS_2 0x00080000U |
Bit 2
Definition at line 4007 of file stm32f407xx.h.
| #define FSMC_PCR4_PBKEN 0x00000004U |
PC Card/NAND Flash memory bank enable bit
Definition at line 3983 of file stm32f407xx.h.
| #define FSMC_PCR4_PTYP 0x00000008U |
Memory type
Definition at line 3984 of file stm32f407xx.h.
| #define FSMC_PCR4_PWAITEN 0x00000002U |
Wait feature enable bit
Definition at line 3982 of file stm32f407xx.h.
| #define FSMC_PCR4_PWID 0x00000030U |
PWID[1:0] bits (NAND Flash databus width)
Definition at line 3986 of file stm32f407xx.h.
| #define FSMC_PCR4_PWID_0 0x00000010U |
Bit 0
Definition at line 3987 of file stm32f407xx.h.
| #define FSMC_PCR4_PWID_1 0x00000020U |
Bit 1
Definition at line 3988 of file stm32f407xx.h.
| #define FSMC_PCR4_TAR 0x0001E000U |
TAR[3:0] bits (ALE to RE delay)
Definition at line 3998 of file stm32f407xx.h.
| #define FSMC_PCR4_TAR_0 0x00002000U |
Bit 0
Definition at line 3999 of file stm32f407xx.h.
| #define FSMC_PCR4_TAR_1 0x00004000U |
Bit 1
Definition at line 4000 of file stm32f407xx.h.
| #define FSMC_PCR4_TAR_2 0x00008000U |
Bit 2
Definition at line 4001 of file stm32f407xx.h.
| #define FSMC_PCR4_TAR_3 0x00010000U |
Bit 3
Definition at line 4002 of file stm32f407xx.h.
| #define FSMC_PCR4_TCLR 0x00001E00U |
TCLR[3:0] bits (CLE to RE delay)
Definition at line 3992 of file stm32f407xx.h.
| #define FSMC_PCR4_TCLR_0 0x00000200U |
Bit 0
Definition at line 3993 of file stm32f407xx.h.
| #define FSMC_PCR4_TCLR_1 0x00000400U |
Bit 1
Definition at line 3994 of file stm32f407xx.h.
| #define FSMC_PCR4_TCLR_2 0x00000800U |
Bit 2
Definition at line 3995 of file stm32f407xx.h.
| #define FSMC_PCR4_TCLR_3 0x00001000U |
Bit 3
Definition at line 3996 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHIZ4 0xFF000000U |
IOHIZ4[7:0] bits (I/O 4 databus HiZ time)
Definition at line 4313 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHIZ4_0 0x01000000U |
Bit 0
Definition at line 4314 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHIZ4_1 0x02000000U |
Bit 1
Definition at line 4315 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHIZ4_2 0x04000000U |
Bit 2
Definition at line 4316 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHIZ4_3 0x08000000U |
Bit 3
Definition at line 4317 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHIZ4_4 0x10000000U |
Bit 4
Definition at line 4318 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHIZ4_5 0x20000000U |
Bit 5
Definition at line 4319 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHIZ4_6 0x40000000U |
Bit 6
Definition at line 4320 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHIZ4_7 0x80000000U |
Bit 7
Definition at line 4321 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHOLD4 0x00FF0000U |
IOHOLD4[7:0] bits (I/O 4 hold time)
Definition at line 4303 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHOLD4_0 0x00010000U |
Bit 0
Definition at line 4304 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHOLD4_1 0x00020000U |
Bit 1
Definition at line 4305 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHOLD4_2 0x00040000U |
Bit 2
Definition at line 4306 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHOLD4_3 0x00080000U |
Bit 3
Definition at line 4307 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHOLD4_4 0x00100000U |
Bit 4
Definition at line 4308 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHOLD4_5 0x00200000U |
Bit 5
Definition at line 4309 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHOLD4_6 0x00400000U |
Bit 6
Definition at line 4310 of file stm32f407xx.h.
| #define FSMC_PIO4_IOHOLD4_7 0x00800000U |
Bit 7
Definition at line 4311 of file stm32f407xx.h.
| #define FSMC_PIO4_IOSET4 0x000000FFU |
IOSET4[7:0] bits (I/O 4 setup time)
Definition at line 4283 of file stm32f407xx.h.
| #define FSMC_PIO4_IOSET4_0 0x00000001U |
Bit 0
Definition at line 4284 of file stm32f407xx.h.
| #define FSMC_PIO4_IOSET4_1 0x00000002U |
Bit 1
Definition at line 4285 of file stm32f407xx.h.
| #define FSMC_PIO4_IOSET4_2 0x00000004U |
Bit 2
Definition at line 4286 of file stm32f407xx.h.
| #define FSMC_PIO4_IOSET4_3 0x00000008U |
Bit 3
Definition at line 4287 of file stm32f407xx.h.
| #define FSMC_PIO4_IOSET4_4 0x00000010U |
Bit 4
Definition at line 4288 of file stm32f407xx.h.
| #define FSMC_PIO4_IOSET4_5 0x00000020U |
Bit 5
Definition at line 4289 of file stm32f407xx.h.
| #define FSMC_PIO4_IOSET4_6 0x00000040U |
Bit 6
Definition at line 4290 of file stm32f407xx.h.
| #define FSMC_PIO4_IOSET4_7 0x00000080U |
Bit 7
Definition at line 4291 of file stm32f407xx.h.
| #define FSMC_PIO4_IOWAIT4 0x0000FF00U |
IOWAIT4[7:0] bits (I/O 4 wait time)
Definition at line 4293 of file stm32f407xx.h.
| #define FSMC_PIO4_IOWAIT4_0 0x00000100U |
Bit 0
Definition at line 4294 of file stm32f407xx.h.
| #define FSMC_PIO4_IOWAIT4_1 0x00000200U |
Bit 1
Definition at line 4295 of file stm32f407xx.h.
| #define FSMC_PIO4_IOWAIT4_2 0x00000400U |
Bit 2
Definition at line 4296 of file stm32f407xx.h.
| #define FSMC_PIO4_IOWAIT4_3 0x00000800U |
Bit 3
Definition at line 4297 of file stm32f407xx.h.
| #define FSMC_PIO4_IOWAIT4_4 0x00001000U |
Bit 4
Definition at line 4298 of file stm32f407xx.h.
| #define FSMC_PIO4_IOWAIT4_5 0x00002000U |
Bit 5
Definition at line 4299 of file stm32f407xx.h.
| #define FSMC_PIO4_IOWAIT4_6 0x00004000U |
Bit 6
Definition at line 4300 of file stm32f407xx.h.
| #define FSMC_PIO4_IOWAIT4_7 0x00008000U |
Bit 7
Definition at line 4301 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHIZ2 0xFF000000U |
MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time)
Definition at line 4067 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHIZ2_0 0x01000000U |
Bit 0
Definition at line 4068 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHIZ2_1 0x02000000U |
Bit 1
Definition at line 4069 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHIZ2_2 0x04000000U |
Bit 2
Definition at line 4070 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHIZ2_3 0x08000000U |
Bit 3
Definition at line 4071 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHIZ2_4 0x10000000U |
Bit 4
Definition at line 4072 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHIZ2_5 0x20000000U |
Bit 5
Definition at line 4073 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHIZ2_6 0x40000000U |
Bit 6
Definition at line 4074 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHIZ2_7 0x80000000U |
Bit 7
Definition at line 4075 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHOLD2 0x00FF0000U |
MEMHOLD2[7:0] bits (Common memory 2 hold time)
Definition at line 4057 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHOLD2_0 0x00010000U |
Bit 0
Definition at line 4058 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHOLD2_1 0x00020000U |
Bit 1
Definition at line 4059 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHOLD2_2 0x00040000U |
Bit 2
Definition at line 4060 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHOLD2_3 0x00080000U |
Bit 3
Definition at line 4061 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHOLD2_4 0x00100000U |
Bit 4
Definition at line 4062 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHOLD2_5 0x00200000U |
Bit 5
Definition at line 4063 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHOLD2_6 0x00400000U |
Bit 6
Definition at line 4064 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMHOLD2_7 0x00800000U |
Bit 7
Definition at line 4065 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMSET2 0x000000FFU |
MEMSET2[7:0] bits (Common memory 2 setup time)
Definition at line 4037 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMSET2_0 0x00000001U |
Bit 0
Definition at line 4038 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMSET2_1 0x00000002U |
Bit 1
Definition at line 4039 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMSET2_2 0x00000004U |
Bit 2
Definition at line 4040 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMSET2_3 0x00000008U |
Bit 3
Definition at line 4041 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMSET2_4 0x00000010U |
Bit 4
Definition at line 4042 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMSET2_5 0x00000020U |
Bit 5
Definition at line 4043 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMSET2_6 0x00000040U |
Bit 6
Definition at line 4044 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMSET2_7 0x00000080U |
Bit 7
Definition at line 4045 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMWAIT2 0x0000FF00U |
MEMWAIT2[7:0] bits (Common memory 2 wait time)
Definition at line 4047 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMWAIT2_0 0x00000100U |
Bit 0
Definition at line 4048 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMWAIT2_1 0x00000200U |
Bit 1
Definition at line 4049 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMWAIT2_2 0x00000400U |
Bit 2
Definition at line 4050 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMWAIT2_3 0x00000800U |
Bit 3
Definition at line 4051 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMWAIT2_4 0x00001000U |
Bit 4
Definition at line 4052 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMWAIT2_5 0x00002000U |
Bit 5
Definition at line 4053 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMWAIT2_6 0x00004000U |
Bit 6
Definition at line 4054 of file stm32f407xx.h.
| #define FSMC_PMEM2_MEMWAIT2_7 0x00008000U |
Bit 7
Definition at line 4055 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHIZ3 0xFF000000U |
MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time)
Definition at line 4108 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHIZ3_0 0x01000000U |
Bit 0
Definition at line 4109 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHIZ3_1 0x02000000U |
Bit 1
Definition at line 4110 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHIZ3_2 0x04000000U |
Bit 2
Definition at line 4111 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHIZ3_3 0x08000000U |
Bit 3
Definition at line 4112 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHIZ3_4 0x10000000U |
Bit 4
Definition at line 4113 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHIZ3_5 0x20000000U |
Bit 5
Definition at line 4114 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHIZ3_6 0x40000000U |
Bit 6
Definition at line 4115 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHIZ3_7 0x80000000U |
Bit 7
Definition at line 4116 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHOLD3 0x00FF0000U |
MEMHOLD3[7:0] bits (Common memory 3 hold time)
Definition at line 4098 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHOLD3_0 0x00010000U |
Bit 0
Definition at line 4099 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHOLD3_1 0x00020000U |
Bit 1
Definition at line 4100 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHOLD3_2 0x00040000U |
Bit 2
Definition at line 4101 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHOLD3_3 0x00080000U |
Bit 3
Definition at line 4102 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHOLD3_4 0x00100000U |
Bit 4
Definition at line 4103 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHOLD3_5 0x00200000U |
Bit 5
Definition at line 4104 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHOLD3_6 0x00400000U |
Bit 6
Definition at line 4105 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMHOLD3_7 0x00800000U |
Bit 7
Definition at line 4106 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMSET3 0x000000FFU |
MEMSET3[7:0] bits (Common memory 3 setup time)
Definition at line 4078 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMSET3_0 0x00000001U |
Bit 0
Definition at line 4079 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMSET3_1 0x00000002U |
Bit 1
Definition at line 4080 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMSET3_2 0x00000004U |
Bit 2
Definition at line 4081 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMSET3_3 0x00000008U |
Bit 3
Definition at line 4082 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMSET3_4 0x00000010U |
Bit 4
Definition at line 4083 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMSET3_5 0x00000020U |
Bit 5
Definition at line 4084 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMSET3_6 0x00000040U |
Bit 6
Definition at line 4085 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMSET3_7 0x00000080U |
Bit 7
Definition at line 4086 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMWAIT3 0x0000FF00U |
MEMWAIT3[7:0] bits (Common memory 3 wait time)
Definition at line 4088 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMWAIT3_0 0x00000100U |
Bit 0
Definition at line 4089 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMWAIT3_1 0x00000200U |
Bit 1
Definition at line 4090 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMWAIT3_2 0x00000400U |
Bit 2
Definition at line 4091 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMWAIT3_3 0x00000800U |
Bit 3
Definition at line 4092 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMWAIT3_4 0x00001000U |
Bit 4
Definition at line 4093 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMWAIT3_5 0x00002000U |
Bit 5
Definition at line 4094 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMWAIT3_6 0x00004000U |
Bit 6
Definition at line 4095 of file stm32f407xx.h.
| #define FSMC_PMEM3_MEMWAIT3_7 0x00008000U |
Bit 7
Definition at line 4096 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHIZ4 0xFF000000U |
MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time)
Definition at line 4149 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHIZ4_0 0x01000000U |
Bit 0
Definition at line 4150 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHIZ4_1 0x02000000U |
Bit 1
Definition at line 4151 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHIZ4_2 0x04000000U |
Bit 2
Definition at line 4152 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHIZ4_3 0x08000000U |
Bit 3
Definition at line 4153 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHIZ4_4 0x10000000U |
Bit 4
Definition at line 4154 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHIZ4_5 0x20000000U |
Bit 5
Definition at line 4155 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHIZ4_6 0x40000000U |
Bit 6
Definition at line 4156 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHIZ4_7 0x80000000U |
Bit 7
Definition at line 4157 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHOLD4 0x00FF0000U |
MEMHOLD4[7:0] bits (Common memory 4 hold time)
Definition at line 4139 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHOLD4_0 0x00010000U |
Bit 0
Definition at line 4140 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHOLD4_1 0x00020000U |
Bit 1
Definition at line 4141 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHOLD4_2 0x00040000U |
Bit 2
Definition at line 4142 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHOLD4_3 0x00080000U |
Bit 3
Definition at line 4143 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHOLD4_4 0x00100000U |
Bit 4
Definition at line 4144 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHOLD4_5 0x00200000U |
Bit 5
Definition at line 4145 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHOLD4_6 0x00400000U |
Bit 6
Definition at line 4146 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMHOLD4_7 0x00800000U |
Bit 7
Definition at line 4147 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMSET4 0x000000FFU |
MEMSET4[7:0] bits (Common memory 4 setup time)
Definition at line 4119 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMSET4_0 0x00000001U |
Bit 0
Definition at line 4120 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMSET4_1 0x00000002U |
Bit 1
Definition at line 4121 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMSET4_2 0x00000004U |
Bit 2
Definition at line 4122 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMSET4_3 0x00000008U |
Bit 3
Definition at line 4123 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMSET4_4 0x00000010U |
Bit 4
Definition at line 4124 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMSET4_5 0x00000020U |
Bit 5
Definition at line 4125 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMSET4_6 0x00000040U |
Bit 6
Definition at line 4126 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMSET4_7 0x00000080U |
Bit 7
Definition at line 4127 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMWAIT4 0x0000FF00U |
MEMWAIT4[7:0] bits (Common memory 4 wait time)
Definition at line 4129 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMWAIT4_0 0x00000100U |
Bit 0
Definition at line 4130 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMWAIT4_1 0x00000200U |
Bit 1
Definition at line 4131 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMWAIT4_2 0x00000400U |
Bit 2
Definition at line 4132 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMWAIT4_3 0x00000800U |
Bit 3
Definition at line 4133 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMWAIT4_4 0x00001000U |
Bit 4
Definition at line 4134 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMWAIT4_5 0x00002000U |
Bit 5
Definition at line 4135 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMWAIT4_6 0x00004000U |
Bit 6
Definition at line 4136 of file stm32f407xx.h.
| #define FSMC_PMEM4_MEMWAIT4_7 0x00008000U |
Bit 7
Definition at line 4137 of file stm32f407xx.h.
| #define FSMC_SR2_FEMPT 0x40U |
FIFO empty
Definition at line 4016 of file stm32f407xx.h.
| #define FSMC_SR2_IFEN 0x20U |
Interrupt Falling Edge detection Enable bit
Definition at line 4015 of file stm32f407xx.h.
| #define FSMC_SR2_IFS 0x04U |
Interrupt Falling Edge status
Definition at line 4012 of file stm32f407xx.h.
| #define FSMC_SR2_ILEN 0x10U |
Interrupt Level detection Enable bit
Definition at line 4014 of file stm32f407xx.h.
| #define FSMC_SR2_ILS 0x02U |
Interrupt Level status
Definition at line 4011 of file stm32f407xx.h.
| #define FSMC_SR2_IREN 0x08U |
Interrupt Rising Edge detection Enable bit
Definition at line 4013 of file stm32f407xx.h.
| #define FSMC_SR2_IRS 0x01U |
Interrupt Rising Edge status
Definition at line 4010 of file stm32f407xx.h.
| #define FSMC_SR3_FEMPT 0x40U |
FIFO empty
Definition at line 4025 of file stm32f407xx.h.
| #define FSMC_SR3_IFEN 0x20U |
Interrupt Falling Edge detection Enable bit
Definition at line 4024 of file stm32f407xx.h.
| #define FSMC_SR3_IFS 0x04U |
Interrupt Falling Edge status
Definition at line 4021 of file stm32f407xx.h.
| #define FSMC_SR3_ILEN 0x10U |
Interrupt Level detection Enable bit
Definition at line 4023 of file stm32f407xx.h.
| #define FSMC_SR3_ILS 0x02U |
Interrupt Level status
Definition at line 4020 of file stm32f407xx.h.
| #define FSMC_SR3_IREN 0x08U |
Interrupt Rising Edge detection Enable bit
Definition at line 4022 of file stm32f407xx.h.
| #define FSMC_SR3_IRS 0x01U |
Interrupt Rising Edge status
Definition at line 4019 of file stm32f407xx.h.
| #define FSMC_SR4_FEMPT 0x40U |
FIFO empty
Definition at line 4034 of file stm32f407xx.h.
| #define FSMC_SR4_IFEN 0x20U |
Interrupt Falling Edge detection Enable bit
Definition at line 4033 of file stm32f407xx.h.
| #define FSMC_SR4_IFS 0x04U |
Interrupt Falling Edge status
Definition at line 4030 of file stm32f407xx.h.
| #define FSMC_SR4_ILEN 0x10U |
Interrupt Level detection Enable bit
Definition at line 4032 of file stm32f407xx.h.
| #define FSMC_SR4_ILS 0x02U |
Interrupt Level status
Definition at line 4029 of file stm32f407xx.h.
| #define FSMC_SR4_IREN 0x08U |
Interrupt Rising Edge detection Enable bit
Definition at line 4031 of file stm32f407xx.h.
| #define FSMC_SR4_IRS 0x01U |
Interrupt Rising Edge status
Definition at line 4028 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_0 0x00010000U |
Definition at line 4634 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_1 0x00020000U |
Definition at line 4635 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_10 0x04000000U |
Definition at line 4644 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_11 0x08000000U |
Definition at line 4645 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_12 0x10000000U |
Definition at line 4646 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_13 0x20000000U |
Definition at line 4647 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_14 0x40000000U |
Definition at line 4648 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_15 0x80000000U |
Definition at line 4649 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_2 0x00040000U |
Definition at line 4636 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_3 0x00080000U |
Definition at line 4637 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_4 0x00100000U |
Definition at line 4638 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_5 0x00200000U |
Definition at line 4639 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_6 0x00400000U |
Definition at line 4640 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_7 0x00800000U |
Definition at line 4641 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_8 0x01000000U |
Definition at line 4642 of file stm32f407xx.h.
| #define GPIO_BSRR_BR_9 0x02000000U |
Definition at line 4643 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_0 0x00000001U |
Definition at line 4618 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_1 0x00000002U |
Definition at line 4619 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_10 0x00000400U |
Definition at line 4628 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_11 0x00000800U |
Definition at line 4629 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_12 0x00001000U |
Definition at line 4630 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_13 0x00002000U |
Definition at line 4631 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_14 0x00004000U |
Definition at line 4632 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_15 0x00008000U |
Definition at line 4633 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_2 0x00000004U |
Definition at line 4620 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_3 0x00000008U |
Definition at line 4621 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_4 0x00000010U |
Definition at line 4622 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_5 0x00000020U |
Definition at line 4623 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_6 0x00000040U |
Definition at line 4624 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_7 0x00000080U |
Definition at line 4625 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_8 0x00000100U |
Definition at line 4626 of file stm32f407xx.h.
| #define GPIO_BSRR_BS_9 0x00000200U |
Definition at line 4627 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_0 0x00000001U |
Definition at line 4548 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_1 0x00000002U |
Definition at line 4549 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_10 0x00000400U |
Definition at line 4558 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_11 0x00000800U |
Definition at line 4559 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_12 0x00001000U |
Definition at line 4560 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_13 0x00002000U |
Definition at line 4561 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_14 0x00004000U |
Definition at line 4562 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_15 0x00008000U |
Definition at line 4563 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_2 0x00000004U |
Definition at line 4550 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_3 0x00000008U |
Definition at line 4551 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_4 0x00000010U |
Definition at line 4552 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_5 0x00000020U |
Definition at line 4553 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_6 0x00000040U |
Definition at line 4554 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_7 0x00000080U |
Definition at line 4555 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_8 0x00000100U |
Definition at line 4556 of file stm32f407xx.h.
| #define GPIO_IDR_IDR_9 0x00000200U |
Definition at line 4557 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK0 0x00000001U |
Definition at line 4652 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK1 0x00000002U |
Definition at line 4653 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK10 0x00000400U |
Definition at line 4662 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK11 0x00000800U |
Definition at line 4663 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK12 0x00001000U |
Definition at line 4664 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK13 0x00002000U |
Definition at line 4665 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK14 0x00004000U |
Definition at line 4666 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK15 0x00008000U |
Definition at line 4667 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK2 0x00000004U |
Definition at line 4654 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK3 0x00000008U |
Definition at line 4655 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK4 0x00000010U |
Definition at line 4656 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK5 0x00000020U |
Definition at line 4657 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK6 0x00000040U |
Definition at line 4658 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK7 0x00000080U |
Definition at line 4659 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK8 0x00000100U |
Definition at line 4660 of file stm32f407xx.h.
| #define GPIO_LCKR_LCK9 0x00000200U |
Definition at line 4661 of file stm32f407xx.h.
| #define GPIO_LCKR_LCKK 0x00010000U |
Definition at line 4668 of file stm32f407xx.h.
| #define GPIO_MODER_MODER0 0x00000003U |
Definition at line 4335 of file stm32f407xx.h.
| #define GPIO_MODER_MODER0_0 0x00000001U |
Definition at line 4336 of file stm32f407xx.h.
| #define GPIO_MODER_MODER0_1 0x00000002U |
Definition at line 4337 of file stm32f407xx.h.
| #define GPIO_MODER_MODER1 0x0000000CU |
Definition at line 4339 of file stm32f407xx.h.
| #define GPIO_MODER_MODER10 0x00300000U |
Definition at line 4375 of file stm32f407xx.h.
| #define GPIO_MODER_MODER10_0 0x00100000U |
Definition at line 4376 of file stm32f407xx.h.
| #define GPIO_MODER_MODER10_1 0x00200000U |
Definition at line 4377 of file stm32f407xx.h.
| #define GPIO_MODER_MODER11 0x00C00000U |
Definition at line 4379 of file stm32f407xx.h.
| #define GPIO_MODER_MODER11_0 0x00400000U |
Definition at line 4380 of file stm32f407xx.h.
| #define GPIO_MODER_MODER11_1 0x00800000U |
Definition at line 4381 of file stm32f407xx.h.
| #define GPIO_MODER_MODER12 0x03000000U |
Definition at line 4383 of file stm32f407xx.h.
| #define GPIO_MODER_MODER12_0 0x01000000U |
Definition at line 4384 of file stm32f407xx.h.
| #define GPIO_MODER_MODER12_1 0x02000000U |
Definition at line 4385 of file stm32f407xx.h.
| #define GPIO_MODER_MODER13 0x0C000000U |
Definition at line 4387 of file stm32f407xx.h.
| #define GPIO_MODER_MODER13_0 0x04000000U |
Definition at line 4388 of file stm32f407xx.h.
| #define GPIO_MODER_MODER13_1 0x08000000U |
Definition at line 4389 of file stm32f407xx.h.
| #define GPIO_MODER_MODER14 0x30000000U |
Definition at line 4391 of file stm32f407xx.h.
| #define GPIO_MODER_MODER14_0 0x10000000U |
Definition at line 4392 of file stm32f407xx.h.
| #define GPIO_MODER_MODER14_1 0x20000000U |
Definition at line 4393 of file stm32f407xx.h.
| #define GPIO_MODER_MODER15 0xC0000000U |
Definition at line 4395 of file stm32f407xx.h.
| #define GPIO_MODER_MODER15_0 0x40000000U |
Definition at line 4396 of file stm32f407xx.h.
| #define GPIO_MODER_MODER15_1 0x80000000U |
Definition at line 4397 of file stm32f407xx.h.
| #define GPIO_MODER_MODER1_0 0x00000004U |
Definition at line 4340 of file stm32f407xx.h.
| #define GPIO_MODER_MODER1_1 0x00000008U |
Definition at line 4341 of file stm32f407xx.h.
| #define GPIO_MODER_MODER2 0x00000030U |
Definition at line 4343 of file stm32f407xx.h.
| #define GPIO_MODER_MODER2_0 0x00000010U |
Definition at line 4344 of file stm32f407xx.h.
| #define GPIO_MODER_MODER2_1 0x00000020U |
Definition at line 4345 of file stm32f407xx.h.
| #define GPIO_MODER_MODER3 0x000000C0U |
Definition at line 4347 of file stm32f407xx.h.
| #define GPIO_MODER_MODER3_0 0x00000040U |
Definition at line 4348 of file stm32f407xx.h.
| #define GPIO_MODER_MODER3_1 0x00000080U |
Definition at line 4349 of file stm32f407xx.h.
| #define GPIO_MODER_MODER4 0x00000300U |
Definition at line 4351 of file stm32f407xx.h.
| #define GPIO_MODER_MODER4_0 0x00000100U |
Definition at line 4352 of file stm32f407xx.h.
| #define GPIO_MODER_MODER4_1 0x00000200U |
Definition at line 4353 of file stm32f407xx.h.
| #define GPIO_MODER_MODER5 0x00000C00U |
Definition at line 4355 of file stm32f407xx.h.
| #define GPIO_MODER_MODER5_0 0x00000400U |
Definition at line 4356 of file stm32f407xx.h.
| #define GPIO_MODER_MODER5_1 0x00000800U |
Definition at line 4357 of file stm32f407xx.h.
| #define GPIO_MODER_MODER6 0x00003000U |
Definition at line 4359 of file stm32f407xx.h.
| #define GPIO_MODER_MODER6_0 0x00001000U |
Definition at line 4360 of file stm32f407xx.h.
| #define GPIO_MODER_MODER6_1 0x00002000U |
Definition at line 4361 of file stm32f407xx.h.
| #define GPIO_MODER_MODER7 0x0000C000U |
Definition at line 4363 of file stm32f407xx.h.
| #define GPIO_MODER_MODER7_0 0x00004000U |
Definition at line 4364 of file stm32f407xx.h.
| #define GPIO_MODER_MODER7_1 0x00008000U |
Definition at line 4365 of file stm32f407xx.h.
| #define GPIO_MODER_MODER8 0x00030000U |
Definition at line 4367 of file stm32f407xx.h.
| #define GPIO_MODER_MODER8_0 0x00010000U |
Definition at line 4368 of file stm32f407xx.h.
| #define GPIO_MODER_MODER8_1 0x00020000U |
Definition at line 4369 of file stm32f407xx.h.
| #define GPIO_MODER_MODER9 0x000C0000U |
Definition at line 4371 of file stm32f407xx.h.
| #define GPIO_MODER_MODER9_0 0x00040000U |
Definition at line 4372 of file stm32f407xx.h.
| #define GPIO_MODER_MODER9_1 0x00080000U |
Definition at line 4373 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_0 0x00000001U |
Definition at line 4583 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_1 0x00000002U |
Definition at line 4584 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_10 0x00000400U |
Definition at line 4593 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_11 0x00000800U |
Definition at line 4594 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_12 0x00001000U |
Definition at line 4595 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_13 0x00002000U |
Definition at line 4596 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_14 0x00004000U |
Definition at line 4597 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_15 0x00008000U |
Definition at line 4598 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_2 0x00000004U |
Definition at line 4585 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_3 0x00000008U |
Definition at line 4586 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_4 0x00000010U |
Definition at line 4587 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_5 0x00000020U |
Definition at line 4588 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_6 0x00000040U |
Definition at line 4589 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_7 0x00000080U |
Definition at line 4590 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_8 0x00000100U |
Definition at line 4591 of file stm32f407xx.h.
| #define GPIO_ODR_ODR_9 0x00000200U |
Definition at line 4592 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U |
Definition at line 4418 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U |
Definition at line 4419 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U |
Definition at line 4420 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU |
Definition at line 4422 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U |
Definition at line 4458 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U |
Definition at line 4459 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U |
Definition at line 4460 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U |
Definition at line 4462 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U |
Definition at line 4463 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U |
Definition at line 4464 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U |
Definition at line 4466 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U |
Definition at line 4467 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U |
Definition at line 4468 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U |
Definition at line 4470 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U |
Definition at line 4471 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U |
Definition at line 4472 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U |
Definition at line 4474 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U |
Definition at line 4475 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U |
Definition at line 4476 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U |
Definition at line 4478 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U |
Definition at line 4479 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U |
Definition at line 4480 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U |
Definition at line 4423 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U |
Definition at line 4424 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U |
Definition at line 4426 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U |
Definition at line 4427 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U |
Definition at line 4428 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U |
Definition at line 4430 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U |
Definition at line 4431 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U |
Definition at line 4432 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U |
Definition at line 4434 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U |
Definition at line 4435 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U |
Definition at line 4436 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U |
Definition at line 4438 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U |
Definition at line 4439 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U |
Definition at line 4440 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U |
Definition at line 4442 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U |
Definition at line 4443 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U |
Definition at line 4444 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U |
Definition at line 4446 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U |
Definition at line 4447 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U |
Definition at line 4448 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U |
Definition at line 4450 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U |
Definition at line 4451 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U |
Definition at line 4452 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U |
Definition at line 4454 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U |
Definition at line 4455 of file stm32f407xx.h.
| #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U |
Definition at line 4456 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 |
Definition at line 4565 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 |
Definition at line 4566 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 |
Definition at line 4575 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 |
Definition at line 4576 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 |
Definition at line 4577 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 |
Definition at line 4578 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 |
Definition at line 4579 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 |
Definition at line 4580 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 |
Definition at line 4567 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 |
Definition at line 4568 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 |
Definition at line 4569 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 |
Definition at line 4570 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 |
Definition at line 4571 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 |
Definition at line 4572 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 |
Definition at line 4573 of file stm32f407xx.h.
| #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 |
Definition at line 4574 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 |
Definition at line 4600 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 |
Definition at line 4601 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 |
Definition at line 4610 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 |
Definition at line 4611 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 |
Definition at line 4612 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 |
Definition at line 4613 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 |
Definition at line 4614 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 |
Definition at line 4615 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 |
Definition at line 4602 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 |
Definition at line 4603 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 |
Definition at line 4604 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 |
Definition at line 4605 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 |
Definition at line 4606 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 |
Definition at line 4607 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 |
Definition at line 4608 of file stm32f407xx.h.
| #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 |
Definition at line 4609 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_0 0x00000001U |
Definition at line 4400 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_1 0x00000002U |
Definition at line 4401 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_10 0x00000400U |
Definition at line 4410 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_11 0x00000800U |
Definition at line 4411 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_12 0x00001000U |
Definition at line 4412 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_13 0x00002000U |
Definition at line 4413 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_14 0x00004000U |
Definition at line 4414 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_15 0x00008000U |
Definition at line 4415 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_2 0x00000004U |
Definition at line 4402 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_3 0x00000008U |
Definition at line 4403 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_4 0x00000010U |
Definition at line 4404 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_5 0x00000020U |
Definition at line 4405 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_6 0x00000040U |
Definition at line 4406 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_7 0x00000080U |
Definition at line 4407 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_8 0x00000100U |
Definition at line 4408 of file stm32f407xx.h.
| #define GPIO_OTYPER_OT_9 0x00000200U |
Definition at line 4409 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR0 0x00000003U |
Definition at line 4483 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR0_0 0x00000001U |
Definition at line 4484 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR0_1 0x00000002U |
Definition at line 4485 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR1 0x0000000CU |
Definition at line 4487 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR10 0x00300000U |
Definition at line 4523 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR10_0 0x00100000U |
Definition at line 4524 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR10_1 0x00200000U |
Definition at line 4525 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR11 0x00C00000U |
Definition at line 4527 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR11_0 0x00400000U |
Definition at line 4528 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR11_1 0x00800000U |
Definition at line 4529 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR12 0x03000000U |
Definition at line 4531 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR12_0 0x01000000U |
Definition at line 4532 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR12_1 0x02000000U |
Definition at line 4533 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR13 0x0C000000U |
Definition at line 4535 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR13_0 0x04000000U |
Definition at line 4536 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR13_1 0x08000000U |
Definition at line 4537 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR14 0x30000000U |
Definition at line 4539 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR14_0 0x10000000U |
Definition at line 4540 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR14_1 0x20000000U |
Definition at line 4541 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR15 0xC0000000U |
Definition at line 4543 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR15_0 0x40000000U |
Definition at line 4544 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR15_1 0x80000000U |
Definition at line 4545 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR1_0 0x00000004U |
Definition at line 4488 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR1_1 0x00000008U |
Definition at line 4489 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR2 0x00000030U |
Definition at line 4491 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR2_0 0x00000010U |
Definition at line 4492 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR2_1 0x00000020U |
Definition at line 4493 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR3 0x000000C0U |
Definition at line 4495 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR3_0 0x00000040U |
Definition at line 4496 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR3_1 0x00000080U |
Definition at line 4497 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR4 0x00000300U |
Definition at line 4499 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR4_0 0x00000100U |
Definition at line 4500 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR4_1 0x00000200U |
Definition at line 4501 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR5 0x00000C00U |
Definition at line 4503 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR5_0 0x00000400U |
Definition at line 4504 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR5_1 0x00000800U |
Definition at line 4505 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR6 0x00003000U |
Definition at line 4507 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR6_0 0x00001000U |
Definition at line 4508 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR6_1 0x00002000U |
Definition at line 4509 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR7 0x0000C000U |
Definition at line 4511 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR7_0 0x00004000U |
Definition at line 4512 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR7_1 0x00008000U |
Definition at line 4513 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR8 0x00030000U |
Definition at line 4515 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR8_0 0x00010000U |
Definition at line 4516 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR8_1 0x00020000U |
Definition at line 4517 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR9 0x000C0000U |
Definition at line 4519 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR9_0 0x00040000U |
Definition at line 4520 of file stm32f407xx.h.
| #define GPIO_PUPDR_PUPDR9_1 0x00080000U |
Definition at line 4521 of file stm32f407xx.h.
| #define I2C_CCR_CCR 0x00000FFFU |
Clock Control Register in Fast/Standard mode (Master mode)
Definition at line 4757 of file stm32f407xx.h.
| #define I2C_CCR_DUTY 0x00004000U |
Fast Mode Duty Cycle
Definition at line 4758 of file stm32f407xx.h.
| #define I2C_CCR_FS 0x00008000U |
I2C Master Mode Selection
Definition at line 4759 of file stm32f407xx.h.
| #define I2C_CR1_ACK 0x00000400U |
Acknowledge Enable
Definition at line 4685 of file stm32f407xx.h.
| #define I2C_CR1_ALERT 0x00002000U |
SMBus Alert
Definition at line 4688 of file stm32f407xx.h.
| #define I2C_CR1_ENARP 0x00000010U |
ARP Enable
Definition at line 4679 of file stm32f407xx.h.
| #define I2C_CR1_ENGC 0x00000040U |
General Call Enable
Definition at line 4681 of file stm32f407xx.h.
| #define I2C_CR1_ENPEC 0x00000020U |
PEC Enable
Definition at line 4680 of file stm32f407xx.h.
| #define I2C_CR1_NOSTRETCH 0x00000080U |
Clock Stretching Disable (Slave mode)
Definition at line 4682 of file stm32f407xx.h.
| #define I2C_CR1_PE 0x00000001U |
Peripheral Enable
Definition at line 4676 of file stm32f407xx.h.
| #define I2C_CR1_PEC 0x00001000U |
Packet Error Checking
Definition at line 4687 of file stm32f407xx.h.
| #define I2C_CR1_POS 0x00000800U |
Acknowledge/PEC Position (for data reception)
Definition at line 4686 of file stm32f407xx.h.
| #define I2C_CR1_SMBTYPE 0x00000008U |
SMBus Type
Definition at line 4678 of file stm32f407xx.h.
| #define I2C_CR1_SMBUS 0x00000002U |
SMBus Mode
Definition at line 4677 of file stm32f407xx.h.
| #define I2C_CR1_START 0x00000100U |
Start Generation
Definition at line 4683 of file stm32f407xx.h.
| #define I2C_CR1_STOP 0x00000200U |
Stop Generation
Definition at line 4684 of file stm32f407xx.h.
| #define I2C_CR1_SWRST 0x00008000U |
Software Reset
Definition at line 4689 of file stm32f407xx.h.
| #define I2C_CR2_DMAEN 0x00000800U |
DMA Requests Enable
Definition at line 4703 of file stm32f407xx.h.
| #define I2C_CR2_FREQ 0x0000003FU |
FREQ[5:0] bits (Peripheral Clock Frequency)
Definition at line 4692 of file stm32f407xx.h.
| #define I2C_CR2_FREQ_0 0x00000001U |
Bit 0
Definition at line 4693 of file stm32f407xx.h.
| #define I2C_CR2_FREQ_1 0x00000002U |
Bit 1
Definition at line 4694 of file stm32f407xx.h.
| #define I2C_CR2_FREQ_2 0x00000004U |
Bit 2
Definition at line 4695 of file stm32f407xx.h.
| #define I2C_CR2_FREQ_3 0x00000008U |
Bit 3
Definition at line 4696 of file stm32f407xx.h.
| #define I2C_CR2_FREQ_4 0x00000010U |
Bit 4
Definition at line 4697 of file stm32f407xx.h.
| #define I2C_CR2_FREQ_5 0x00000020U |
Bit 5
Definition at line 4698 of file stm32f407xx.h.
| #define I2C_CR2_ITBUFEN 0x00000400U |
Buffer Interrupt Enable
Definition at line 4702 of file stm32f407xx.h.
| #define I2C_CR2_ITERREN 0x00000100U |
Error Interrupt Enable
Definition at line 4700 of file stm32f407xx.h.
| #define I2C_CR2_ITEVTEN 0x00000200U |
Event Interrupt Enable
Definition at line 4701 of file stm32f407xx.h.
| #define I2C_CR2_LAST 0x00001000U |
DMA Last Transfer
Definition at line 4704 of file stm32f407xx.h.
| #define I2C_DR_DR 0x000000FFU |
8-bit Data Register
Definition at line 4728 of file stm32f407xx.h.
| #define I2C_FLTR_ANOFF 0x00000010U |
Analog Noise Filter OFF
Definition at line 4766 of file stm32f407xx.h.
| #define I2C_FLTR_DNF 0x0000000FU |
Digital Noise Filter
Definition at line 4765 of file stm32f407xx.h.
| #define I2C_OAR1_ADD0 0x00000001U |
Bit 0
Definition at line 4710 of file stm32f407xx.h.
| #define I2C_OAR1_ADD1 0x00000002U |
Bit 1
Definition at line 4711 of file stm32f407xx.h.
| #define I2C_OAR1_ADD1_7 0x000000FEU |
Interface Address
Definition at line 4707 of file stm32f407xx.h.
| #define I2C_OAR1_ADD2 0x00000004U |
Bit 2
Definition at line 4712 of file stm32f407xx.h.
| #define I2C_OAR1_ADD3 0x00000008U |
Bit 3
Definition at line 4713 of file stm32f407xx.h.
| #define I2C_OAR1_ADD4 0x00000010U |
Bit 4
Definition at line 4714 of file stm32f407xx.h.
| #define I2C_OAR1_ADD5 0x00000020U |
Bit 5
Definition at line 4715 of file stm32f407xx.h.
| #define I2C_OAR1_ADD6 0x00000040U |
Bit 6
Definition at line 4716 of file stm32f407xx.h.
| #define I2C_OAR1_ADD7 0x00000080U |
Bit 7
Definition at line 4717 of file stm32f407xx.h.
| #define I2C_OAR1_ADD8 0x00000100U |
Bit 8
Definition at line 4718 of file stm32f407xx.h.
| #define I2C_OAR1_ADD8_9 0x00000300U |
Interface Address
Definition at line 4708 of file stm32f407xx.h.
| #define I2C_OAR1_ADD9 0x00000200U |
Bit 9
Definition at line 4719 of file stm32f407xx.h.
| #define I2C_OAR1_ADDMODE 0x00008000U |
Addressing Mode (Slave mode)
Definition at line 4721 of file stm32f407xx.h.
| #define I2C_OAR2_ADD2 0x000000FEU |
Interface address
Definition at line 4725 of file stm32f407xx.h.
| #define I2C_OAR2_ENDUAL 0x00000001U |
Dual addressing mode enable
Definition at line 4724 of file stm32f407xx.h.
| #define I2C_SR1_ADD10 0x00000008U |
10-bit header sent (Master mode)
Definition at line 4734 of file stm32f407xx.h.
| #define I2C_SR1_ADDR 0x00000002U |
Address sent (master mode)/matched (slave mode)
Definition at line 4732 of file stm32f407xx.h.
| #define I2C_SR1_AF 0x00000400U |
Acknowledge Failure
Definition at line 4740 of file stm32f407xx.h.
| #define I2C_SR1_ARLO 0x00000200U |
Arbitration Lost (master mode)
Definition at line 4739 of file stm32f407xx.h.
| #define I2C_SR1_BERR 0x00000100U |
Bus Error
Definition at line 4738 of file stm32f407xx.h.
| #define I2C_SR1_BTF 0x00000004U |
Byte Transfer Finished
Definition at line 4733 of file stm32f407xx.h.
| #define I2C_SR1_OVR 0x00000800U |
Overrun/Underrun
Definition at line 4741 of file stm32f407xx.h.
| #define I2C_SR1_PECERR 0x00001000U |
PEC Error in reception
Definition at line 4742 of file stm32f407xx.h.
| #define I2C_SR1_RXNE 0x00000040U |
Data Register not Empty (receivers)
Definition at line 4736 of file stm32f407xx.h.
| #define I2C_SR1_SB 0x00000001U |
Start Bit (Master mode)
Definition at line 4731 of file stm32f407xx.h.
| #define I2C_SR1_SMBALERT 0x00008000U |
SMBus Alert
Definition at line 4744 of file stm32f407xx.h.
| #define I2C_SR1_STOPF 0x00000010U |
Stop detection (Slave mode)
Definition at line 4735 of file stm32f407xx.h.
| #define I2C_SR1_TIMEOUT 0x00004000U |
Timeout or Tlow Error
Definition at line 4743 of file stm32f407xx.h.
| #define I2C_SR1_TXE 0x00000080U |
Data Register Empty (transmitters)
Definition at line 4737 of file stm32f407xx.h.
| #define I2C_SR2_BUSY 0x00000002U |
Bus Busy
Definition at line 4748 of file stm32f407xx.h.
| #define I2C_SR2_DUALF 0x00000080U |
Dual Flag (Slave mode)
Definition at line 4753 of file stm32f407xx.h.
| #define I2C_SR2_GENCALL 0x00000010U |
General Call Address (Slave mode)
Definition at line 4750 of file stm32f407xx.h.
| #define I2C_SR2_MSL 0x00000001U |
Master/Slave
Definition at line 4747 of file stm32f407xx.h.
| #define I2C_SR2_PEC 0x0000FF00U |
Packet Error Checking Register
Definition at line 4754 of file stm32f407xx.h.
| #define I2C_SR2_SMBDEFAULT 0x00000020U |
SMBus Device Default Address (Slave mode)
Definition at line 4751 of file stm32f407xx.h.
| #define I2C_SR2_SMBHOST 0x00000040U |
SMBus Host Header (Slave mode)
Definition at line 4752 of file stm32f407xx.h.
| #define I2C_SR2_TRA 0x00000004U |
Transmitter/Receiver
Definition at line 4749 of file stm32f407xx.h.
| #define I2C_TRISE_TRISE 0x0000003FU |
Maximum Rise Time in Fast/Standard mode (Master mode)
Definition at line 4762 of file stm32f407xx.h.
| #define IWDG_KR_KEY 0xFFFFU |
Key value (write only, read 0000h)
Definition at line 4774 of file stm32f407xx.h.
| #define IWDG_PR_PR 0x07U |
PR[2:0] (Prescaler divider)
Definition at line 4777 of file stm32f407xx.h.
| #define IWDG_PR_PR_0 0x01U |
Bit 0
Definition at line 4778 of file stm32f407xx.h.
| #define IWDG_PR_PR_1 0x02U |
Bit 1
Definition at line 4779 of file stm32f407xx.h.
| #define IWDG_PR_PR_2 0x04U |
Bit 2
Definition at line 4780 of file stm32f407xx.h.
| #define IWDG_RLR_RL 0x0FFFU |
Watchdog counter reload value
Definition at line 4783 of file stm32f407xx.h.
| #define IWDG_SR_PVU 0x01U |
Watchdog prescaler value update
Definition at line 4786 of file stm32f407xx.h.
| #define IWDG_SR_RVU 0x02U |
Watchdog counter reload value update
Definition at line 4787 of file stm32f407xx.h.
| #define PWR_CR_CSBF 0x00000008U |
Clear Standby Flag
Definition at line 4799 of file stm32f407xx.h.
| #define PWR_CR_CWUF 0x00000004U |
Clear Wakeup Flag
Definition at line 4798 of file stm32f407xx.h.
| #define PWR_CR_DBP 0x00000100U |
Disable Backup Domain write protection
Definition at line 4817 of file stm32f407xx.h.
| #define PWR_CR_FPDS 0x00000200U |
Flash power down in Stop mode
Definition at line 4818 of file stm32f407xx.h.
| #define PWR_CR_LPDS 0x00000001U |
Low-Power Deepsleep
Definition at line 4796 of file stm32f407xx.h.
| #define PWR_CR_PDDS 0x00000002U |
Power Down Deepsleep
Definition at line 4797 of file stm32f407xx.h.
| #define PWR_CR_PLS 0x000000E0U |
PLS[2:0] bits (PVD Level Selection)
Definition at line 4802 of file stm32f407xx.h.
| #define PWR_CR_PLS_0 0x00000020U |
Bit 0
Definition at line 4803 of file stm32f407xx.h.
| #define PWR_CR_PLS_1 0x00000040U |
Bit 1
Definition at line 4804 of file stm32f407xx.h.
| #define PWR_CR_PLS_2 0x00000080U |
Bit 2 PVD level configuration
Definition at line 4807 of file stm32f407xx.h.
| #define PWR_CR_PLS_LEV0 0x00000000U |
PVD level 0
Definition at line 4808 of file stm32f407xx.h.
| #define PWR_CR_PLS_LEV1 0x00000020U |
PVD level 1
Definition at line 4809 of file stm32f407xx.h.
| #define PWR_CR_PLS_LEV2 0x00000040U |
PVD level 2
Definition at line 4810 of file stm32f407xx.h.
| #define PWR_CR_PLS_LEV3 0x00000060U |
PVD level 3
Definition at line 4811 of file stm32f407xx.h.
| #define PWR_CR_PLS_LEV4 0x00000080U |
PVD level 4
Definition at line 4812 of file stm32f407xx.h.
| #define PWR_CR_PLS_LEV5 0x000000A0U |
PVD level 5
Definition at line 4813 of file stm32f407xx.h.
| #define PWR_CR_PLS_LEV6 0x000000C0U |
PVD level 6
Definition at line 4814 of file stm32f407xx.h.
| #define PWR_CR_PLS_LEV7 0x000000E0U |
PVD level 7
Definition at line 4815 of file stm32f407xx.h.
| #define PWR_CR_PMODE PWR_CR_VOS |
Definition at line 4822 of file stm32f407xx.h.
| #define PWR_CR_PVDE 0x00000010U |
Power Voltage Detector Enable
Definition at line 4800 of file stm32f407xx.h.
| #define PWR_CR_VOS 0x00004000U |
VOS bit (Regulator voltage scaling output selection)
Definition at line 4819 of file stm32f407xx.h.
| #define PWR_CSR_BRE 0x00000200U |
Backup regulator enable
Definition at line 4830 of file stm32f407xx.h.
| #define PWR_CSR_BRR 0x00000008U |
Backup regulator ready
Definition at line 4828 of file stm32f407xx.h.
| #define PWR_CSR_EWUP 0x00000100U |
Enable WKUP pin
Definition at line 4829 of file stm32f407xx.h.
| #define PWR_CSR_PVDO 0x00000004U |
PVD Output
Definition at line 4827 of file stm32f407xx.h.
| #define PWR_CSR_REGRDY PWR_CSR_VOSRDY |
Definition at line 4834 of file stm32f407xx.h.
| #define PWR_CSR_SBF 0x00000002U |
Standby Flag
Definition at line 4826 of file stm32f407xx.h.
| #define PWR_CSR_VOSRDY 0x00004000U |
Regulator voltage scaling output selection ready
Definition at line 4831 of file stm32f407xx.h.
| #define PWR_CSR_WUF 0x00000001U |
Wakeup Flag
Definition at line 4825 of file stm32f407xx.h.
| #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U |
Definition at line 5096 of file stm32f407xx.h.
| #define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U |
Definition at line 5097 of file stm32f407xx.h.
| #define RCC_AHB1ENR_CRCEN 0x00001000U |
Definition at line 5095 of file stm32f407xx.h.
| #define RCC_AHB1ENR_DMA1EN 0x00200000U |
Definition at line 5098 of file stm32f407xx.h.
| #define RCC_AHB1ENR_DMA2EN 0x00400000U |
Definition at line 5099 of file stm32f407xx.h.
| #define RCC_AHB1ENR_ETHMACEN 0x02000000U |
Definition at line 5101 of file stm32f407xx.h.
| #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U |
Definition at line 5104 of file stm32f407xx.h.
| #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U |
Definition at line 5103 of file stm32f407xx.h.
| #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U |
Definition at line 5102 of file stm32f407xx.h.
| #define RCC_AHB1ENR_GPIOAEN 0x00000001U |
Definition at line 5086 of file stm32f407xx.h.
| #define RCC_AHB1ENR_GPIOBEN 0x00000002U |
Definition at line 5087 of file stm32f407xx.h.
| #define RCC_AHB1ENR_GPIOCEN 0x00000004U |
Definition at line 5088 of file stm32f407xx.h.
| #define RCC_AHB1ENR_GPIODEN 0x00000008U |
Definition at line 5089 of file stm32f407xx.h.
| #define RCC_AHB1ENR_GPIOEEN 0x00000010U |
Definition at line 5090 of file stm32f407xx.h.
| #define RCC_AHB1ENR_GPIOFEN 0x00000020U |
Definition at line 5091 of file stm32f407xx.h.
| #define RCC_AHB1ENR_GPIOGEN 0x00000040U |
Definition at line 5092 of file stm32f407xx.h.
| #define RCC_AHB1ENR_GPIOHEN 0x00000080U |
Definition at line 5093 of file stm32f407xx.h.
| #define RCC_AHB1ENR_GPIOIEN 0x00000100U |
Definition at line 5094 of file stm32f407xx.h.
| #define RCC_AHB1ENR_OTGHSEN 0x20000000U |
Definition at line 5105 of file stm32f407xx.h.
| #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U |
Definition at line 5106 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U |
Definition at line 5173 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_CRCLPEN 0x00001000U |
Definition at line 5169 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U |
Definition at line 5174 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U |
Definition at line 5175 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U |
Definition at line 5176 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U |
Definition at line 5179 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U |
Definition at line 5178 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U |
Definition at line 5177 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U |
Definition at line 5170 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U |
Definition at line 5160 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U |
Definition at line 5161 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U |
Definition at line 5162 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U |
Definition at line 5163 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U |
Definition at line 5164 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U |
Definition at line 5165 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U |
Definition at line 5166 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U |
Definition at line 5167 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U |
Definition at line 5168 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U |
Definition at line 5180 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U |
Definition at line 5181 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U |
Definition at line 5171 of file stm32f407xx.h.
| #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U |
Definition at line 5172 of file stm32f407xx.h.
| #define RCC_AHB1RSTR_CRCRST 0x00001000U |
Definition at line 5029 of file stm32f407xx.h.
| #define RCC_AHB1RSTR_DMA1RST 0x00200000U |
Definition at line 5030 of file stm32f407xx.h.
| #define RCC_AHB1RSTR_DMA2RST 0x00400000U |
Definition at line 5031 of file stm32f407xx.h.
| #define RCC_AHB1RSTR_ETHMACRST 0x02000000U |
Definition at line 5032 of file stm32f407xx.h.
| #define RCC_AHB1RSTR_GPIOARST 0x00000001U |
Definition at line 5020 of file stm32f407xx.h.
| #define RCC_AHB1RSTR_GPIOBRST 0x00000002U |
Definition at line 5021 of file stm32f407xx.h.
| #define RCC_AHB1RSTR_GPIOCRST 0x00000004U |
Definition at line 5022 of file stm32f407xx.h.
| #define RCC_AHB1RSTR_GPIODRST 0x00000008U |
Definition at line 5023 of file stm32f407xx.h.
| #define RCC_AHB1RSTR_GPIOERST 0x00000010U |
Definition at line 5024 of file stm32f407xx.h.
| #define RCC_AHB1RSTR_GPIOFRST 0x00000020U |
Definition at line 5025 of file stm32f407xx.h.
| #define RCC_AHB1RSTR_GPIOGRST 0x00000040U |
Definition at line 5026 of file stm32f407xx.h.
| #define RCC_AHB1RSTR_GPIOHRST 0x00000080U |
Definition at line 5027 of file stm32f407xx.h.
| #define RCC_AHB1RSTR_GPIOIRST 0x00000100U |
Definition at line 5028 of file stm32f407xx.h.
| #define RCC_AHB1RSTR_OTGHRST 0x20000000U |
Definition at line 5033 of file stm32f407xx.h.
| #define RCC_AHB2ENR_DCMIEN 0x00000001U |
Definition at line 5109 of file stm32f407xx.h.
| #define RCC_AHB2ENR_OTGFSEN 0x00000080U |
Definition at line 5111 of file stm32f407xx.h.
| #define RCC_AHB2ENR_RNGEN 0x00000040U |
Definition at line 5110 of file stm32f407xx.h.
| #define RCC_AHB2LPENR_DCMILPEN 0x00000001U |
Definition at line 5184 of file stm32f407xx.h.
| #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U |
Definition at line 5186 of file stm32f407xx.h.
| #define RCC_AHB2LPENR_RNGLPEN 0x00000040U |
Definition at line 5185 of file stm32f407xx.h.
| #define RCC_AHB2RSTR_DCMIRST 0x00000001U |
Definition at line 5036 of file stm32f407xx.h.
| #define RCC_AHB2RSTR_OTGFSRST 0x00000080U |
Definition at line 5038 of file stm32f407xx.h.
| #define RCC_AHB2RSTR_RNGRST 0x00000040U |
Definition at line 5037 of file stm32f407xx.h.
| #define RCC_AHB3ENR_FSMCEN 0x00000001U |
Definition at line 5115 of file stm32f407xx.h.
| #define RCC_AHB3LPENR_FSMCLPEN 0x00000001U |
Definition at line 5190 of file stm32f407xx.h.
| #define RCC_AHB3RSTR_FSMCRST 0x00000001U |
Definition at line 5042 of file stm32f407xx.h.
| #define RCC_APB1ENR_CAN1EN 0x02000000U |
Definition at line 5137 of file stm32f407xx.h.
| #define RCC_APB1ENR_CAN2EN 0x04000000U |
Definition at line 5138 of file stm32f407xx.h.
| #define RCC_APB1ENR_DACEN 0x20000000U |
Definition at line 5140 of file stm32f407xx.h.
| #define RCC_APB1ENR_I2C1EN 0x00200000U |
Definition at line 5134 of file stm32f407xx.h.
| #define RCC_APB1ENR_I2C2EN 0x00400000U |
Definition at line 5135 of file stm32f407xx.h.
| #define RCC_APB1ENR_I2C3EN 0x00800000U |
Definition at line 5136 of file stm32f407xx.h.
| #define RCC_APB1ENR_PWREN 0x10000000U |
Definition at line 5139 of file stm32f407xx.h.
| #define RCC_APB1ENR_SPI2EN 0x00004000U |
Definition at line 5128 of file stm32f407xx.h.
| #define RCC_APB1ENR_SPI3EN 0x00008000U |
Definition at line 5129 of file stm32f407xx.h.
| #define RCC_APB1ENR_TIM12EN 0x00000040U |
Definition at line 5124 of file stm32f407xx.h.
| #define RCC_APB1ENR_TIM13EN 0x00000080U |
Definition at line 5125 of file stm32f407xx.h.
| #define RCC_APB1ENR_TIM14EN 0x00000100U |
Definition at line 5126 of file stm32f407xx.h.
| #define RCC_APB1ENR_TIM2EN 0x00000001U |
Definition at line 5118 of file stm32f407xx.h.
| #define RCC_APB1ENR_TIM3EN 0x00000002U |
Definition at line 5119 of file stm32f407xx.h.
| #define RCC_APB1ENR_TIM4EN 0x00000004U |
Definition at line 5120 of file stm32f407xx.h.
| #define RCC_APB1ENR_TIM5EN 0x00000008U |
Definition at line 5121 of file stm32f407xx.h.
| #define RCC_APB1ENR_TIM6EN 0x00000010U |
Definition at line 5122 of file stm32f407xx.h.
| #define RCC_APB1ENR_TIM7EN 0x00000020U |
Definition at line 5123 of file stm32f407xx.h.
| #define RCC_APB1ENR_UART4EN 0x00080000U |
Definition at line 5132 of file stm32f407xx.h.
| #define RCC_APB1ENR_UART5EN 0x00100000U |
Definition at line 5133 of file stm32f407xx.h.
| #define RCC_APB1ENR_USART2EN 0x00020000U |
Definition at line 5130 of file stm32f407xx.h.
| #define RCC_APB1ENR_USART3EN 0x00040000U |
Definition at line 5131 of file stm32f407xx.h.
| #define RCC_APB1ENR_WWDGEN 0x00000800U |
Definition at line 5127 of file stm32f407xx.h.
| #define RCC_APB1LPENR_CAN1LPEN 0x02000000U |
Definition at line 5212 of file stm32f407xx.h.
| #define RCC_APB1LPENR_CAN2LPEN 0x04000000U |
Definition at line 5213 of file stm32f407xx.h.
| #define RCC_APB1LPENR_DACLPEN 0x20000000U |
Definition at line 5215 of file stm32f407xx.h.
| #define RCC_APB1LPENR_I2C1LPEN 0x00200000U |
Definition at line 5209 of file stm32f407xx.h.
| #define RCC_APB1LPENR_I2C2LPEN 0x00400000U |
Definition at line 5210 of file stm32f407xx.h.
| #define RCC_APB1LPENR_I2C3LPEN 0x00800000U |
Definition at line 5211 of file stm32f407xx.h.
| #define RCC_APB1LPENR_PWRLPEN 0x10000000U |
Definition at line 5214 of file stm32f407xx.h.
| #define RCC_APB1LPENR_SPI2LPEN 0x00004000U |
Definition at line 5203 of file stm32f407xx.h.
| #define RCC_APB1LPENR_SPI3LPEN 0x00008000U |
Definition at line 5204 of file stm32f407xx.h.
| #define RCC_APB1LPENR_TIM12LPEN 0x00000040U |
Definition at line 5199 of file stm32f407xx.h.
| #define RCC_APB1LPENR_TIM13LPEN 0x00000080U |
Definition at line 5200 of file stm32f407xx.h.
| #define RCC_APB1LPENR_TIM14LPEN 0x00000100U |
Definition at line 5201 of file stm32f407xx.h.
| #define RCC_APB1LPENR_TIM2LPEN 0x00000001U |
Definition at line 5193 of file stm32f407xx.h.
| #define RCC_APB1LPENR_TIM3LPEN 0x00000002U |
Definition at line 5194 of file stm32f407xx.h.
| #define RCC_APB1LPENR_TIM4LPEN 0x00000004U |
Definition at line 5195 of file stm32f407xx.h.
| #define RCC_APB1LPENR_TIM5LPEN 0x00000008U |
Definition at line 5196 of file stm32f407xx.h.
| #define RCC_APB1LPENR_TIM6LPEN 0x00000010U |
Definition at line 5197 of file stm32f407xx.h.
| #define RCC_APB1LPENR_TIM7LPEN 0x00000020U |
Definition at line 5198 of file stm32f407xx.h.
| #define RCC_APB1LPENR_UART4LPEN 0x00080000U |
Definition at line 5207 of file stm32f407xx.h.
| #define RCC_APB1LPENR_UART5LPEN 0x00100000U |
Definition at line 5208 of file stm32f407xx.h.
| #define RCC_APB1LPENR_USART2LPEN 0x00020000U |
Definition at line 5205 of file stm32f407xx.h.
| #define RCC_APB1LPENR_USART3LPEN 0x00040000U |
Definition at line 5206 of file stm32f407xx.h.
| #define RCC_APB1LPENR_WWDGLPEN 0x00000800U |
Definition at line 5202 of file stm32f407xx.h.
| #define RCC_APB1RSTR_CAN1RST 0x02000000U |
Definition at line 5064 of file stm32f407xx.h.
| #define RCC_APB1RSTR_CAN2RST 0x04000000U |
Definition at line 5065 of file stm32f407xx.h.
| #define RCC_APB1RSTR_DACRST 0x20000000U |
Definition at line 5067 of file stm32f407xx.h.
| #define RCC_APB1RSTR_I2C1RST 0x00200000U |
Definition at line 5061 of file stm32f407xx.h.
| #define RCC_APB1RSTR_I2C2RST 0x00400000U |
Definition at line 5062 of file stm32f407xx.h.
| #define RCC_APB1RSTR_I2C3RST 0x00800000U |
Definition at line 5063 of file stm32f407xx.h.
| #define RCC_APB1RSTR_PWRRST 0x10000000U |
Definition at line 5066 of file stm32f407xx.h.
| #define RCC_APB1RSTR_SPI2RST 0x00004000U |
Definition at line 5055 of file stm32f407xx.h.
| #define RCC_APB1RSTR_SPI3RST 0x00008000U |
Definition at line 5056 of file stm32f407xx.h.
| #define RCC_APB1RSTR_TIM12RST 0x00000040U |
Definition at line 5051 of file stm32f407xx.h.
| #define RCC_APB1RSTR_TIM13RST 0x00000080U |
Definition at line 5052 of file stm32f407xx.h.
| #define RCC_APB1RSTR_TIM14RST 0x00000100U |
Definition at line 5053 of file stm32f407xx.h.
| #define RCC_APB1RSTR_TIM2RST 0x00000001U |
Definition at line 5045 of file stm32f407xx.h.
| #define RCC_APB1RSTR_TIM3RST 0x00000002U |
Definition at line 5046 of file stm32f407xx.h.
| #define RCC_APB1RSTR_TIM4RST 0x00000004U |
Definition at line 5047 of file stm32f407xx.h.
| #define RCC_APB1RSTR_TIM5RST 0x00000008U |
Definition at line 5048 of file stm32f407xx.h.
| #define RCC_APB1RSTR_TIM6RST 0x00000010U |
Definition at line 5049 of file stm32f407xx.h.
| #define RCC_APB1RSTR_TIM7RST 0x00000020U |
Definition at line 5050 of file stm32f407xx.h.
| #define RCC_APB1RSTR_UART4RST 0x00080000U |
Definition at line 5059 of file stm32f407xx.h.
| #define RCC_APB1RSTR_UART5RST 0x00100000U |
Definition at line 5060 of file stm32f407xx.h.
| #define RCC_APB1RSTR_USART2RST 0x00020000U |
Definition at line 5057 of file stm32f407xx.h.
| #define RCC_APB1RSTR_USART3RST 0x00040000U |
Definition at line 5058 of file stm32f407xx.h.
| #define RCC_APB1RSTR_WWDGRST 0x00000800U |
Definition at line 5054 of file stm32f407xx.h.
| #define RCC_APB2ENR_ADC1EN 0x00000100U |
Definition at line 5147 of file stm32f407xx.h.
| #define RCC_APB2ENR_ADC2EN 0x00000200U |
Definition at line 5148 of file stm32f407xx.h.
| #define RCC_APB2ENR_ADC3EN 0x00000400U |
Definition at line 5149 of file stm32f407xx.h.
| #define RCC_APB2ENR_SDIOEN 0x00000800U |
Definition at line 5150 of file stm32f407xx.h.
| #define RCC_APB2ENR_SPI1EN 0x00001000U |
Definition at line 5151 of file stm32f407xx.h.
| #define RCC_APB2ENR_SPI5EN 0x00100000U |
Definition at line 5156 of file stm32f407xx.h.
| #define RCC_APB2ENR_SPI6EN 0x00200000U |
Definition at line 5157 of file stm32f407xx.h.
| #define RCC_APB2ENR_SYSCFGEN 0x00004000U |
Definition at line 5152 of file stm32f407xx.h.
| #define RCC_APB2ENR_TIM10EN 0x00020000U |
Definition at line 5154 of file stm32f407xx.h.
| #define RCC_APB2ENR_TIM11EN 0x00040000U |
Definition at line 5155 of file stm32f407xx.h.
| #define RCC_APB2ENR_TIM1EN 0x00000001U |
Definition at line 5143 of file stm32f407xx.h.
| #define RCC_APB2ENR_TIM8EN 0x00000002U |
Definition at line 5144 of file stm32f407xx.h.
| #define RCC_APB2ENR_TIM9EN 0x00010000U |
Definition at line 5153 of file stm32f407xx.h.
| #define RCC_APB2ENR_USART1EN 0x00000010U |
Definition at line 5145 of file stm32f407xx.h.
| #define RCC_APB2ENR_USART6EN 0x00000020U |
Definition at line 5146 of file stm32f407xx.h.
| #define RCC_APB2LPENR_ADC1LPEN 0x00000100U |
Definition at line 5222 of file stm32f407xx.h.
| #define RCC_APB2LPENR_ADC2LPEN 0x00000200U |
Definition at line 5223 of file stm32f407xx.h.
| #define RCC_APB2LPENR_ADC3LPEN 0x00000400U |
Definition at line 5224 of file stm32f407xx.h.
| #define RCC_APB2LPENR_SDIOLPEN 0x00000800U |
Definition at line 5225 of file stm32f407xx.h.
| #define RCC_APB2LPENR_SPI1LPEN 0x00001000U |
Definition at line 5226 of file stm32f407xx.h.
| #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U |
Definition at line 5227 of file stm32f407xx.h.
| #define RCC_APB2LPENR_TIM10LPEN 0x00020000U |
Definition at line 5229 of file stm32f407xx.h.
| #define RCC_APB2LPENR_TIM11LPEN 0x00040000U |
Definition at line 5230 of file stm32f407xx.h.
| #define RCC_APB2LPENR_TIM1LPEN 0x00000001U |
Definition at line 5218 of file stm32f407xx.h.
| #define RCC_APB2LPENR_TIM8LPEN 0x00000002U |
Definition at line 5219 of file stm32f407xx.h.
| #define RCC_APB2LPENR_TIM9LPEN 0x00010000U |
Definition at line 5228 of file stm32f407xx.h.
| #define RCC_APB2LPENR_USART1LPEN 0x00000010U |
Definition at line 5220 of file stm32f407xx.h.
| #define RCC_APB2LPENR_USART6LPEN 0x00000020U |
Definition at line 5221 of file stm32f407xx.h.
| #define RCC_APB2RSTR_ADCRST 0x00000100U |
Definition at line 5074 of file stm32f407xx.h.
| #define RCC_APB2RSTR_SDIORST 0x00000800U |
Definition at line 5075 of file stm32f407xx.h.
| #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST |
Definition at line 5083 of file stm32f407xx.h.
| #define RCC_APB2RSTR_SPI1RST 0x00001000U |
Definition at line 5076 of file stm32f407xx.h.
| #define RCC_APB2RSTR_SYSCFGRST 0x00004000U |
Definition at line 5077 of file stm32f407xx.h.
| #define RCC_APB2RSTR_TIM10RST 0x00020000U |
Definition at line 5079 of file stm32f407xx.h.
| #define RCC_APB2RSTR_TIM11RST 0x00040000U |
Definition at line 5080 of file stm32f407xx.h.
| #define RCC_APB2RSTR_TIM1RST 0x00000001U |
Definition at line 5070 of file stm32f407xx.h.
| #define RCC_APB2RSTR_TIM8RST 0x00000002U |
Definition at line 5071 of file stm32f407xx.h.
| #define RCC_APB2RSTR_TIM9RST 0x00010000U |
Definition at line 5078 of file stm32f407xx.h.
| #define RCC_APB2RSTR_USART1RST 0x00000010U |
Definition at line 5072 of file stm32f407xx.h.
| #define RCC_APB2RSTR_USART6RST 0x00000020U |
Definition at line 5073 of file stm32f407xx.h.
| #define RCC_BDCR_BDRST 0x00010000U |
Definition at line 5242 of file stm32f407xx.h.
| #define RCC_BDCR_LSEBYP 0x00000004U |
Definition at line 5235 of file stm32f407xx.h.
| #define RCC_BDCR_LSEON 0x00000001U |
Definition at line 5233 of file stm32f407xx.h.
| #define RCC_BDCR_LSERDY 0x00000002U |
Definition at line 5234 of file stm32f407xx.h.
| #define RCC_BDCR_RTCEN 0x00008000U |
Definition at line 5241 of file stm32f407xx.h.
| #define RCC_BDCR_RTCSEL 0x00000300U |
Definition at line 5237 of file stm32f407xx.h.
| #define RCC_BDCR_RTCSEL_0 0x00000100U |
Definition at line 5238 of file stm32f407xx.h.
| #define RCC_BDCR_RTCSEL_1 0x00000200U |
Definition at line 5239 of file stm32f407xx.h.
| #define RCC_CFGR_HPRE 0x000000F0U |
HPRE[3:0] bits (AHB prescaler)
Definition at line 4925 of file stm32f407xx.h.
| #define RCC_CFGR_HPRE_0 0x00000010U |
Bit 0
Definition at line 4926 of file stm32f407xx.h.
| #define RCC_CFGR_HPRE_1 0x00000020U |
Bit 1
Definition at line 4927 of file stm32f407xx.h.
| #define RCC_CFGR_HPRE_2 0x00000040U |
Bit 2
Definition at line 4928 of file stm32f407xx.h.
| #define RCC_CFGR_HPRE_3 0x00000080U |
Bit 3
Definition at line 4929 of file stm32f407xx.h.
| #define RCC_CFGR_HPRE_DIV1 0x00000000U |
SYSCLK not divided
Definition at line 4931 of file stm32f407xx.h.
| #define RCC_CFGR_HPRE_DIV128 0x000000D0U |
SYSCLK divided by 128
Definition at line 4937 of file stm32f407xx.h.
| #define RCC_CFGR_HPRE_DIV16 0x000000B0U |
SYSCLK divided by 16
Definition at line 4935 of file stm32f407xx.h.
| #define RCC_CFGR_HPRE_DIV2 0x00000080U |
SYSCLK divided by 2
Definition at line 4932 of file stm32f407xx.h.
| #define RCC_CFGR_HPRE_DIV256 0x000000E0U |
SYSCLK divided by 256
Definition at line 4938 of file stm32f407xx.h.
| #define RCC_CFGR_HPRE_DIV4 0x00000090U |
SYSCLK divided by 4
Definition at line 4933 of file stm32f407xx.h.
| #define RCC_CFGR_HPRE_DIV512 0x000000F0U |
SYSCLK divided by 512 PPRE1 configuration
Definition at line 4941 of file stm32f407xx.h.
| #define RCC_CFGR_HPRE_DIV64 0x000000C0U |
SYSCLK divided by 64
Definition at line 4936 of file stm32f407xx.h.
| #define RCC_CFGR_HPRE_DIV8 0x000000A0U |
SYSCLK divided by 8
Definition at line 4934 of file stm32f407xx.h.
| #define RCC_CFGR_I2SSRC 0x00800000U |
Definition at line 4978 of file stm32f407xx.h.
| #define RCC_CFGR_MCO1 0x00600000U |
Definition at line 4974 of file stm32f407xx.h.
| #define RCC_CFGR_MCO1_0 0x00200000U |
Definition at line 4975 of file stm32f407xx.h.
| #define RCC_CFGR_MCO1_1 0x00400000U |
Definition at line 4976 of file stm32f407xx.h.
| #define RCC_CFGR_MCO1PRE 0x07000000U |
Definition at line 4980 of file stm32f407xx.h.
| #define RCC_CFGR_MCO1PRE_0 0x01000000U |
Definition at line 4981 of file stm32f407xx.h.
| #define RCC_CFGR_MCO1PRE_1 0x02000000U |
Definition at line 4982 of file stm32f407xx.h.
| #define RCC_CFGR_MCO1PRE_2 0x04000000U |
Definition at line 4983 of file stm32f407xx.h.
| #define RCC_CFGR_MCO2 0xC0000000U |
Definition at line 4990 of file stm32f407xx.h.
| #define RCC_CFGR_MCO2_0 0x40000000U |
Definition at line 4991 of file stm32f407xx.h.
| #define RCC_CFGR_MCO2_1 0x80000000U |
Definition at line 4992 of file stm32f407xx.h.
| #define RCC_CFGR_MCO2PRE 0x38000000U |
Definition at line 4985 of file stm32f407xx.h.
| #define RCC_CFGR_MCO2PRE_0 0x08000000U |
Definition at line 4986 of file stm32f407xx.h.
| #define RCC_CFGR_MCO2PRE_1 0x10000000U |
Definition at line 4987 of file stm32f407xx.h.
| #define RCC_CFGR_MCO2PRE_2 0x20000000U |
Definition at line 4988 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE1 0x00001C00U |
PRE1[2:0] bits (APB1 prescaler)
Definition at line 4942 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE1_0 0x00000400U |
Bit 0
Definition at line 4943 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE1_1 0x00000800U |
Bit 1
Definition at line 4944 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE1_2 0x00001000U |
Bit 2
Definition at line 4945 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE1_DIV1 0x00000000U |
HCLK not divided
Definition at line 4947 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE1_DIV16 0x00001C00U |
HCLK divided by 16 PPRE2 configuration
Definition at line 4953 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE1_DIV2 0x00001000U |
HCLK divided by 2
Definition at line 4948 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE1_DIV4 0x00001400U |
HCLK divided by 4
Definition at line 4949 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE1_DIV8 0x00001800U |
HCLK divided by 8
Definition at line 4950 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE2 0x0000E000U |
PRE2[2:0] bits (APB2 prescaler)
Definition at line 4954 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE2_0 0x00002000U |
Bit 0
Definition at line 4955 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE2_1 0x00004000U |
Bit 1
Definition at line 4956 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE2_2 0x00008000U |
Bit 2
Definition at line 4957 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE2_DIV1 0x00000000U |
HCLK not divided
Definition at line 4959 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE2_DIV16 0x0000E000U |
HCLK divided by 16 RTCPRE configuration
Definition at line 4965 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE2_DIV2 0x00008000U |
HCLK divided by 2
Definition at line 4960 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE2_DIV4 0x0000A000U |
HCLK divided by 4
Definition at line 4961 of file stm32f407xx.h.
| #define RCC_CFGR_PPRE2_DIV8 0x0000C000U |
HCLK divided by 8
Definition at line 4962 of file stm32f407xx.h.
| #define RCC_CFGR_RTCPRE 0x001F0000U |
Definition at line 4966 of file stm32f407xx.h.
| #define RCC_CFGR_RTCPRE_0 0x00010000U |
Definition at line 4967 of file stm32f407xx.h.
| #define RCC_CFGR_RTCPRE_1 0x00020000U |
Definition at line 4968 of file stm32f407xx.h.
| #define RCC_CFGR_RTCPRE_2 0x00040000U |
Definition at line 4969 of file stm32f407xx.h.
| #define RCC_CFGR_RTCPRE_3 0x00080000U |
Definition at line 4970 of file stm32f407xx.h.
| #define RCC_CFGR_RTCPRE_4 0x00100000U |
MCO1 configuration
Definition at line 4973 of file stm32f407xx.h.
| #define RCC_CFGR_SW 0x00000003U |
< SW configuration SW[1:0] bits (System clock Switch)
Definition at line 4907 of file stm32f407xx.h.
| #define RCC_CFGR_SW_0 0x00000001U |
Bit 0
Definition at line 4908 of file stm32f407xx.h.
| #define RCC_CFGR_SW_1 0x00000002U |
Bit 1
Definition at line 4909 of file stm32f407xx.h.
| #define RCC_CFGR_SW_HSE 0x00000001U |
HSE selected as system clock
Definition at line 4912 of file stm32f407xx.h.
| #define RCC_CFGR_SW_HSI 0x00000000U |
HSI selected as system clock
Definition at line 4911 of file stm32f407xx.h.
| #define RCC_CFGR_SW_PLL 0x00000002U |
PLL selected as system clock SWS configuration
Definition at line 4915 of file stm32f407xx.h.
| #define RCC_CFGR_SWS 0x0000000CU |
SWS[1:0] bits (System Clock Switch Status)
Definition at line 4916 of file stm32f407xx.h.
| #define RCC_CFGR_SWS_0 0x00000004U |
Bit 0
Definition at line 4917 of file stm32f407xx.h.
| #define RCC_CFGR_SWS_1 0x00000008U |
Bit 1
Definition at line 4918 of file stm32f407xx.h.
| #define RCC_CFGR_SWS_HSE 0x00000004U |
HSE oscillator used as system clock
Definition at line 4921 of file stm32f407xx.h.
| #define RCC_CFGR_SWS_HSI 0x00000000U |
HSI oscillator used as system clock
Definition at line 4920 of file stm32f407xx.h.
| #define RCC_CFGR_SWS_PLL 0x00000008U |
PLL used as system clock HPRE configuration
Definition at line 4924 of file stm32f407xx.h.
| #define RCC_CIR_CSSC 0x00800000U |
Definition at line 5017 of file stm32f407xx.h.
| #define RCC_CIR_CSSF 0x00000080U |
Definition at line 5002 of file stm32f407xx.h.
| #define RCC_CIR_HSERDYC 0x00080000U |
Definition at line 5013 of file stm32f407xx.h.
| #define RCC_CIR_HSERDYF 0x00000008U |
Definition at line 4998 of file stm32f407xx.h.
| #define RCC_CIR_HSERDYIE 0x00000800U |
Definition at line 5006 of file stm32f407xx.h.
| #define RCC_CIR_HSIRDYC 0x00040000U |
Definition at line 5012 of file stm32f407xx.h.
| #define RCC_CIR_HSIRDYF 0x00000004U |
Definition at line 4997 of file stm32f407xx.h.
| #define RCC_CIR_HSIRDYIE 0x00000400U |
Definition at line 5005 of file stm32f407xx.h.
| #define RCC_CIR_LSERDYC 0x00020000U |
Definition at line 5011 of file stm32f407xx.h.
| #define RCC_CIR_LSERDYF 0x00000002U |
Definition at line 4996 of file stm32f407xx.h.
| #define RCC_CIR_LSERDYIE 0x00000200U |
Definition at line 5004 of file stm32f407xx.h.
| #define RCC_CIR_LSIRDYC 0x00010000U |
Definition at line 5010 of file stm32f407xx.h.
| #define RCC_CIR_LSIRDYF 0x00000001U |
Definition at line 4995 of file stm32f407xx.h.
| #define RCC_CIR_LSIRDYIE 0x00000100U |
Definition at line 5003 of file stm32f407xx.h.
| #define RCC_CIR_PLLI2SRDYC 0x00200000U |
Definition at line 5015 of file stm32f407xx.h.
| #define RCC_CIR_PLLI2SRDYF 0x00000020U |
Definition at line 5000 of file stm32f407xx.h.
| #define RCC_CIR_PLLI2SRDYIE 0x00002000U |
Definition at line 5008 of file stm32f407xx.h.
| #define RCC_CIR_PLLRDYC 0x00100000U |
Definition at line 5014 of file stm32f407xx.h.
| #define RCC_CIR_PLLRDYF 0x00000010U |
Definition at line 4999 of file stm32f407xx.h.
| #define RCC_CIR_PLLRDYIE 0x00001000U |
Definition at line 5007 of file stm32f407xx.h.
| #define RCC_CR_CSSON 0x00080000U |
Definition at line 4865 of file stm32f407xx.h.
| #define RCC_CR_HSEBYP 0x00040000U |
Definition at line 4864 of file stm32f407xx.h.
| #define RCC_CR_HSEON 0x00010000U |
Definition at line 4862 of file stm32f407xx.h.
| #define RCC_CR_HSERDY 0x00020000U |
Definition at line 4863 of file stm32f407xx.h.
| #define RCC_CR_HSICAL 0x0000FF00U |
Definition at line 4852 of file stm32f407xx.h.
| #define RCC_CR_HSICAL_0 0x00000100U |
Bit 0
Definition at line 4853 of file stm32f407xx.h.
| #define RCC_CR_HSICAL_1 0x00000200U |
Bit 1
Definition at line 4854 of file stm32f407xx.h.
| #define RCC_CR_HSICAL_2 0x00000400U |
Bit 2
Definition at line 4855 of file stm32f407xx.h.
| #define RCC_CR_HSICAL_3 0x00000800U |
Bit 3
Definition at line 4856 of file stm32f407xx.h.
| #define RCC_CR_HSICAL_4 0x00001000U |
Bit 4
Definition at line 4857 of file stm32f407xx.h.
| #define RCC_CR_HSICAL_5 0x00002000U |
Bit 5
Definition at line 4858 of file stm32f407xx.h.
| #define RCC_CR_HSICAL_6 0x00004000U |
Bit 6
Definition at line 4859 of file stm32f407xx.h.
| #define RCC_CR_HSICAL_7 0x00008000U |
Bit 7
Definition at line 4860 of file stm32f407xx.h.
| #define RCC_CR_HSION 0x00000001U |
Definition at line 4842 of file stm32f407xx.h.
| #define RCC_CR_HSIRDY 0x00000002U |
Definition at line 4843 of file stm32f407xx.h.
| #define RCC_CR_HSITRIM 0x000000F8U |
Definition at line 4845 of file stm32f407xx.h.
| #define RCC_CR_HSITRIM_0 0x00000008U |
Bit 0
Definition at line 4846 of file stm32f407xx.h.
| #define RCC_CR_HSITRIM_1 0x00000010U |
Bit 1
Definition at line 4847 of file stm32f407xx.h.
| #define RCC_CR_HSITRIM_2 0x00000020U |
Bit 2
Definition at line 4848 of file stm32f407xx.h.
| #define RCC_CR_HSITRIM_3 0x00000040U |
Bit 3
Definition at line 4849 of file stm32f407xx.h.
| #define RCC_CR_HSITRIM_4 0x00000080U |
Bit 4
Definition at line 4850 of file stm32f407xx.h.
| #define RCC_CR_PLLI2SON 0x04000000U |
Definition at line 4868 of file stm32f407xx.h.
| #define RCC_CR_PLLI2SRDY 0x08000000U |
Definition at line 4869 of file stm32f407xx.h.
| #define RCC_CR_PLLON 0x01000000U |
Definition at line 4866 of file stm32f407xx.h.
| #define RCC_CR_PLLRDY 0x02000000U |
Definition at line 4867 of file stm32f407xx.h.
| #define RCC_CSR_BORRSTF 0x02000000U |
Definition at line 5248 of file stm32f407xx.h.
| #define RCC_CSR_LPWRRSTF 0x80000000U |
Definition at line 5254 of file stm32f407xx.h.
| #define RCC_CSR_LSION 0x00000001U |
Definition at line 5245 of file stm32f407xx.h.
| #define RCC_CSR_LSIRDY 0x00000002U |
Definition at line 5246 of file stm32f407xx.h.
| #define RCC_CSR_PADRSTF 0x04000000U |
Definition at line 5249 of file stm32f407xx.h.
| #define RCC_CSR_PORRSTF 0x08000000U |
Definition at line 5250 of file stm32f407xx.h.
| #define RCC_CSR_RMVF 0x01000000U |
Definition at line 5247 of file stm32f407xx.h.
| #define RCC_CSR_SFTRSTF 0x10000000U |
Definition at line 5251 of file stm32f407xx.h.
| #define RCC_CSR_WDGRSTF 0x20000000U |
Definition at line 5252 of file stm32f407xx.h.
| #define RCC_CSR_WWDGRSTF 0x40000000U |
Definition at line 5253 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLM 0x0000003FU |
Definition at line 4872 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLM_0 0x00000001U |
Definition at line 4873 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLM_1 0x00000002U |
Definition at line 4874 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLM_2 0x00000004U |
Definition at line 4875 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLM_3 0x00000008U |
Definition at line 4876 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLM_4 0x00000010U |
Definition at line 4877 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLM_5 0x00000020U |
Definition at line 4878 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLN 0x00007FC0U |
Definition at line 4880 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLN_0 0x00000040U |
Definition at line 4881 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLN_1 0x00000080U |
Definition at line 4882 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLN_2 0x00000100U |
Definition at line 4883 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLN_3 0x00000200U |
Definition at line 4884 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLN_4 0x00000400U |
Definition at line 4885 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLN_5 0x00000800U |
Definition at line 4886 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLN_6 0x00001000U |
Definition at line 4887 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLN_7 0x00002000U |
Definition at line 4888 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLN_8 0x00004000U |
Definition at line 4889 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLP 0x00030000U |
Definition at line 4891 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLP_0 0x00010000U |
Definition at line 4892 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLP_1 0x00020000U |
Definition at line 4893 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLQ 0x0F000000U |
Definition at line 4899 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLQ_0 0x01000000U |
Definition at line 4900 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLQ_1 0x02000000U |
Definition at line 4901 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLQ_2 0x04000000U |
Definition at line 4902 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLQ_3 0x08000000U |
Definition at line 4903 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLSRC 0x00400000U |
Definition at line 4895 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U |
Definition at line 4896 of file stm32f407xx.h.
| #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U |
Definition at line 4897 of file stm32f407xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U |
Definition at line 5263 of file stm32f407xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U |
Definition at line 5264 of file stm32f407xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U |
Definition at line 5265 of file stm32f407xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U |
Definition at line 5266 of file stm32f407xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U |
Definition at line 5267 of file stm32f407xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U |
Definition at line 5268 of file stm32f407xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U |
Definition at line 5269 of file stm32f407xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U |
Definition at line 5270 of file stm32f407xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U |
Definition at line 5271 of file stm32f407xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U |
Definition at line 5272 of file stm32f407xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U |
Definition at line 5274 of file stm32f407xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U |
Definition at line 5275 of file stm32f407xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U |
Definition at line 5276 of file stm32f407xx.h.
| #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U |
Definition at line 5277 of file stm32f407xx.h.
| #define RCC_SSCGR_INCSTEP 0x0FFFE000U |
Definition at line 5258 of file stm32f407xx.h.
| #define RCC_SSCGR_MODPER 0x00001FFFU |
Definition at line 5257 of file stm32f407xx.h.
| #define RCC_SSCGR_SPREADSEL 0x40000000U |
Definition at line 5259 of file stm32f407xx.h.
| #define RCC_SSCGR_SSCGEN 0x80000000U |
Definition at line 5260 of file stm32f407xx.h.
| #define RNG_CR_IE 0x00000008U |
Definition at line 5286 of file stm32f407xx.h.
| #define RNG_CR_RNGEN 0x00000004U |
Definition at line 5285 of file stm32f407xx.h.
| #define RNG_SR_CECS 0x00000002U |
Definition at line 5290 of file stm32f407xx.h.
| #define RNG_SR_CEIS 0x00000020U |
Definition at line 5292 of file stm32f407xx.h.
| #define RNG_SR_DRDY 0x00000001U |
Definition at line 5289 of file stm32f407xx.h.
| #define RNG_SR_SECS 0x00000004U |
Definition at line 5291 of file stm32f407xx.h.
| #define RNG_SR_SEIS 0x00000040U |
Definition at line 5293 of file stm32f407xx.h.
| #define RTC_ALRMAR_DT 0x30000000U |
Definition at line 5419 of file stm32f407xx.h.
| #define RTC_ALRMAR_DT_0 0x10000000U |
Definition at line 5420 of file stm32f407xx.h.
| #define RTC_ALRMAR_DT_1 0x20000000U |
Definition at line 5421 of file stm32f407xx.h.
| #define RTC_ALRMAR_DU 0x0F000000U |
Definition at line 5422 of file stm32f407xx.h.
| #define RTC_ALRMAR_DU_0 0x01000000U |
Definition at line 5423 of file stm32f407xx.h.
| #define RTC_ALRMAR_DU_1 0x02000000U |
Definition at line 5424 of file stm32f407xx.h.
| #define RTC_ALRMAR_DU_2 0x04000000U |
Definition at line 5425 of file stm32f407xx.h.
| #define RTC_ALRMAR_DU_3 0x08000000U |
Definition at line 5426 of file stm32f407xx.h.
| #define RTC_ALRMAR_HT 0x00300000U |
Definition at line 5429 of file stm32f407xx.h.
| #define RTC_ALRMAR_HT_0 0x00100000U |
Definition at line 5430 of file stm32f407xx.h.
| #define RTC_ALRMAR_HT_1 0x00200000U |
Definition at line 5431 of file stm32f407xx.h.
| #define RTC_ALRMAR_HU 0x000F0000U |
Definition at line 5432 of file stm32f407xx.h.
| #define RTC_ALRMAR_HU_0 0x00010000U |
Definition at line 5433 of file stm32f407xx.h.
| #define RTC_ALRMAR_HU_1 0x00020000U |
Definition at line 5434 of file stm32f407xx.h.
| #define RTC_ALRMAR_HU_2 0x00040000U |
Definition at line 5435 of file stm32f407xx.h.
| #define RTC_ALRMAR_HU_3 0x00080000U |
Definition at line 5436 of file stm32f407xx.h.
| #define RTC_ALRMAR_MNT 0x00007000U |
Definition at line 5438 of file stm32f407xx.h.
| #define RTC_ALRMAR_MNT_0 0x00001000U |
Definition at line 5439 of file stm32f407xx.h.
| #define RTC_ALRMAR_MNT_1 0x00002000U |
Definition at line 5440 of file stm32f407xx.h.
| #define RTC_ALRMAR_MNT_2 0x00004000U |
Definition at line 5441 of file stm32f407xx.h.
| #define RTC_ALRMAR_MNU 0x00000F00U |
Definition at line 5442 of file stm32f407xx.h.
| #define RTC_ALRMAR_MNU_0 0x00000100U |
Definition at line 5443 of file stm32f407xx.h.
| #define RTC_ALRMAR_MNU_1 0x00000200U |
Definition at line 5444 of file stm32f407xx.h.
| #define RTC_ALRMAR_MNU_2 0x00000400U |
Definition at line 5445 of file stm32f407xx.h.
| #define RTC_ALRMAR_MNU_3 0x00000800U |
Definition at line 5446 of file stm32f407xx.h.
| #define RTC_ALRMAR_MSK1 0x00000080U |
Definition at line 5447 of file stm32f407xx.h.
| #define RTC_ALRMAR_MSK2 0x00008000U |
Definition at line 5437 of file stm32f407xx.h.
| #define RTC_ALRMAR_MSK3 0x00800000U |
Definition at line 5427 of file stm32f407xx.h.
| #define RTC_ALRMAR_MSK4 0x80000000U |
Definition at line 5417 of file stm32f407xx.h.
| #define RTC_ALRMAR_PM 0x00400000U |
Definition at line 5428 of file stm32f407xx.h.
| #define RTC_ALRMAR_ST 0x00000070U |
Definition at line 5448 of file stm32f407xx.h.
| #define RTC_ALRMAR_ST_0 0x00000010U |
Definition at line 5449 of file stm32f407xx.h.
| #define RTC_ALRMAR_ST_1 0x00000020U |
Definition at line 5450 of file stm32f407xx.h.
| #define RTC_ALRMAR_ST_2 0x00000040U |
Definition at line 5451 of file stm32f407xx.h.
| #define RTC_ALRMAR_SU 0x0000000FU |
Definition at line 5452 of file stm32f407xx.h.
| #define RTC_ALRMAR_SU_0 0x00000001U |
Definition at line 5453 of file stm32f407xx.h.
| #define RTC_ALRMAR_SU_1 0x00000002U |
Definition at line 5454 of file stm32f407xx.h.
| #define RTC_ALRMAR_SU_2 0x00000004U |
Definition at line 5455 of file stm32f407xx.h.
| #define RTC_ALRMAR_SU_3 0x00000008U |
Definition at line 5456 of file stm32f407xx.h.
| #define RTC_ALRMAR_WDSEL 0x40000000U |
Definition at line 5418 of file stm32f407xx.h.
| #define RTC_ALRMASSR_MASKSS 0x0F000000U |
Definition at line 5600 of file stm32f407xx.h.
| #define RTC_ALRMASSR_MASKSS_0 0x01000000U |
Definition at line 5601 of file stm32f407xx.h.
| #define RTC_ALRMASSR_MASKSS_1 0x02000000U |
Definition at line 5602 of file stm32f407xx.h.
| #define RTC_ALRMASSR_MASKSS_2 0x04000000U |
Definition at line 5603 of file stm32f407xx.h.
| #define RTC_ALRMASSR_MASKSS_3 0x08000000U |
Definition at line 5604 of file stm32f407xx.h.
| #define RTC_ALRMASSR_SS 0x00007FFFU |
Definition at line 5605 of file stm32f407xx.h.
| #define RTC_ALRMBR_DT 0x30000000U |
Definition at line 5461 of file stm32f407xx.h.
| #define RTC_ALRMBR_DT_0 0x10000000U |
Definition at line 5462 of file stm32f407xx.h.
| #define RTC_ALRMBR_DT_1 0x20000000U |
Definition at line 5463 of file stm32f407xx.h.
| #define RTC_ALRMBR_DU 0x0F000000U |
Definition at line 5464 of file stm32f407xx.h.
| #define RTC_ALRMBR_DU_0 0x01000000U |
Definition at line 5465 of file stm32f407xx.h.
| #define RTC_ALRMBR_DU_1 0x02000000U |
Definition at line 5466 of file stm32f407xx.h.
| #define RTC_ALRMBR_DU_2 0x04000000U |
Definition at line 5467 of file stm32f407xx.h.
| #define RTC_ALRMBR_DU_3 0x08000000U |
Definition at line 5468 of file stm32f407xx.h.
| #define RTC_ALRMBR_HT 0x00300000U |
Definition at line 5471 of file stm32f407xx.h.
| #define RTC_ALRMBR_HT_0 0x00100000U |
Definition at line 5472 of file stm32f407xx.h.
| #define RTC_ALRMBR_HT_1 0x00200000U |
Definition at line 5473 of file stm32f407xx.h.
| #define RTC_ALRMBR_HU 0x000F0000U |
Definition at line 5474 of file stm32f407xx.h.
| #define RTC_ALRMBR_HU_0 0x00010000U |
Definition at line 5475 of file stm32f407xx.h.
| #define RTC_ALRMBR_HU_1 0x00020000U |
Definition at line 5476 of file stm32f407xx.h.
| #define RTC_ALRMBR_HU_2 0x00040000U |
Definition at line 5477 of file stm32f407xx.h.
| #define RTC_ALRMBR_HU_3 0x00080000U |
Definition at line 5478 of file stm32f407xx.h.
| #define RTC_ALRMBR_MNT 0x00007000U |
Definition at line 5480 of file stm32f407xx.h.
| #define RTC_ALRMBR_MNT_0 0x00001000U |
Definition at line 5481 of file stm32f407xx.h.
| #define RTC_ALRMBR_MNT_1 0x00002000U |
Definition at line 5482 of file stm32f407xx.h.
| #define RTC_ALRMBR_MNT_2 0x00004000U |
Definition at line 5483 of file stm32f407xx.h.
| #define RTC_ALRMBR_MNU 0x00000F00U |
Definition at line 5484 of file stm32f407xx.h.
| #define RTC_ALRMBR_MNU_0 0x00000100U |
Definition at line 5485 of file stm32f407xx.h.
| #define RTC_ALRMBR_MNU_1 0x00000200U |
Definition at line 5486 of file stm32f407xx.h.
| #define RTC_ALRMBR_MNU_2 0x00000400U |
Definition at line 5487 of file stm32f407xx.h.
| #define RTC_ALRMBR_MNU_3 0x00000800U |
Definition at line 5488 of file stm32f407xx.h.
| #define RTC_ALRMBR_MSK1 0x00000080U |
Definition at line 5489 of file stm32f407xx.h.
| #define RTC_ALRMBR_MSK2 0x00008000U |
Definition at line 5479 of file stm32f407xx.h.
| #define RTC_ALRMBR_MSK3 0x00800000U |
Definition at line 5469 of file stm32f407xx.h.
| #define RTC_ALRMBR_MSK4 0x80000000U |
Definition at line 5459 of file stm32f407xx.h.
| #define RTC_ALRMBR_PM 0x00400000U |
Definition at line 5470 of file stm32f407xx.h.
| #define RTC_ALRMBR_ST 0x00000070U |
Definition at line 5490 of file stm32f407xx.h.
| #define RTC_ALRMBR_ST_0 0x00000010U |
Definition at line 5491 of file stm32f407xx.h.
| #define RTC_ALRMBR_ST_1 0x00000020U |
Definition at line 5492 of file stm32f407xx.h.
| #define RTC_ALRMBR_ST_2 0x00000040U |
Definition at line 5493 of file stm32f407xx.h.
| #define RTC_ALRMBR_SU 0x0000000FU |
Definition at line 5494 of file stm32f407xx.h.
| #define RTC_ALRMBR_SU_0 0x00000001U |
Definition at line 5495 of file stm32f407xx.h.
| #define RTC_ALRMBR_SU_1 0x00000002U |
Definition at line 5496 of file stm32f407xx.h.
| #define RTC_ALRMBR_SU_2 0x00000004U |
Definition at line 5497 of file stm32f407xx.h.
| #define RTC_ALRMBR_SU_3 0x00000008U |
Definition at line 5498 of file stm32f407xx.h.
| #define RTC_ALRMBR_WDSEL 0x40000000U |
Definition at line 5460 of file stm32f407xx.h.
| #define RTC_ALRMBSSR_MASKSS 0x0F000000U |
Definition at line 5608 of file stm32f407xx.h.
| #define RTC_ALRMBSSR_MASKSS_0 0x01000000U |
Definition at line 5609 of file stm32f407xx.h.
| #define RTC_ALRMBSSR_MASKSS_1 0x02000000U |
Definition at line 5610 of file stm32f407xx.h.
| #define RTC_ALRMBSSR_MASKSS_2 0x04000000U |
Definition at line 5611 of file stm32f407xx.h.
| #define RTC_ALRMBSSR_MASKSS_3 0x08000000U |
Definition at line 5612 of file stm32f407xx.h.
| #define RTC_ALRMBSSR_SS 0x00007FFFU |
Definition at line 5613 of file stm32f407xx.h.
| #define RTC_BKP0R 0xFFFFFFFFU |
Definition at line 5616 of file stm32f407xx.h.
| #define RTC_BKP10R 0xFFFFFFFFU |
Definition at line 5646 of file stm32f407xx.h.
| #define RTC_BKP11R 0xFFFFFFFFU |
Definition at line 5649 of file stm32f407xx.h.
| #define RTC_BKP12R 0xFFFFFFFFU |
Definition at line 5652 of file stm32f407xx.h.
| #define RTC_BKP13R 0xFFFFFFFFU |
Definition at line 5655 of file stm32f407xx.h.
| #define RTC_BKP14R 0xFFFFFFFFU |
Definition at line 5658 of file stm32f407xx.h.
| #define RTC_BKP15R 0xFFFFFFFFU |
Definition at line 5661 of file stm32f407xx.h.
| #define RTC_BKP16R 0xFFFFFFFFU |
Definition at line 5664 of file stm32f407xx.h.
| #define RTC_BKP17R 0xFFFFFFFFU |
Definition at line 5667 of file stm32f407xx.h.
| #define RTC_BKP18R 0xFFFFFFFFU |
Definition at line 5670 of file stm32f407xx.h.
| #define RTC_BKP19R 0xFFFFFFFFU |
Definition at line 5673 of file stm32f407xx.h.
| #define RTC_BKP1R 0xFFFFFFFFU |
Definition at line 5619 of file stm32f407xx.h.
| #define RTC_BKP2R 0xFFFFFFFFU |
Definition at line 5622 of file stm32f407xx.h.
| #define RTC_BKP3R 0xFFFFFFFFU |
Definition at line 5625 of file stm32f407xx.h.
| #define RTC_BKP4R 0xFFFFFFFFU |
Definition at line 5628 of file stm32f407xx.h.
| #define RTC_BKP5R 0xFFFFFFFFU |
Definition at line 5631 of file stm32f407xx.h.
| #define RTC_BKP6R 0xFFFFFFFFU |
Definition at line 5634 of file stm32f407xx.h.
| #define RTC_BKP7R 0xFFFFFFFFU |
Definition at line 5637 of file stm32f407xx.h.
| #define RTC_BKP8R 0xFFFFFFFFU |
Definition at line 5640 of file stm32f407xx.h.
| #define RTC_BKP9R 0xFFFFFFFFU |
Definition at line 5643 of file stm32f407xx.h.
| #define RTC_CALIBR_DC 0x0000001FU |
Definition at line 5414 of file stm32f407xx.h.
| #define RTC_CALIBR_DCS 0x00000080U |
Definition at line 5413 of file stm32f407xx.h.
| #define RTC_CALR_CALM 0x000001FFU |
Definition at line 5566 of file stm32f407xx.h.
| #define RTC_CALR_CALM_0 0x00000001U |
Definition at line 5567 of file stm32f407xx.h.
| #define RTC_CALR_CALM_1 0x00000002U |
Definition at line 5568 of file stm32f407xx.h.
| #define RTC_CALR_CALM_2 0x00000004U |
Definition at line 5569 of file stm32f407xx.h.
| #define RTC_CALR_CALM_3 0x00000008U |
Definition at line 5570 of file stm32f407xx.h.
| #define RTC_CALR_CALM_4 0x00000010U |
Definition at line 5571 of file stm32f407xx.h.
| #define RTC_CALR_CALM_5 0x00000020U |
Definition at line 5572 of file stm32f407xx.h.
| #define RTC_CALR_CALM_6 0x00000040U |
Definition at line 5573 of file stm32f407xx.h.
| #define RTC_CALR_CALM_7 0x00000080U |
Definition at line 5574 of file stm32f407xx.h.
| #define RTC_CALR_CALM_8 0x00000100U |
Definition at line 5575 of file stm32f407xx.h.
| #define RTC_CALR_CALP 0x00008000U |
Definition at line 5563 of file stm32f407xx.h.
| #define RTC_CALR_CALW16 0x00002000U |
Definition at line 5565 of file stm32f407xx.h.
| #define RTC_CALR_CALW8 0x00004000U |
Definition at line 5564 of file stm32f407xx.h.
| #define RTC_CR_ADD1H 0x00010000U |
Definition at line 5368 of file stm32f407xx.h.
| #define RTC_CR_ALRAE 0x00000100U |
Definition at line 5376 of file stm32f407xx.h.
| #define RTC_CR_ALRAIE 0x00001000U |
Definition at line 5372 of file stm32f407xx.h.
| #define RTC_CR_ALRBE 0x00000200U |
Definition at line 5375 of file stm32f407xx.h.
| #define RTC_CR_ALRBIE 0x00002000U |
Definition at line 5371 of file stm32f407xx.h.
| #define RTC_CR_BCK 0x00040000U |
Definition at line 5366 of file stm32f407xx.h.
| #define RTC_CR_BYPSHAD 0x00000020U |
Definition at line 5379 of file stm32f407xx.h.
| #define RTC_CR_COE 0x00800000U |
Definition at line 5360 of file stm32f407xx.h.
| #define RTC_CR_COSEL 0x00080000U |
Definition at line 5365 of file stm32f407xx.h.
| #define RTC_CR_DCE 0x00000080U |
Definition at line 5377 of file stm32f407xx.h.
| #define RTC_CR_FMT 0x00000040U |
Definition at line 5378 of file stm32f407xx.h.
| #define RTC_CR_OSEL 0x00600000U |
Definition at line 5361 of file stm32f407xx.h.
| #define RTC_CR_OSEL_0 0x00200000U |
Definition at line 5362 of file stm32f407xx.h.
| #define RTC_CR_OSEL_1 0x00400000U |
Definition at line 5363 of file stm32f407xx.h.
| #define RTC_CR_POL 0x00100000U |
Definition at line 5364 of file stm32f407xx.h.
| #define RTC_CR_REFCKON 0x00000010U |
Definition at line 5380 of file stm32f407xx.h.
| #define RTC_CR_SUB1H 0x00020000U |
Definition at line 5367 of file stm32f407xx.h.
| #define RTC_CR_TSE 0x00000800U |
Definition at line 5373 of file stm32f407xx.h.
| #define RTC_CR_TSEDGE 0x00000008U |
Definition at line 5381 of file stm32f407xx.h.
| #define RTC_CR_TSIE 0x00008000U |
Definition at line 5369 of file stm32f407xx.h.
| #define RTC_CR_WUCKSEL 0x00000007U |
Definition at line 5382 of file stm32f407xx.h.
| #define RTC_CR_WUCKSEL_0 0x00000001U |
Definition at line 5383 of file stm32f407xx.h.
| #define RTC_CR_WUCKSEL_1 0x00000002U |
Definition at line 5384 of file stm32f407xx.h.
| #define RTC_CR_WUCKSEL_2 0x00000004U |
Definition at line 5385 of file stm32f407xx.h.
| #define RTC_CR_WUTE 0x00000400U |
Definition at line 5374 of file stm32f407xx.h.
| #define RTC_CR_WUTIE 0x00004000U |
Definition at line 5370 of file stm32f407xx.h.
| #define RTC_DR_DT 0x00000030U |
Definition at line 5350 of file stm32f407xx.h.
| #define RTC_DR_DT_0 0x00000010U |
Definition at line 5351 of file stm32f407xx.h.
| #define RTC_DR_DT_1 0x00000020U |
Definition at line 5352 of file stm32f407xx.h.
| #define RTC_DR_DU 0x0000000FU |
Definition at line 5353 of file stm32f407xx.h.
| #define RTC_DR_DU_0 0x00000001U |
Definition at line 5354 of file stm32f407xx.h.
| #define RTC_DR_DU_1 0x00000002U |
Definition at line 5355 of file stm32f407xx.h.
| #define RTC_DR_DU_2 0x00000004U |
Definition at line 5356 of file stm32f407xx.h.
| #define RTC_DR_DU_3 0x00000008U |
Definition at line 5357 of file stm32f407xx.h.
| #define RTC_DR_MT 0x00001000U |
Definition at line 5344 of file stm32f407xx.h.
| #define RTC_DR_MU 0x00000F00U |
Definition at line 5345 of file stm32f407xx.h.
| #define RTC_DR_MU_0 0x00000100U |
Definition at line 5346 of file stm32f407xx.h.
| #define RTC_DR_MU_1 0x00000200U |
Definition at line 5347 of file stm32f407xx.h.
| #define RTC_DR_MU_2 0x00000400U |
Definition at line 5348 of file stm32f407xx.h.
| #define RTC_DR_MU_3 0x00000800U |
Definition at line 5349 of file stm32f407xx.h.
| #define RTC_DR_WDU 0x0000E000U |
Definition at line 5340 of file stm32f407xx.h.
| #define RTC_DR_WDU_0 0x00002000U |
Definition at line 5341 of file stm32f407xx.h.
| #define RTC_DR_WDU_1 0x00004000U |
Definition at line 5342 of file stm32f407xx.h.
| #define RTC_DR_WDU_2 0x00008000U |
Definition at line 5343 of file stm32f407xx.h.
| #define RTC_DR_YT 0x00F00000U |
Definition at line 5330 of file stm32f407xx.h.
| #define RTC_DR_YT_0 0x00100000U |
Definition at line 5331 of file stm32f407xx.h.
| #define RTC_DR_YT_1 0x00200000U |
Definition at line 5332 of file stm32f407xx.h.
| #define RTC_DR_YT_2 0x00400000U |
Definition at line 5333 of file stm32f407xx.h.
| #define RTC_DR_YT_3 0x00800000U |
Definition at line 5334 of file stm32f407xx.h.
| #define RTC_DR_YU 0x000F0000U |
Definition at line 5335 of file stm32f407xx.h.
| #define RTC_DR_YU_0 0x00010000U |
Definition at line 5336 of file stm32f407xx.h.
| #define RTC_DR_YU_1 0x00020000U |
Definition at line 5337 of file stm32f407xx.h.
| #define RTC_DR_YU_2 0x00040000U |
Definition at line 5338 of file stm32f407xx.h.
| #define RTC_DR_YU_3 0x00080000U |
Definition at line 5339 of file stm32f407xx.h.
| #define RTC_ISR_ALRAF 0x00000100U |
Definition at line 5395 of file stm32f407xx.h.
| #define RTC_ISR_ALRAWF 0x00000001U |
Definition at line 5403 of file stm32f407xx.h.
| #define RTC_ISR_ALRBF 0x00000200U |
Definition at line 5394 of file stm32f407xx.h.
| #define RTC_ISR_ALRBWF 0x00000002U |
Definition at line 5402 of file stm32f407xx.h.
| #define RTC_ISR_INIT 0x00000080U |
Definition at line 5396 of file stm32f407xx.h.
| #define RTC_ISR_INITF 0x00000040U |
Definition at line 5397 of file stm32f407xx.h.
| #define RTC_ISR_INITS 0x00000010U |
Definition at line 5399 of file stm32f407xx.h.
| #define RTC_ISR_RECALPF 0x00010000U |
Definition at line 5388 of file stm32f407xx.h.
| #define RTC_ISR_RSF 0x00000020U |
Definition at line 5398 of file stm32f407xx.h.
| #define RTC_ISR_SHPF 0x00000008U |
Definition at line 5400 of file stm32f407xx.h.
| #define RTC_ISR_TAMP1F 0x00002000U |
Definition at line 5389 of file stm32f407xx.h.
| #define RTC_ISR_TAMP2F 0x00004000U |
Definition at line 5390 of file stm32f407xx.h.
| #define RTC_ISR_TSF 0x00000800U |
Definition at line 5392 of file stm32f407xx.h.
| #define RTC_ISR_TSOVF 0x00001000U |
Definition at line 5391 of file stm32f407xx.h.
| #define RTC_ISR_WUTF 0x00000400U |
Definition at line 5393 of file stm32f407xx.h.
| #define RTC_ISR_WUTWF 0x00000004U |
Definition at line 5401 of file stm32f407xx.h.
| #define RTC_PRER_PREDIV_A 0x007F0000U |
Definition at line 5406 of file stm32f407xx.h.
| #define RTC_PRER_PREDIV_S 0x00007FFFU |
Definition at line 5407 of file stm32f407xx.h.
| #define RTC_SHIFTR_ADD1S 0x80000000U |
Definition at line 5508 of file stm32f407xx.h.
| #define RTC_SHIFTR_SUBFS 0x00007FFFU |
Definition at line 5507 of file stm32f407xx.h.
| #define RTC_SSR_SS 0x0000FFFFU |
Definition at line 5504 of file stm32f407xx.h.
| #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U |
Definition at line 5578 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMP1E 0x00000001U |
Definition at line 5597 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMP1TRG 0x00000002U |
Definition at line 5596 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMP2E 0x00000008U |
Definition at line 5594 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMP2TRG 0x00000010U |
Definition at line 5593 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMPFLT 0x00001800U |
Definition at line 5585 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMPFLT_0 0x00000800U |
Definition at line 5586 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMPFLT_1 0x00001000U |
Definition at line 5587 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMPFREQ 0x00000700U |
Definition at line 5588 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMPFREQ_0 0x00000100U |
Definition at line 5589 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMPFREQ_1 0x00000200U |
Definition at line 5590 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMPFREQ_2 0x00000400U |
Definition at line 5591 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMPIE 0x00000004U |
Definition at line 5595 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMPINSEL 0x00010000U |
Definition at line 5580 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMPPRCH 0x00006000U |
Definition at line 5582 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMPPRCH_0 0x00002000U |
Definition at line 5583 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMPPRCH_1 0x00004000U |
Definition at line 5584 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMPPUDIS 0x00008000U |
Definition at line 5581 of file stm32f407xx.h.
| #define RTC_TAFCR_TAMPTS 0x00000080U |
Definition at line 5592 of file stm32f407xx.h.
| #define RTC_TAFCR_TSINSEL 0x00020000U |
Definition at line 5579 of file stm32f407xx.h.
| #define RTC_TR_HT 0x00300000U |
Definition at line 5302 of file stm32f407xx.h.
| #define RTC_TR_HT_0 0x00100000U |
Definition at line 5303 of file stm32f407xx.h.
| #define RTC_TR_HT_1 0x00200000U |
Definition at line 5304 of file stm32f407xx.h.
| #define RTC_TR_HU 0x000F0000U |
Definition at line 5305 of file stm32f407xx.h.
| #define RTC_TR_HU_0 0x00010000U |
Definition at line 5306 of file stm32f407xx.h.
| #define RTC_TR_HU_1 0x00020000U |
Definition at line 5307 of file stm32f407xx.h.
| #define RTC_TR_HU_2 0x00040000U |
Definition at line 5308 of file stm32f407xx.h.
| #define RTC_TR_HU_3 0x00080000U |
Definition at line 5309 of file stm32f407xx.h.
| #define RTC_TR_MNT 0x00007000U |
Definition at line 5310 of file stm32f407xx.h.
| #define RTC_TR_MNT_0 0x00001000U |
Definition at line 5311 of file stm32f407xx.h.
| #define RTC_TR_MNT_1 0x00002000U |
Definition at line 5312 of file stm32f407xx.h.
| #define RTC_TR_MNT_2 0x00004000U |
Definition at line 5313 of file stm32f407xx.h.
| #define RTC_TR_MNU 0x00000F00U |
Definition at line 5314 of file stm32f407xx.h.
| #define RTC_TR_MNU_0 0x00000100U |
Definition at line 5315 of file stm32f407xx.h.
| #define RTC_TR_MNU_1 0x00000200U |
Definition at line 5316 of file stm32f407xx.h.
| #define RTC_TR_MNU_2 0x00000400U |
Definition at line 5317 of file stm32f407xx.h.
| #define RTC_TR_MNU_3 0x00000800U |
Definition at line 5318 of file stm32f407xx.h.
| #define RTC_TR_PM 0x00400000U |
Definition at line 5301 of file stm32f407xx.h.
| #define RTC_TR_ST 0x00000070U |
Definition at line 5319 of file stm32f407xx.h.
| #define RTC_TR_ST_0 0x00000010U |
Definition at line 5320 of file stm32f407xx.h.
| #define RTC_TR_ST_1 0x00000020U |
Definition at line 5321 of file stm32f407xx.h.
| #define RTC_TR_ST_2 0x00000040U |
Definition at line 5322 of file stm32f407xx.h.
| #define RTC_TR_SU 0x0000000FU |
Definition at line 5323 of file stm32f407xx.h.
| #define RTC_TR_SU_0 0x00000001U |
Definition at line 5324 of file stm32f407xx.h.
| #define RTC_TR_SU_1 0x00000002U |
Definition at line 5325 of file stm32f407xx.h.
| #define RTC_TR_SU_2 0x00000004U |
Definition at line 5326 of file stm32f407xx.h.
| #define RTC_TR_SU_3 0x00000008U |
Definition at line 5327 of file stm32f407xx.h.
| #define RTC_TSDR_DT 0x00000030U |
Definition at line 5550 of file stm32f407xx.h.
| #define RTC_TSDR_DT_0 0x00000010U |
Definition at line 5551 of file stm32f407xx.h.
| #define RTC_TSDR_DT_1 0x00000020U |
Definition at line 5552 of file stm32f407xx.h.
| #define RTC_TSDR_DU 0x0000000FU |
Definition at line 5553 of file stm32f407xx.h.
| #define RTC_TSDR_DU_0 0x00000001U |
Definition at line 5554 of file stm32f407xx.h.
| #define RTC_TSDR_DU_1 0x00000002U |
Definition at line 5555 of file stm32f407xx.h.
| #define RTC_TSDR_DU_2 0x00000004U |
Definition at line 5556 of file stm32f407xx.h.
| #define RTC_TSDR_DU_3 0x00000008U |
Definition at line 5557 of file stm32f407xx.h.
| #define RTC_TSDR_MT 0x00001000U |
Definition at line 5544 of file stm32f407xx.h.
| #define RTC_TSDR_MU 0x00000F00U |
Definition at line 5545 of file stm32f407xx.h.
| #define RTC_TSDR_MU_0 0x00000100U |
Definition at line 5546 of file stm32f407xx.h.
| #define RTC_TSDR_MU_1 0x00000200U |
Definition at line 5547 of file stm32f407xx.h.
| #define RTC_TSDR_MU_2 0x00000400U |
Definition at line 5548 of file stm32f407xx.h.
| #define RTC_TSDR_MU_3 0x00000800U |
Definition at line 5549 of file stm32f407xx.h.
| #define RTC_TSDR_WDU 0x0000E000U |
Definition at line 5540 of file stm32f407xx.h.
| #define RTC_TSDR_WDU_0 0x00002000U |
Definition at line 5541 of file stm32f407xx.h.
| #define RTC_TSDR_WDU_1 0x00004000U |
Definition at line 5542 of file stm32f407xx.h.
| #define RTC_TSDR_WDU_2 0x00008000U |
Definition at line 5543 of file stm32f407xx.h.
| #define RTC_TSSSR_SS 0x0000FFFFU |
Definition at line 5560 of file stm32f407xx.h.
| #define RTC_TSTR_HT 0x00300000U |
Definition at line 5512 of file stm32f407xx.h.
| #define RTC_TSTR_HT_0 0x00100000U |
Definition at line 5513 of file stm32f407xx.h.
| #define RTC_TSTR_HT_1 0x00200000U |
Definition at line 5514 of file stm32f407xx.h.
| #define RTC_TSTR_HU 0x000F0000U |
Definition at line 5515 of file stm32f407xx.h.
| #define RTC_TSTR_HU_0 0x00010000U |
Definition at line 5516 of file stm32f407xx.h.
| #define RTC_TSTR_HU_1 0x00020000U |
Definition at line 5517 of file stm32f407xx.h.
| #define RTC_TSTR_HU_2 0x00040000U |
Definition at line 5518 of file stm32f407xx.h.
| #define RTC_TSTR_HU_3 0x00080000U |
Definition at line 5519 of file stm32f407xx.h.
| #define RTC_TSTR_MNT 0x00007000U |
Definition at line 5520 of file stm32f407xx.h.
| #define RTC_TSTR_MNT_0 0x00001000U |
Definition at line 5521 of file stm32f407xx.h.
| #define RTC_TSTR_MNT_1 0x00002000U |
Definition at line 5522 of file stm32f407xx.h.
| #define RTC_TSTR_MNT_2 0x00004000U |
Definition at line 5523 of file stm32f407xx.h.
| #define RTC_TSTR_MNU 0x00000F00U |
Definition at line 5524 of file stm32f407xx.h.
| #define RTC_TSTR_MNU_0 0x00000100U |
Definition at line 5525 of file stm32f407xx.h.
| #define RTC_TSTR_MNU_1 0x00000200U |
Definition at line 5526 of file stm32f407xx.h.
| #define RTC_TSTR_MNU_2 0x00000400U |
Definition at line 5527 of file stm32f407xx.h.
| #define RTC_TSTR_MNU_3 0x00000800U |
Definition at line 5528 of file stm32f407xx.h.
| #define RTC_TSTR_PM 0x00400000U |
Definition at line 5511 of file stm32f407xx.h.
| #define RTC_TSTR_ST 0x00000070U |
Definition at line 5529 of file stm32f407xx.h.
| #define RTC_TSTR_ST_0 0x00000010U |
Definition at line 5530 of file stm32f407xx.h.
| #define RTC_TSTR_ST_1 0x00000020U |
Definition at line 5531 of file stm32f407xx.h.
| #define RTC_TSTR_ST_2 0x00000040U |
Definition at line 5532 of file stm32f407xx.h.
| #define RTC_TSTR_SU 0x0000000FU |
Definition at line 5533 of file stm32f407xx.h.
| #define RTC_TSTR_SU_0 0x00000001U |
Definition at line 5534 of file stm32f407xx.h.
| #define RTC_TSTR_SU_1 0x00000002U |
Definition at line 5535 of file stm32f407xx.h.
| #define RTC_TSTR_SU_2 0x00000004U |
Definition at line 5536 of file stm32f407xx.h.
| #define RTC_TSTR_SU_3 0x00000008U |
Definition at line 5537 of file stm32f407xx.h.
| #define RTC_WPR_KEY 0x000000FFU |
Definition at line 5501 of file stm32f407xx.h.
| #define RTC_WUTR_WUT 0x0000FFFFU |
Definition at line 5410 of file stm32f407xx.h.
| #define SDIO_ARG_CMDARG 0xFFFFFFFFU |
Command argument
Definition at line 5701 of file stm32f407xx.h.
| #define SDIO_CLKCR_BYPASS 0x0400U |
Clock divider bypass enable bit
Definition at line 5691 of file stm32f407xx.h.
| #define SDIO_CLKCR_CLKDIV 0x00FFU |
Clock divide factor
Definition at line 5688 of file stm32f407xx.h.
| #define SDIO_CLKCR_CLKEN 0x0100U |
Clock enable bit
Definition at line 5689 of file stm32f407xx.h.
| #define SDIO_CLKCR_HWFC_EN 0x4000U |
HW Flow Control enable
Definition at line 5698 of file stm32f407xx.h.
| #define SDIO_CLKCR_NEGEDGE 0x2000U |
SDIO_CK dephasing selection bit
Definition at line 5697 of file stm32f407xx.h.
| #define SDIO_CLKCR_PWRSAV 0x0200U |
Power saving configuration bit
Definition at line 5690 of file stm32f407xx.h.
| #define SDIO_CLKCR_WIDBUS 0x1800U |
WIDBUS[1:0] bits (Wide bus mode enable bit)
Definition at line 5693 of file stm32f407xx.h.
| #define SDIO_CLKCR_WIDBUS_0 0x0800U |
Bit 0
Definition at line 5694 of file stm32f407xx.h.
| #define SDIO_CLKCR_WIDBUS_1 0x1000U |
Bit 1
Definition at line 5695 of file stm32f407xx.h.
| #define SDIO_CMD_CEATACMD 0x4000U |
CE-ATA command
Definition at line 5716 of file stm32f407xx.h.
| #define SDIO_CMD_CMDINDEX 0x003FU |
Command Index
Definition at line 5704 of file stm32f407xx.h.
| #define SDIO_CMD_CPSMEN 0x0400U |
Command path state machine (CPSM) Enable bit
Definition at line 5712 of file stm32f407xx.h.
| #define SDIO_CMD_ENCMDCOMPL 0x1000U |
Enable CMD completion
Definition at line 5714 of file stm32f407xx.h.
| #define SDIO_CMD_NIEN 0x2000U |
Not Interrupt Enable
Definition at line 5715 of file stm32f407xx.h.
| #define SDIO_CMD_SDIOSUSPEND 0x0800U |
SD I/O suspend command
Definition at line 5713 of file stm32f407xx.h.
| #define SDIO_CMD_WAITINT 0x0100U |
CPSM Waits for Interrupt Request
Definition at line 5710 of file stm32f407xx.h.
| #define SDIO_CMD_WAITPEND 0x0200U |
CPSM Waits for ends of data transfer (CmdPend internal signal)
Definition at line 5711 of file stm32f407xx.h.
| #define SDIO_CMD_WAITRESP 0x00C0U |
WAITRESP[1:0] bits (Wait for response bits)
Definition at line 5706 of file stm32f407xx.h.
| #define SDIO_CMD_WAITRESP_0 0x0040U |
Bit 0
Definition at line 5707 of file stm32f407xx.h.
| #define SDIO_CMD_WAITRESP_1 0x0080U |
Bit 1
Definition at line 5708 of file stm32f407xx.h.
| #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU |
Data count value
Definition at line 5760 of file stm32f407xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE 0x00F0U |
DBLOCKSIZE[3:0] bits (Data block size)
Definition at line 5748 of file stm32f407xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U |
Bit 0
Definition at line 5749 of file stm32f407xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U |
Bit 1
Definition at line 5750 of file stm32f407xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U |
Bit 2
Definition at line 5751 of file stm32f407xx.h.
| #define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U |
Bit 3
Definition at line 5752 of file stm32f407xx.h.
| #define SDIO_DCTRL_DMAEN 0x0008U |
DMA enabled bit
Definition at line 5746 of file stm32f407xx.h.
| #define SDIO_DCTRL_DTDIR 0x0002U |
Data transfer direction selection
Definition at line 5744 of file stm32f407xx.h.
| #define SDIO_DCTRL_DTEN 0x0001U |
Data transfer enabled bit
Definition at line 5743 of file stm32f407xx.h.
| #define SDIO_DCTRL_DTMODE 0x0004U |
Data transfer mode selection
Definition at line 5745 of file stm32f407xx.h.
| #define SDIO_DCTRL_RWMOD 0x0400U |
Read wait mode
Definition at line 5756 of file stm32f407xx.h.
| #define SDIO_DCTRL_RWSTART 0x0100U |
Read wait start
Definition at line 5754 of file stm32f407xx.h.
| #define SDIO_DCTRL_RWSTOP 0x0200U |
Read wait stop
Definition at line 5755 of file stm32f407xx.h.
| #define SDIO_DCTRL_SDIOEN 0x0800U |
SD I/O enable functions
Definition at line 5757 of file stm32f407xx.h.
| #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU |
Data length value
Definition at line 5740 of file stm32f407xx.h.
| #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU |
Data timeout period.
Definition at line 5737 of file stm32f407xx.h.
| #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU |
Receive and transmit FIFO data
Definition at line 5833 of file stm32f407xx.h.
| #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU |
Remaining number of words to be written to or read from the FIFO
Definition at line 5830 of file stm32f407xx.h.
| #define SDIO_ICR_CCRCFAILC 0x00000001U |
CCRCFAIL flag clear bit
Definition at line 5789 of file stm32f407xx.h.
| #define SDIO_ICR_CEATAENDC 0x00800000U |
CEATAEND flag clear bit
Definition at line 5801 of file stm32f407xx.h.
| #define SDIO_ICR_CMDRENDC 0x00000040U |
CMDREND flag clear bit
Definition at line 5795 of file stm32f407xx.h.
| #define SDIO_ICR_CMDSENTC 0x00000080U |
CMDSENT flag clear bit
Definition at line 5796 of file stm32f407xx.h.
| #define SDIO_ICR_CTIMEOUTC 0x00000004U |
CTIMEOUT flag clear bit
Definition at line 5791 of file stm32f407xx.h.
| #define SDIO_ICR_DATAENDC 0x00000100U |
DATAEND flag clear bit
Definition at line 5797 of file stm32f407xx.h.
| #define SDIO_ICR_DBCKENDC 0x00000400U |
DBCKEND flag clear bit
Definition at line 5799 of file stm32f407xx.h.
| #define SDIO_ICR_DCRCFAILC 0x00000002U |
DCRCFAIL flag clear bit
Definition at line 5790 of file stm32f407xx.h.
| #define SDIO_ICR_DTIMEOUTC 0x00000008U |
DTIMEOUT flag clear bit
Definition at line 5792 of file stm32f407xx.h.
| #define SDIO_ICR_RXOVERRC 0x00000020U |
RXOVERR flag clear bit
Definition at line 5794 of file stm32f407xx.h.
| #define SDIO_ICR_SDIOITC 0x00400000U |
SDIOIT flag clear bit
Definition at line 5800 of file stm32f407xx.h.
| #define SDIO_ICR_STBITERRC 0x00000200U |
STBITERR flag clear bit
Definition at line 5798 of file stm32f407xx.h.
| #define SDIO_ICR_TXUNDERRC 0x00000010U |
TXUNDERR flag clear bit
Definition at line 5793 of file stm32f407xx.h.
| #define SDIO_MASK_CCRCFAILIE 0x00000001U |
Command CRC Fail Interrupt Enable
Definition at line 5804 of file stm32f407xx.h.
| #define SDIO_MASK_CEATAENDIE 0x00800000U |
CE-ATA command completion signal received Interrupt Enable
Definition at line 5827 of file stm32f407xx.h.
| #define SDIO_MASK_CMDACTIE 0x00000800U |
CCommand Acting Interrupt Enable
Definition at line 5815 of file stm32f407xx.h.
| #define SDIO_MASK_CMDRENDIE 0x00000040U |
Command Response Received Interrupt Enable
Definition at line 5810 of file stm32f407xx.h.
| #define SDIO_MASK_CMDSENTIE 0x00000080U |
Command Sent Interrupt Enable
Definition at line 5811 of file stm32f407xx.h.
| #define SDIO_MASK_CTIMEOUTIE 0x00000004U |
Command TimeOut Interrupt Enable
Definition at line 5806 of file stm32f407xx.h.
| #define SDIO_MASK_DATAENDIE 0x00000100U |
Data End Interrupt Enable
Definition at line 5812 of file stm32f407xx.h.
| #define SDIO_MASK_DBCKENDIE 0x00000400U |
Data Block End Interrupt Enable
Definition at line 5814 of file stm32f407xx.h.
| #define SDIO_MASK_DCRCFAILIE 0x00000002U |
Data CRC Fail Interrupt Enable
Definition at line 5805 of file stm32f407xx.h.
| #define SDIO_MASK_DTIMEOUTIE 0x00000008U |
Data TimeOut Interrupt Enable
Definition at line 5807 of file stm32f407xx.h.
| #define SDIO_MASK_RXACTIE 0x00002000U |
Data receive acting interrupt enabled
Definition at line 5817 of file stm32f407xx.h.
| #define SDIO_MASK_RXDAVLIE 0x00200000U |
Data available in Rx FIFO interrupt Enable
Definition at line 5825 of file stm32f407xx.h.
| #define SDIO_MASK_RXFIFOEIE 0x00080000U |
Rx FIFO Empty interrupt Enable
Definition at line 5823 of file stm32f407xx.h.
| #define SDIO_MASK_RXFIFOFIE 0x00020000U |
Rx FIFO Full interrupt Enable
Definition at line 5821 of file stm32f407xx.h.
| #define SDIO_MASK_RXFIFOHFIE 0x00008000U |
Rx FIFO Half Full interrupt Enable
Definition at line 5819 of file stm32f407xx.h.
| #define SDIO_MASK_RXOVERRIE 0x00000020U |
Rx FIFO OverRun Error Interrupt Enable
Definition at line 5809 of file stm32f407xx.h.
| #define SDIO_MASK_SDIOITIE 0x00400000U |
SDIO Mode Interrupt Received interrupt Enable
Definition at line 5826 of file stm32f407xx.h.
| #define SDIO_MASK_STBITERRIE 0x00000200U |
Start Bit Error Interrupt Enable
Definition at line 5813 of file stm32f407xx.h.
| #define SDIO_MASK_TXACTIE 0x00001000U |
Data Transmit Acting Interrupt Enable
Definition at line 5816 of file stm32f407xx.h.
| #define SDIO_MASK_TXDAVLIE 0x00100000U |
Data available in Tx FIFO interrupt Enable
Definition at line 5824 of file stm32f407xx.h.
| #define SDIO_MASK_TXFIFOEIE 0x00040000U |
Tx FIFO Empty interrupt Enable
Definition at line 5822 of file stm32f407xx.h.
| #define SDIO_MASK_TXFIFOFIE 0x00010000U |
Tx FIFO Full interrupt Enable
Definition at line 5820 of file stm32f407xx.h.
| #define SDIO_MASK_TXFIFOHEIE 0x00004000U |
Tx FIFO Half Empty interrupt Enable
Definition at line 5818 of file stm32f407xx.h.
| #define SDIO_MASK_TXUNDERRIE 0x00000010U |
Tx FIFO UnderRun Error Interrupt Enable
Definition at line 5808 of file stm32f407xx.h.
| #define SDIO_POWER_PWRCTRL 0x03U |
PWRCTRL[1:0] bits (Power supply control bits)
Definition at line 5683 of file stm32f407xx.h.
| #define SDIO_POWER_PWRCTRL_0 0x01U |
Bit 0
Definition at line 5684 of file stm32f407xx.h.
| #define SDIO_POWER_PWRCTRL_1 0x02U |
Bit 1
Definition at line 5685 of file stm32f407xx.h.
| #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU |
Card Status
Definition at line 5722 of file stm32f407xx.h.
| #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU |
Card Status
Definition at line 5725 of file stm32f407xx.h.
| #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU |
Card Status
Definition at line 5728 of file stm32f407xx.h.
| #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU |
Card Status
Definition at line 5731 of file stm32f407xx.h.
| #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU |
Card Status
Definition at line 5734 of file stm32f407xx.h.
| #define SDIO_RESPCMD_RESPCMD 0x3FU |
Response command index
Definition at line 5719 of file stm32f407xx.h.
| #define SDIO_STA_CCRCFAIL 0x00000001U |
Command response received (CRC check failed)
Definition at line 5763 of file stm32f407xx.h.
| #define SDIO_STA_CEATAEND 0x00800000U |
CE-ATA command completion signal received for CMD61
Definition at line 5786 of file stm32f407xx.h.
| #define SDIO_STA_CMDACT 0x00000800U |
Command transfer in progress
Definition at line 5774 of file stm32f407xx.h.
| #define SDIO_STA_CMDREND 0x00000040U |
Command response received (CRC check passed)
Definition at line 5769 of file stm32f407xx.h.
| #define SDIO_STA_CMDSENT 0x00000080U |
Command sent (no response required)
Definition at line 5770 of file stm32f407xx.h.
| #define SDIO_STA_CTIMEOUT 0x00000004U |
Command response timeout
Definition at line 5765 of file stm32f407xx.h.
| #define SDIO_STA_DATAEND 0x00000100U |
Data end (data counter, SDIDCOUNT, is zero)
Definition at line 5771 of file stm32f407xx.h.
| #define SDIO_STA_DBCKEND 0x00000400U |
Data block sent/received (CRC check passed)
Definition at line 5773 of file stm32f407xx.h.
| #define SDIO_STA_DCRCFAIL 0x00000002U |
Data block sent/received (CRC check failed)
Definition at line 5764 of file stm32f407xx.h.
| #define SDIO_STA_DTIMEOUT 0x00000008U |
Data timeout
Definition at line 5766 of file stm32f407xx.h.
| #define SDIO_STA_RXACT 0x00002000U |
Data receive in progress
Definition at line 5776 of file stm32f407xx.h.
| #define SDIO_STA_RXDAVL 0x00200000U |
Data available in receive FIFO
Definition at line 5784 of file stm32f407xx.h.
| #define SDIO_STA_RXFIFOE 0x00080000U |
Receive FIFO empty
Definition at line 5782 of file stm32f407xx.h.
| #define SDIO_STA_RXFIFOF 0x00020000U |
Receive FIFO full
Definition at line 5780 of file stm32f407xx.h.
| #define SDIO_STA_RXFIFOHF 0x00008000U |
Receive FIFO Half Full: there are at least 8 words in the FIFO
Definition at line 5778 of file stm32f407xx.h.
| #define SDIO_STA_RXOVERR 0x00000020U |
Received FIFO overrun error
Definition at line 5768 of file stm32f407xx.h.
| #define SDIO_STA_SDIOIT 0x00400000U |
SDIO interrupt received
Definition at line 5785 of file stm32f407xx.h.
| #define SDIO_STA_STBITERR 0x00000200U |
Start bit not detected on all data signals in wide bus mode
Definition at line 5772 of file stm32f407xx.h.
| #define SDIO_STA_TXACT 0x00001000U |
Data transmit in progress
Definition at line 5775 of file stm32f407xx.h.
| #define SDIO_STA_TXDAVL 0x00100000U |
Data available in transmit FIFO
Definition at line 5783 of file stm32f407xx.h.
| #define SDIO_STA_TXFIFOE 0x00040000U |
Transmit FIFO empty
Definition at line 5781 of file stm32f407xx.h.
| #define SDIO_STA_TXFIFOF 0x00010000U |
Transmit FIFO full
Definition at line 5779 of file stm32f407xx.h.
| #define SDIO_STA_TXFIFOHE 0x00004000U |
Transmit FIFO Half Empty: at least 8 words can be written into the FIFO
Definition at line 5777 of file stm32f407xx.h.
| #define SDIO_STA_TXUNDERR 0x00000010U |
Transmit FIFO underrun error
Definition at line 5767 of file stm32f407xx.h.
| #define SPI_CR1_BIDIMODE 0x00008000U |
Bidirectional data mode enable
Definition at line 5859 of file stm32f407xx.h.
| #define SPI_CR1_BIDIOE 0x00004000U |
Output enable in bidirectional mode
Definition at line 5858 of file stm32f407xx.h.
| #define SPI_CR1_BR 0x00000038U |
BR[2:0] bits (Baud Rate Control)
Definition at line 5845 of file stm32f407xx.h.
| #define SPI_CR1_BR_0 0x00000008U |
Bit 0
Definition at line 5846 of file stm32f407xx.h.
| #define SPI_CR1_BR_1 0x00000010U |
Bit 1
Definition at line 5847 of file stm32f407xx.h.
| #define SPI_CR1_BR_2 0x00000020U |
Bit 2
Definition at line 5848 of file stm32f407xx.h.
| #define SPI_CR1_CPHA 0x00000001U |
Clock Phase
Definition at line 5841 of file stm32f407xx.h.
| #define SPI_CR1_CPOL 0x00000002U |
Clock Polarity
Definition at line 5842 of file stm32f407xx.h.
| #define SPI_CR1_CRCEN 0x00002000U |
Hardware CRC calculation enable
Definition at line 5857 of file stm32f407xx.h.
| #define SPI_CR1_CRCNEXT 0x00001000U |
Transmit CRC next
Definition at line 5856 of file stm32f407xx.h.
| #define SPI_CR1_DFF 0x00000800U |
Data Frame Format
Definition at line 5855 of file stm32f407xx.h.
| #define SPI_CR1_LSBFIRST 0x00000080U |
Frame Format
Definition at line 5851 of file stm32f407xx.h.
| #define SPI_CR1_MSTR 0x00000004U |
Master Selection
Definition at line 5843 of file stm32f407xx.h.
| #define SPI_CR1_RXONLY 0x00000400U |
Receive only
Definition at line 5854 of file stm32f407xx.h.
| #define SPI_CR1_SPE 0x00000040U |
SPI Enable
Definition at line 5850 of file stm32f407xx.h.
| #define SPI_CR1_SSI 0x00000100U |
Internal slave select
Definition at line 5852 of file stm32f407xx.h.
| #define SPI_CR1_SSM 0x00000200U |
Software slave management
Definition at line 5853 of file stm32f407xx.h.
| #define SPI_CR2_ERRIE 0x00000020U |
Error Interrupt Enable
Definition at line 5866 of file stm32f407xx.h.
| #define SPI_CR2_FRF 0x00000010U |
Frame Format
Definition at line 5865 of file stm32f407xx.h.
| #define SPI_CR2_RXDMAEN 0x00000001U |
Rx Buffer DMA Enable
Definition at line 5862 of file stm32f407xx.h.
| #define SPI_CR2_RXNEIE 0x00000040U |
RX buffer Not Empty Interrupt Enable
Definition at line 5867 of file stm32f407xx.h.
| #define SPI_CR2_SSOE 0x00000004U |
SS Output Enable
Definition at line 5864 of file stm32f407xx.h.
| #define SPI_CR2_TXDMAEN 0x00000002U |
Tx Buffer DMA Enable
Definition at line 5863 of file stm32f407xx.h.
| #define SPI_CR2_TXEIE 0x00000080U |
Tx buffer Empty Interrupt Enable
Definition at line 5868 of file stm32f407xx.h.
| #define SPI_CRCPR_CRCPOLY 0x0000FFFFU |
CRC polynomial register
Definition at line 5885 of file stm32f407xx.h.
| #define SPI_DR_DR 0x0000FFFFU |
Data Register
Definition at line 5882 of file stm32f407xx.h.
| #define SPI_I2SCFGR_CHLEN 0x00000001U |
Channel length (number of bits per audio channel)
Definition at line 5894 of file stm32f407xx.h.
| #define SPI_I2SCFGR_CKPOL 0x00000008U |
steady state clock polarity
Definition at line 5900 of file stm32f407xx.h.
| #define SPI_I2SCFGR_DATLEN 0x00000006U |
DATLEN[1:0] bits (Data length to be transferred)
Definition at line 5896 of file stm32f407xx.h.
| #define SPI_I2SCFGR_DATLEN_0 0x00000002U |
Bit 0
Definition at line 5897 of file stm32f407xx.h.
| #define SPI_I2SCFGR_DATLEN_1 0x00000004U |
Bit 1
Definition at line 5898 of file stm32f407xx.h.
| #define SPI_I2SCFGR_I2SCFG 0x00000300U |
I2SCFG[1:0] bits (I2S configuration mode)
Definition at line 5908 of file stm32f407xx.h.
| #define SPI_I2SCFGR_I2SCFG_0 0x00000100U |
Bit 0
Definition at line 5909 of file stm32f407xx.h.
| #define SPI_I2SCFGR_I2SCFG_1 0x00000200U |
Bit 1
Definition at line 5910 of file stm32f407xx.h.
| #define SPI_I2SCFGR_I2SE 0x00000400U |
I2S Enable
Definition at line 5912 of file stm32f407xx.h.
| #define SPI_I2SCFGR_I2SMOD 0x00000800U |
I2S mode selection
Definition at line 5913 of file stm32f407xx.h.
| #define SPI_I2SCFGR_I2SSTD 0x00000030U |
I2SSTD[1:0] bits (I2S standard selection)
Definition at line 5902 of file stm32f407xx.h.
| #define SPI_I2SCFGR_I2SSTD_0 0x00000010U |
Bit 0
Definition at line 5903 of file stm32f407xx.h.
| #define SPI_I2SCFGR_I2SSTD_1 0x00000020U |
Bit 1
Definition at line 5904 of file stm32f407xx.h.
| #define SPI_I2SCFGR_PCMSYNC 0x00000080U |
PCM frame synchronization
Definition at line 5906 of file stm32f407xx.h.
| #define SPI_I2SPR_I2SDIV 0x000000FFU |
I2S Linear prescaler
Definition at line 5916 of file stm32f407xx.h.
| #define SPI_I2SPR_MCKOE 0x00000200U |
Master Clock Output Enable
Definition at line 5918 of file stm32f407xx.h.
| #define SPI_I2SPR_ODD 0x00000100U |
Odd factor for the prescaler
Definition at line 5917 of file stm32f407xx.h.
| #define SPI_RXCRCR_RXCRC 0x0000FFFFU |
Rx CRC Register
Definition at line 5888 of file stm32f407xx.h.
| #define SPI_SR_BSY 0x00000080U |
Busy flag
Definition at line 5878 of file stm32f407xx.h.
| #define SPI_SR_CHSIDE 0x00000004U |
Channel side
Definition at line 5873 of file stm32f407xx.h.
| #define SPI_SR_CRCERR 0x00000010U |
CRC Error flag
Definition at line 5875 of file stm32f407xx.h.
| #define SPI_SR_FRE 0x00000100U |
Frame format error flag
Definition at line 5879 of file stm32f407xx.h.
| #define SPI_SR_MODF 0x00000020U |
Mode fault
Definition at line 5876 of file stm32f407xx.h.
| #define SPI_SR_OVR 0x00000040U |
Overrun flag
Definition at line 5877 of file stm32f407xx.h.
| #define SPI_SR_RXNE 0x00000001U |
Receive buffer Not Empty
Definition at line 5871 of file stm32f407xx.h.
| #define SPI_SR_TXE 0x00000002U |
Transmit buffer Empty
Definition at line 5872 of file stm32f407xx.h.
| #define SPI_SR_UDR 0x00000008U |
Underrun flag
Definition at line 5874 of file stm32f407xx.h.
| #define SPI_TXCRCR_TXCRC 0x0000FFFFU |
Tx CRC Register
Definition at line 5891 of file stm32f407xx.h.
| #define SYSCFG_CMPCR_CMP_PD 0x00000001U |
Compensation cell ready flag
Definition at line 6163 of file stm32f407xx.h.
| #define SYSCFG_CMPCR_READY 0x00000100U |
Compensation cell power-down
Definition at line 6164 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI0 0x000FU |
EXTI 0 configuration
Definition at line 5937 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U |
| #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U |
PB[0] pin
Definition at line 5945 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U |
PC[0] pin
Definition at line 5946 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U |
PD[0] pin
Definition at line 5947 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U |
PE[0] pin
Definition at line 5948 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U |
PF[0] pin
Definition at line 5949 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U |
PG[0] pin
Definition at line 5950 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U |
PH[0] pin
Definition at line 5951 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U |
PI[0] pin
Definition at line 5952 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI1 0x00F0U |
EXTI 1 configuration
Definition at line 5938 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U |
| #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U |
PB[1] pin
Definition at line 5958 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U |
PC[1] pin
Definition at line 5959 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U |
PD[1] pin
Definition at line 5960 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U |
PE[1] pin
Definition at line 5961 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U |
PF[1] pin
Definition at line 5962 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U |
PG[1] pin
Definition at line 5963 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U |
PH[1] pin
Definition at line 5964 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U |
PI[1] pin
Definition at line 5965 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI2 0x0F00U |
EXTI 2 configuration
Definition at line 5939 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U |
| #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U |
PB[2] pin
Definition at line 5971 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U |
PC[2] pin
Definition at line 5972 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U |
PD[2] pin
Definition at line 5973 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U |
PE[2] pin
Definition at line 5974 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U |
PF[2] pin
Definition at line 5975 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U |
PG[2] pin
Definition at line 5976 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U |
PH[2] pin
Definition at line 5977 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U |
PI[2] pin
Definition at line 5978 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI3 0xF000U |
EXTI 3 configuration
Definition at line 5940 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U |
| #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U |
PB[3] pin
Definition at line 5984 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U |
PC[3] pin
Definition at line 5985 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U |
PD[3] pin
Definition at line 5986 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U |
PE[3] pin
Definition at line 5987 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U |
PF[3] pin
Definition at line 5988 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U |
PG[3] pin
Definition at line 5989 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U |
PH[3] pin
Definition at line 5990 of file stm32f407xx.h.
| #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U |
PI[3] pin
Definition at line 5991 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI4 0x000FU |
EXTI 4 configuration
Definition at line 5994 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U |
| #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U |
PB[4] pin
Definition at line 6002 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U |
PC[4] pin
Definition at line 6003 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U |
PD[4] pin
Definition at line 6004 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U |
PE[4] pin
Definition at line 6005 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U |
PF[4] pin
Definition at line 6006 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U |
PG[4] pin
Definition at line 6007 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U |
PH[4] pin
Definition at line 6008 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U |
PI[4] pin
Definition at line 6009 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI5 0x00F0U |
EXTI 5 configuration
Definition at line 5995 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U |
| #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U |
PB[5] pin
Definition at line 6015 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U |
PC[5] pin
Definition at line 6016 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U |
PD[5] pin
Definition at line 6017 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U |
PE[5] pin
Definition at line 6018 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U |
PF[5] pin
Definition at line 6019 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U |
PG[5] pin
Definition at line 6020 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U |
PH[5] pin
Definition at line 6021 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U |
PI[5] pin
Definition at line 6022 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI6 0x0F00U |
EXTI 6 configuration
Definition at line 5996 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U |
| #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U |
PB[6] pin
Definition at line 6028 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U |
PC[6] pin
Definition at line 6029 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U |
PD[6] pin
Definition at line 6030 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U |
PE[6] pin
Definition at line 6031 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U |
PF[6] pin
Definition at line 6032 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U |
PG[6] pin
Definition at line 6033 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U |
PH[6] pin
Definition at line 6034 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U |
PI[6] pin
Definition at line 6035 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI7 0xF000U |
EXTI 7 configuration
Definition at line 5997 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U |
| #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U |
PB[7] pin
Definition at line 6041 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U |
PC[7] pin
Definition at line 6042 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U |
PD[7] pin
Definition at line 6043 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U |
PE[7] pin
Definition at line 6044 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U |
PF[7] pin
Definition at line 6045 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U |
PG[7] pin
Definition at line 6046 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U |
PH[7] pin
Definition at line 6047 of file stm32f407xx.h.
| #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U |
PI[7] pin
Definition at line 6048 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI10 0x0F00U |
EXTI 10 configuration
Definition at line 6054 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U |
| #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U |
PB[10] pin
Definition at line 6087 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U |
PC[10] pin
Definition at line 6088 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U |
PD[10] pin
Definition at line 6089 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U |
PE[10] pin
Definition at line 6090 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U |
PF[10] pin
Definition at line 6091 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U |
PG[10] pin
Definition at line 6092 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U |
PH[10] pin
Definition at line 6093 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U |
PI[10] pin
Definition at line 6094 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI11 0xF000U |
EXTI 11 configuration
Definition at line 6055 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U |
| #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U |
PB[11] pin
Definition at line 6100 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U |
PC[11] pin
Definition at line 6101 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U |
PD[11] pin
Definition at line 6102 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U |
PE[11] pin
Definition at line 6103 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U |
PF[11] pin
Definition at line 6104 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U |
PG[11] pin
Definition at line 6105 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U |
PH[11] pin
Definition at line 6106 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U |
PI[11] pin
Definition at line 6107 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI8 0x000FU |
EXTI 8 configuration
Definition at line 6052 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U |
| #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U |
PB[8] pin
Definition at line 6061 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U |
PC[8] pin
Definition at line 6062 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U |
PD[8] pin
Definition at line 6063 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U |
PE[8] pin
Definition at line 6064 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U |
PF[8] pin
Definition at line 6065 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U |
PG[8] pin
Definition at line 6066 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U |
PH[8] pin
Definition at line 6067 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U |
PI[8] pin
Definition at line 6068 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI9 0x00F0U |
EXTI 9 configuration
Definition at line 6053 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U |
| #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U |
PB[9] pin
Definition at line 6074 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U |
PC[9] pin
Definition at line 6075 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U |
PD[9] pin
Definition at line 6076 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U |
PE[9] pin
Definition at line 6077 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U |
PF[9] pin
Definition at line 6078 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U |
PG[9] pin
Definition at line 6079 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U |
PH[9] pin
Definition at line 6080 of file stm32f407xx.h.
| #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U |
PI[9] pin
Definition at line 6081 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI12 0x000FU |
EXTI 12 configuration
Definition at line 6110 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U |
| #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U |
PB[12] pin
Definition at line 6118 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U |
PC[12] pin
Definition at line 6119 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U |
PD[12] pin
Definition at line 6120 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U |
PE[12] pin
Definition at line 6121 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U |
PF[12] pin
Definition at line 6122 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U |
PG[12] pin
Definition at line 6123 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U |
PH[12] pin
Definition at line 6124 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI13 0x00F0U |
EXTI 13 configuration
Definition at line 6111 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U |
| #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U |
PB[13] pin
Definition at line 6130 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U |
PC[13] pin
Definition at line 6131 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U |
PD[13] pin
Definition at line 6132 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U |
PE[13] pin
Definition at line 6133 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U |
PF[13] pin
Definition at line 6134 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U |
PG[13] pin
Definition at line 6135 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U |
PH[13] pin
Definition at line 6136 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI14 0x0F00U |
EXTI 14 configuration
Definition at line 6112 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U |
| #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U |
PB[14] pin
Definition at line 6142 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U |
PC[14] pin
Definition at line 6143 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U |
PD[14] pin
Definition at line 6144 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U |
PE[14] pin
Definition at line 6145 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U |
PF[14] pin
Definition at line 6146 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U |
PG[14] pin
Definition at line 6147 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U |
PH[14] pin
Definition at line 6148 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI15 0xF000U |
EXTI 15 configuration
Definition at line 6113 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U |
| #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U |
PB[15] pin
Definition at line 6154 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U |
PC[15] pin
Definition at line 6155 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U |
PD[15] pin
Definition at line 6156 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U |
PE[15] pin
Definition at line 6157 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U |
PF[15] pin
Definition at line 6158 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U |
PG[15] pin
Definition at line 6159 of file stm32f407xx.h.
| #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U |
PH[15] pin
Definition at line 6160 of file stm32f407xx.h.
| #define SYSCFG_MEMRMP_MEM_MODE 0x00000007U |
SYSCFG_Memory Remap Config
Definition at line 5926 of file stm32f407xx.h.
| #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U |
Definition at line 5927 of file stm32f407xx.h.
| #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U |
Definition at line 5928 of file stm32f407xx.h.
| #define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U |
Definition at line 5929 of file stm32f407xx.h.
| #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL |
Definition at line 5934 of file stm32f407xx.h.
| #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U |
Ethernet PHY interface selection
Definition at line 5932 of file stm32f407xx.h.
| #define TIM_ARR_ARR 0xFFFFU |
actual auto-reload Value
Definition at line 6400 of file stm32f407xx.h.
| #define TIM_BDTR_AOE 0x4000U |
Automatic Output enable
Definition at line 6436 of file stm32f407xx.h.
| #define TIM_BDTR_BKE 0x1000U |
Break enable
Definition at line 6434 of file stm32f407xx.h.
| #define TIM_BDTR_BKP 0x2000U |
Break Polarity
Definition at line 6435 of file stm32f407xx.h.
| #define TIM_BDTR_DTG 0x00FFU |
DTG[0:7] bits (Dead-Time Generator set-up)
Definition at line 6418 of file stm32f407xx.h.
| #define TIM_BDTR_DTG_0 0x0001U |
Bit 0
Definition at line 6419 of file stm32f407xx.h.
| #define TIM_BDTR_DTG_1 0x0002U |
Bit 1
Definition at line 6420 of file stm32f407xx.h.
| #define TIM_BDTR_DTG_2 0x0004U |
Bit 2
Definition at line 6421 of file stm32f407xx.h.
| #define TIM_BDTR_DTG_3 0x0008U |
Bit 3
Definition at line 6422 of file stm32f407xx.h.
| #define TIM_BDTR_DTG_4 0x0010U |
Bit 4
Definition at line 6423 of file stm32f407xx.h.
| #define TIM_BDTR_DTG_5 0x0020U |
Bit 5
Definition at line 6424 of file stm32f407xx.h.
| #define TIM_BDTR_DTG_6 0x0040U |
Bit 6
Definition at line 6425 of file stm32f407xx.h.
| #define TIM_BDTR_DTG_7 0x0080U |
Bit 7
Definition at line 6426 of file stm32f407xx.h.
| #define TIM_BDTR_LOCK 0x0300U |
LOCK[1:0] bits (Lock Configuration)
Definition at line 6428 of file stm32f407xx.h.
| #define TIM_BDTR_LOCK_0 0x0100U |
Bit 0
Definition at line 6429 of file stm32f407xx.h.
| #define TIM_BDTR_LOCK_1 0x0200U |
Bit 1
Definition at line 6430 of file stm32f407xx.h.
| #define TIM_BDTR_MOE 0x8000U |
Main Output enable
Definition at line 6437 of file stm32f407xx.h.
| #define TIM_BDTR_OSSI 0x0400U |
Off-State Selection for Idle mode
Definition at line 6432 of file stm32f407xx.h.
| #define TIM_BDTR_OSSR 0x0800U |
Off-State Selection for Run mode
Definition at line 6433 of file stm32f407xx.h.
| #define TIM_CCER_CC1E 0x0001U |
Capture/Compare 1 output enable
Definition at line 6377 of file stm32f407xx.h.
| #define TIM_CCER_CC1NE 0x0004U |
Capture/Compare 1 Complementary output enable
Definition at line 6379 of file stm32f407xx.h.
| #define TIM_CCER_CC1NP 0x0008U |
Capture/Compare 1 Complementary output Polarity
Definition at line 6380 of file stm32f407xx.h.
| #define TIM_CCER_CC1P 0x0002U |
Capture/Compare 1 output Polarity
Definition at line 6378 of file stm32f407xx.h.
| #define TIM_CCER_CC2E 0x0010U |
Capture/Compare 2 output enable
Definition at line 6381 of file stm32f407xx.h.
| #define TIM_CCER_CC2NE 0x0040U |
Capture/Compare 2 Complementary output enable
Definition at line 6383 of file stm32f407xx.h.
| #define TIM_CCER_CC2NP 0x0080U |
Capture/Compare 2 Complementary output Polarity
Definition at line 6384 of file stm32f407xx.h.
| #define TIM_CCER_CC2P 0x0020U |
Capture/Compare 2 output Polarity
Definition at line 6382 of file stm32f407xx.h.
| #define TIM_CCER_CC3E 0x0100U |
Capture/Compare 3 output enable
Definition at line 6385 of file stm32f407xx.h.
| #define TIM_CCER_CC3NE 0x0400U |
Capture/Compare 3 Complementary output enable
Definition at line 6387 of file stm32f407xx.h.
| #define TIM_CCER_CC3NP 0x0800U |
Capture/Compare 3 Complementary output Polarity
Definition at line 6388 of file stm32f407xx.h.
| #define TIM_CCER_CC3P 0x0200U |
Capture/Compare 3 output Polarity
Definition at line 6386 of file stm32f407xx.h.
| #define TIM_CCER_CC4E 0x1000U |
Capture/Compare 4 output enable
Definition at line 6389 of file stm32f407xx.h.
| #define TIM_CCER_CC4NP 0x8000U |
Capture/Compare 4 Complementary output Polarity
Definition at line 6391 of file stm32f407xx.h.
| #define TIM_CCER_CC4P 0x2000U |
Capture/Compare 4 output Polarity
Definition at line 6390 of file stm32f407xx.h.
| #define TIM_CCMR1_CC1S 0x0003U |
CC1S[1:0] bits (Capture/Compare 1 Selection)
Definition at line 6275 of file stm32f407xx.h.
| #define TIM_CCMR1_CC1S_0 0x0001U |
Bit 0
Definition at line 6276 of file stm32f407xx.h.
| #define TIM_CCMR1_CC1S_1 0x0002U |
Bit 1
Definition at line 6277 of file stm32f407xx.h.
| #define TIM_CCMR1_CC2S 0x0300U |
CC2S[1:0] bits (Capture/Compare 2 Selection)
Definition at line 6289 of file stm32f407xx.h.
| #define TIM_CCMR1_CC2S_0 0x0100U |
Bit 0
Definition at line 6290 of file stm32f407xx.h.
| #define TIM_CCMR1_CC2S_1 0x0200U |
Bit 1
Definition at line 6291 of file stm32f407xx.h.
| #define TIM_CCMR1_IC1F 0x00F0U |
IC1F[3:0] bits (Input Capture 1 Filter)
Definition at line 6309 of file stm32f407xx.h.
| #define TIM_CCMR1_IC1F_0 0x0010U |
Bit 0
Definition at line 6310 of file stm32f407xx.h.
| #define TIM_CCMR1_IC1F_1 0x0020U |
Bit 1
Definition at line 6311 of file stm32f407xx.h.
| #define TIM_CCMR1_IC1F_2 0x0040U |
Bit 2
Definition at line 6312 of file stm32f407xx.h.
| #define TIM_CCMR1_IC1F_3 0x0080U |
Bit 3
Definition at line 6313 of file stm32f407xx.h.
| #define TIM_CCMR1_IC1PSC 0x000CU |
IC1PSC[1:0] bits (Input Capture 1 Prescaler)
Definition at line 6305 of file stm32f407xx.h.
| #define TIM_CCMR1_IC1PSC_0 0x0004U |
Bit 0
Definition at line 6306 of file stm32f407xx.h.
| #define TIM_CCMR1_IC1PSC_1 0x0008U |
Bit 1
Definition at line 6307 of file stm32f407xx.h.
| #define TIM_CCMR1_IC2F 0xF000U |
IC2F[3:0] bits (Input Capture 2 Filter)
Definition at line 6319 of file stm32f407xx.h.
| #define TIM_CCMR1_IC2F_0 0x1000U |
Bit 0
Definition at line 6320 of file stm32f407xx.h.
| #define TIM_CCMR1_IC2F_1 0x2000U |
Bit 1
Definition at line 6321 of file stm32f407xx.h.
| #define TIM_CCMR1_IC2F_2 0x4000U |
Bit 2
Definition at line 6322 of file stm32f407xx.h.
| #define TIM_CCMR1_IC2F_3 0x8000U |
Bit 3
Definition at line 6323 of file stm32f407xx.h.
| #define TIM_CCMR1_IC2PSC 0x0C00U |
IC2PSC[1:0] bits (Input Capture 2 Prescaler)
Definition at line 6315 of file stm32f407xx.h.
| #define TIM_CCMR1_IC2PSC_0 0x0400U |
Bit 0
Definition at line 6316 of file stm32f407xx.h.
| #define TIM_CCMR1_IC2PSC_1 0x0800U |
Bit 1
Definition at line 6317 of file stm32f407xx.h.
| #define TIM_CCMR1_OC1CE 0x0080U |
Output Compare 1Clear Enable
Definition at line 6287 of file stm32f407xx.h.
| #define TIM_CCMR1_OC1FE 0x0004U |
Output Compare 1 Fast enable
Definition at line 6279 of file stm32f407xx.h.
| #define TIM_CCMR1_OC1M 0x0070U |
OC1M[2:0] bits (Output Compare 1 Mode)
Definition at line 6282 of file stm32f407xx.h.
| #define TIM_CCMR1_OC1M_0 0x0010U |
Bit 0
Definition at line 6283 of file stm32f407xx.h.
| #define TIM_CCMR1_OC1M_1 0x0020U |
Bit 1
Definition at line 6284 of file stm32f407xx.h.
| #define TIM_CCMR1_OC1M_2 0x0040U |
Bit 2
Definition at line 6285 of file stm32f407xx.h.
| #define TIM_CCMR1_OC1PE 0x0008U |
Output Compare 1 Preload enable
Definition at line 6280 of file stm32f407xx.h.
| #define TIM_CCMR1_OC2CE 0x8000U |
Output Compare 2 Clear Enable
Definition at line 6301 of file stm32f407xx.h.
| #define TIM_CCMR1_OC2FE 0x0400U |
Output Compare 2 Fast enable
Definition at line 6293 of file stm32f407xx.h.
| #define TIM_CCMR1_OC2M 0x7000U |
OC2M[2:0] bits (Output Compare 2 Mode)
Definition at line 6296 of file stm32f407xx.h.
| #define TIM_CCMR1_OC2M_0 0x1000U |
Bit 0
Definition at line 6297 of file stm32f407xx.h.
| #define TIM_CCMR1_OC2M_1 0x2000U |
Bit 1
Definition at line 6298 of file stm32f407xx.h.
| #define TIM_CCMR1_OC2M_2 0x4000U |
Bit 2
Definition at line 6299 of file stm32f407xx.h.
| #define TIM_CCMR1_OC2PE 0x0800U |
Output Compare 2 Preload enable
Definition at line 6294 of file stm32f407xx.h.
| #define TIM_CCMR2_CC3S 0x0003U |
CC3S[1:0] bits (Capture/Compare 3 Selection)
Definition at line 6326 of file stm32f407xx.h.
| #define TIM_CCMR2_CC3S_0 0x0001U |
Bit 0
Definition at line 6327 of file stm32f407xx.h.
| #define TIM_CCMR2_CC3S_1 0x0002U |
Bit 1
Definition at line 6328 of file stm32f407xx.h.
| #define TIM_CCMR2_CC4S 0x0300U |
CC4S[1:0] bits (Capture/Compare 4 Selection)
Definition at line 6340 of file stm32f407xx.h.
| #define TIM_CCMR2_CC4S_0 0x0100U |
Bit 0
Definition at line 6341 of file stm32f407xx.h.
| #define TIM_CCMR2_CC4S_1 0x0200U |
Bit 1
Definition at line 6342 of file stm32f407xx.h.
| #define TIM_CCMR2_IC3F 0x00F0U |
IC3F[3:0] bits (Input Capture 3 Filter)
Definition at line 6360 of file stm32f407xx.h.
| #define TIM_CCMR2_IC3F_0 0x0010U |
Bit 0
Definition at line 6361 of file stm32f407xx.h.
| #define TIM_CCMR2_IC3F_1 0x0020U |
Bit 1
Definition at line 6362 of file stm32f407xx.h.
| #define TIM_CCMR2_IC3F_2 0x0040U |
Bit 2
Definition at line 6363 of file stm32f407xx.h.
| #define TIM_CCMR2_IC3F_3 0x0080U |
Bit 3
Definition at line 6364 of file stm32f407xx.h.
| #define TIM_CCMR2_IC3PSC 0x000CU |
IC3PSC[1:0] bits (Input Capture 3 Prescaler)
Definition at line 6356 of file stm32f407xx.h.
| #define TIM_CCMR2_IC3PSC_0 0x0004U |
Bit 0
Definition at line 6357 of file stm32f407xx.h.
| #define TIM_CCMR2_IC3PSC_1 0x0008U |
Bit 1
Definition at line 6358 of file stm32f407xx.h.
| #define TIM_CCMR2_IC4F 0xF000U |
IC4F[3:0] bits (Input Capture 4 Filter)
Definition at line 6370 of file stm32f407xx.h.
| #define TIM_CCMR2_IC4F_0 0x1000U |
Bit 0
Definition at line 6371 of file stm32f407xx.h.
| #define TIM_CCMR2_IC4F_1 0x2000U |
Bit 1
Definition at line 6372 of file stm32f407xx.h.
| #define TIM_CCMR2_IC4F_2 0x4000U |
Bit 2
Definition at line 6373 of file stm32f407xx.h.
| #define TIM_CCMR2_IC4F_3 0x8000U |
Bit 3
Definition at line 6374 of file stm32f407xx.h.
| #define TIM_CCMR2_IC4PSC 0x0C00U |
IC4PSC[1:0] bits (Input Capture 4 Prescaler)
Definition at line 6366 of file stm32f407xx.h.
| #define TIM_CCMR2_IC4PSC_0 0x0400U |
Bit 0
Definition at line 6367 of file stm32f407xx.h.
| #define TIM_CCMR2_IC4PSC_1 0x0800U |
Bit 1
Definition at line 6368 of file stm32f407xx.h.
| #define TIM_CCMR2_OC3CE 0x0080U |
Output Compare 3 Clear Enable
Definition at line 6338 of file stm32f407xx.h.
| #define TIM_CCMR2_OC3FE 0x0004U |
Output Compare 3 Fast enable
Definition at line 6330 of file stm32f407xx.h.
| #define TIM_CCMR2_OC3M 0x0070U |
OC3M[2:0] bits (Output Compare 3 Mode)
Definition at line 6333 of file stm32f407xx.h.
| #define TIM_CCMR2_OC3M_0 0x0010U |
Bit 0
Definition at line 6334 of file stm32f407xx.h.
| #define TIM_CCMR2_OC3M_1 0x0020U |
Bit 1
Definition at line 6335 of file stm32f407xx.h.
| #define TIM_CCMR2_OC3M_2 0x0040U |
Bit 2
Definition at line 6336 of file stm32f407xx.h.
| #define TIM_CCMR2_OC3PE 0x0008U |
Output Compare 3 Preload enable
Definition at line 6331 of file stm32f407xx.h.
| #define TIM_CCMR2_OC4CE 0x8000U |
Output Compare 4 Clear Enable
Definition at line 6352 of file stm32f407xx.h.
| #define TIM_CCMR2_OC4FE 0x0400U |
Output Compare 4 Fast enable
Definition at line 6344 of file stm32f407xx.h.
| #define TIM_CCMR2_OC4M 0x7000U |
OC4M[2:0] bits (Output Compare 4 Mode)
Definition at line 6347 of file stm32f407xx.h.
| #define TIM_CCMR2_OC4M_0 0x1000U |
Bit 0
Definition at line 6348 of file stm32f407xx.h.
| #define TIM_CCMR2_OC4M_1 0x2000U |
Bit 1
Definition at line 6349 of file stm32f407xx.h.
| #define TIM_CCMR2_OC4M_2 0x4000U |
Bit 2
Definition at line 6350 of file stm32f407xx.h.
| #define TIM_CCMR2_OC4PE 0x0800U |
Output Compare 4 Preload enable
Definition at line 6345 of file stm32f407xx.h.
| #define TIM_CCR1_CCR1 0xFFFFU |
Capture/Compare 1 Value
Definition at line 6406 of file stm32f407xx.h.
| #define TIM_CCR2_CCR2 0xFFFFU |
Capture/Compare 2 Value
Definition at line 6409 of file stm32f407xx.h.
| #define TIM_CCR3_CCR3 0xFFFFU |
Capture/Compare 3 Value
Definition at line 6412 of file stm32f407xx.h.
| #define TIM_CCR4_CCR4 0xFFFFU |
Capture/Compare 4 Value
Definition at line 6415 of file stm32f407xx.h.
| #define TIM_CNT_CNT 0xFFFFU |
Counter Value
Definition at line 6394 of file stm32f407xx.h.
| #define TIM_CR1_ARPE 0x0080U |
Auto-reload preload enable
Definition at line 6182 of file stm32f407xx.h.
| #define TIM_CR1_CEN 0x0001U |
Counter enable
Definition at line 6172 of file stm32f407xx.h.
| #define TIM_CR1_CKD 0x0300U |
CKD[1:0] bits (clock division)
Definition at line 6184 of file stm32f407xx.h.
| #define TIM_CR1_CKD_0 0x0100U |
Bit 0
Definition at line 6185 of file stm32f407xx.h.
| #define TIM_CR1_CKD_1 0x0200U |
Bit 1
Definition at line 6186 of file stm32f407xx.h.
| #define TIM_CR1_CMS 0x0060U |
CMS[1:0] bits (Center-aligned mode selection)
Definition at line 6178 of file stm32f407xx.h.
| #define TIM_CR1_CMS_0 0x0020U |
Bit 0
Definition at line 6179 of file stm32f407xx.h.
| #define TIM_CR1_CMS_1 0x0040U |
Bit 1
Definition at line 6180 of file stm32f407xx.h.
| #define TIM_CR1_DIR 0x0010U |
Direction
Definition at line 6176 of file stm32f407xx.h.
| #define TIM_CR1_OPM 0x0008U |
One pulse mode
Definition at line 6175 of file stm32f407xx.h.
| #define TIM_CR1_UDIS 0x0002U |
Update disable
Definition at line 6173 of file stm32f407xx.h.
| #define TIM_CR1_URS 0x0004U |
Update request source
Definition at line 6174 of file stm32f407xx.h.
| #define TIM_CR2_CCDS 0x0008U |
Capture/Compare DMA Selection
Definition at line 6191 of file stm32f407xx.h.
| #define TIM_CR2_CCPC 0x0001U |
Capture/Compare Preloaded Control
Definition at line 6189 of file stm32f407xx.h.
| #define TIM_CR2_CCUS 0x0004U |
Capture/Compare Control Update Selection
Definition at line 6190 of file stm32f407xx.h.
| #define TIM_CR2_MMS 0x0070U |
MMS[2:0] bits (Master Mode Selection)
Definition at line 6193 of file stm32f407xx.h.
| #define TIM_CR2_MMS_0 0x0010U |
Bit 0
Definition at line 6194 of file stm32f407xx.h.
| #define TIM_CR2_MMS_1 0x0020U |
Bit 1
Definition at line 6195 of file stm32f407xx.h.
| #define TIM_CR2_MMS_2 0x0040U |
Bit 2
Definition at line 6196 of file stm32f407xx.h.
| #define TIM_CR2_OIS1 0x0100U |
Output Idle state 1 (OC1 output)
Definition at line 6199 of file stm32f407xx.h.
| #define TIM_CR2_OIS1N 0x0200U |
Output Idle state 1 (OC1N output)
Definition at line 6200 of file stm32f407xx.h.
| #define TIM_CR2_OIS2 0x0400U |
Output Idle state 2 (OC2 output)
Definition at line 6201 of file stm32f407xx.h.
| #define TIM_CR2_OIS2N 0x0800U |
Output Idle state 2 (OC2N output)
Definition at line 6202 of file stm32f407xx.h.
| #define TIM_CR2_OIS3 0x1000U |
Output Idle state 3 (OC3 output)
Definition at line 6203 of file stm32f407xx.h.
| #define TIM_CR2_OIS3N 0x2000U |
Output Idle state 3 (OC3N output)
Definition at line 6204 of file stm32f407xx.h.
| #define TIM_CR2_OIS4 0x4000U |
Output Idle state 4 (OC4 output)
Definition at line 6205 of file stm32f407xx.h.
| #define TIM_CR2_TI1S 0x0080U |
TI1 Selection
Definition at line 6198 of file stm32f407xx.h.
| #define TIM_DCR_DBA 0x001FU |
DBA[4:0] bits (DMA Base Address)
Definition at line 6440 of file stm32f407xx.h.
| #define TIM_DCR_DBA_0 0x0001U |
Bit 0
Definition at line 6441 of file stm32f407xx.h.
| #define TIM_DCR_DBA_1 0x0002U |
Bit 1
Definition at line 6442 of file stm32f407xx.h.
| #define TIM_DCR_DBA_2 0x0004U |
Bit 2
Definition at line 6443 of file stm32f407xx.h.
| #define TIM_DCR_DBA_3 0x0008U |
Bit 3
Definition at line 6444 of file stm32f407xx.h.
| #define TIM_DCR_DBA_4 0x0010U |
Bit 4
Definition at line 6445 of file stm32f407xx.h.
| #define TIM_DCR_DBL 0x1F00U |
DBL[4:0] bits (DMA Burst Length)
Definition at line 6447 of file stm32f407xx.h.
| #define TIM_DCR_DBL_0 0x0100U |
Bit 0
Definition at line 6448 of file stm32f407xx.h.
| #define TIM_DCR_DBL_1 0x0200U |
Bit 1
Definition at line 6449 of file stm32f407xx.h.
| #define TIM_DCR_DBL_2 0x0400U |
Bit 2
Definition at line 6450 of file stm32f407xx.h.
| #define TIM_DCR_DBL_3 0x0800U |
Bit 3
Definition at line 6451 of file stm32f407xx.h.
| #define TIM_DCR_DBL_4 0x1000U |
Bit 4
Definition at line 6452 of file stm32f407xx.h.
| #define TIM_DIER_BIE 0x0080U |
Break interrupt enable
Definition at line 6241 of file stm32f407xx.h.
| #define TIM_DIER_CC1DE 0x0200U |
Capture/Compare 1 DMA request enable
Definition at line 6243 of file stm32f407xx.h.
| #define TIM_DIER_CC1IE 0x0002U |
Capture/Compare 1 interrupt enable
Definition at line 6235 of file stm32f407xx.h.
| #define TIM_DIER_CC2DE 0x0400U |
Capture/Compare 2 DMA request enable
Definition at line 6244 of file stm32f407xx.h.
| #define TIM_DIER_CC2IE 0x0004U |
Capture/Compare 2 interrupt enable
Definition at line 6236 of file stm32f407xx.h.
| #define TIM_DIER_CC3DE 0x0800U |
Capture/Compare 3 DMA request enable
Definition at line 6245 of file stm32f407xx.h.
| #define TIM_DIER_CC3IE 0x0008U |
Capture/Compare 3 interrupt enable
Definition at line 6237 of file stm32f407xx.h.
| #define TIM_DIER_CC4DE 0x1000U |
Capture/Compare 4 DMA request enable
Definition at line 6246 of file stm32f407xx.h.
| #define TIM_DIER_CC4IE 0x0010U |
Capture/Compare 4 interrupt enable
Definition at line 6238 of file stm32f407xx.h.
| #define TIM_DIER_COMDE 0x2000U |
COM DMA request enable
Definition at line 6247 of file stm32f407xx.h.
| #define TIM_DIER_COMIE 0x0020U |
COM interrupt enable
Definition at line 6239 of file stm32f407xx.h.
| #define TIM_DIER_TDE 0x4000U |
Trigger DMA request enable
Definition at line 6248 of file stm32f407xx.h.
| #define TIM_DIER_TIE 0x0040U |
Trigger interrupt enable
Definition at line 6240 of file stm32f407xx.h.
| #define TIM_DIER_UDE 0x0100U |
Update DMA request enable
Definition at line 6242 of file stm32f407xx.h.
| #define TIM_DIER_UIE 0x0001U |
Update interrupt enable
Definition at line 6234 of file stm32f407xx.h.
| #define TIM_DMAR_DMAB 0xFFFFU |
DMA register for burst accesses
Definition at line 6455 of file stm32f407xx.h.
| #define TIM_EGR_BG 0x80U |
Break Generation
Definition at line 6272 of file stm32f407xx.h.
| #define TIM_EGR_CC1G 0x02U |
Capture/Compare 1 Generation
Definition at line 6266 of file stm32f407xx.h.
| #define TIM_EGR_CC2G 0x04U |
Capture/Compare 2 Generation
Definition at line 6267 of file stm32f407xx.h.
| #define TIM_EGR_CC3G 0x08U |
Capture/Compare 3 Generation
Definition at line 6268 of file stm32f407xx.h.
| #define TIM_EGR_CC4G 0x10U |
Capture/Compare 4 Generation
Definition at line 6269 of file stm32f407xx.h.
| #define TIM_EGR_COMG 0x20U |
Capture/Compare Control Update Generation
Definition at line 6270 of file stm32f407xx.h.
| #define TIM_EGR_TG 0x40U |
Trigger Generation
Definition at line 6271 of file stm32f407xx.h.
| #define TIM_EGR_UG 0x01U |
Update Generation
Definition at line 6265 of file stm32f407xx.h.
| #define TIM_OR_ITR1_RMP 0x0C00U |
ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap)
Definition at line 6461 of file stm32f407xx.h.
| #define TIM_OR_ITR1_RMP_0 0x0400U |
Bit 0
Definition at line 6462 of file stm32f407xx.h.
| #define TIM_OR_ITR1_RMP_1 0x0800U |
Bit 1
Definition at line 6463 of file stm32f407xx.h.
| #define TIM_OR_TI4_RMP 0x00C0U |
TI4_RMP[1:0] bits (TIM5 Input 4 remap)
Definition at line 6458 of file stm32f407xx.h.
| #define TIM_OR_TI4_RMP_0 0x0040U |
Bit 0
Definition at line 6459 of file stm32f407xx.h.
| #define TIM_OR_TI4_RMP_1 0x0080U |
Bit 1
Definition at line 6460 of file stm32f407xx.h.
| #define TIM_PSC_PSC 0xFFFFU |
Prescaler Value
Definition at line 6397 of file stm32f407xx.h.
| #define TIM_RCR_REP 0xFFU |
Repetition Counter Value
Definition at line 6403 of file stm32f407xx.h.
| #define TIM_SMCR_ECE 0x4000U |
External clock enable
Definition at line 6230 of file stm32f407xx.h.
| #define TIM_SMCR_ETF 0x0F00U |
ETF[3:0] bits (External trigger filter)
Definition at line 6220 of file stm32f407xx.h.
| #define TIM_SMCR_ETF_0 0x0100U |
Bit 0
Definition at line 6221 of file stm32f407xx.h.
| #define TIM_SMCR_ETF_1 0x0200U |
Bit 1
Definition at line 6222 of file stm32f407xx.h.
| #define TIM_SMCR_ETF_2 0x0400U |
Bit 2
Definition at line 6223 of file stm32f407xx.h.
| #define TIM_SMCR_ETF_3 0x0800U |
Bit 3
Definition at line 6224 of file stm32f407xx.h.
| #define TIM_SMCR_ETP 0x8000U |
External trigger polarity
Definition at line 6231 of file stm32f407xx.h.
| #define TIM_SMCR_ETPS 0x3000U |
ETPS[1:0] bits (External trigger prescaler)
Definition at line 6226 of file stm32f407xx.h.
| #define TIM_SMCR_ETPS_0 0x1000U |
Bit 0
Definition at line 6227 of file stm32f407xx.h.
| #define TIM_SMCR_ETPS_1 0x2000U |
Bit 1
Definition at line 6228 of file stm32f407xx.h.
| #define TIM_SMCR_MSM 0x0080U |
Master/slave mode
Definition at line 6218 of file stm32f407xx.h.
| #define TIM_SMCR_SMS 0x0007U |
SMS[2:0] bits (Slave mode selection)
Definition at line 6208 of file stm32f407xx.h.
| #define TIM_SMCR_SMS_0 0x0001U |
Bit 0
Definition at line 6209 of file stm32f407xx.h.
| #define TIM_SMCR_SMS_1 0x0002U |
Bit 1
Definition at line 6210 of file stm32f407xx.h.
| #define TIM_SMCR_SMS_2 0x0004U |
Bit 2
Definition at line 6211 of file stm32f407xx.h.
| #define TIM_SMCR_TS 0x0070U |
TS[2:0] bits (Trigger selection)
Definition at line 6213 of file stm32f407xx.h.
| #define TIM_SMCR_TS_0 0x0010U |
Bit 0
Definition at line 6214 of file stm32f407xx.h.
| #define TIM_SMCR_TS_1 0x0020U |
Bit 1
Definition at line 6215 of file stm32f407xx.h.
| #define TIM_SMCR_TS_2 0x0040U |
Bit 2
Definition at line 6216 of file stm32f407xx.h.
| #define TIM_SR_BIF 0x0080U |
Break interrupt Flag
Definition at line 6258 of file stm32f407xx.h.
| #define TIM_SR_CC1IF 0x0002U |
Capture/Compare 1 interrupt Flag
Definition at line 6252 of file stm32f407xx.h.
| #define TIM_SR_CC1OF 0x0200U |
Capture/Compare 1 Overcapture Flag
Definition at line 6259 of file stm32f407xx.h.
| #define TIM_SR_CC2IF 0x0004U |
Capture/Compare 2 interrupt Flag
Definition at line 6253 of file stm32f407xx.h.
| #define TIM_SR_CC2OF 0x0400U |
Capture/Compare 2 Overcapture Flag
Definition at line 6260 of file stm32f407xx.h.
| #define TIM_SR_CC3IF 0x0008U |
Capture/Compare 3 interrupt Flag
Definition at line 6254 of file stm32f407xx.h.
| #define TIM_SR_CC3OF 0x0800U |
Capture/Compare 3 Overcapture Flag
Definition at line 6261 of file stm32f407xx.h.
| #define TIM_SR_CC4IF 0x0010U |
Capture/Compare 4 interrupt Flag
Definition at line 6255 of file stm32f407xx.h.
| #define TIM_SR_CC4OF 0x1000U |
Capture/Compare 4 Overcapture Flag
Definition at line 6262 of file stm32f407xx.h.
| #define TIM_SR_COMIF 0x0020U |
COM interrupt Flag
Definition at line 6256 of file stm32f407xx.h.
| #define TIM_SR_TIF 0x0040U |
Trigger interrupt Flag
Definition at line 6257 of file stm32f407xx.h.
| #define TIM_SR_UIF 0x0001U |
Update interrupt Flag
Definition at line 6251 of file stm32f407xx.h.
| #define USART_BRR_DIV_Fraction 0x000FU |
Fraction of USARTDIV
Definition at line 6487 of file stm32f407xx.h.
| #define USART_BRR_DIV_Mantissa 0xFFF0U |
Mantissa of USARTDIV
Definition at line 6488 of file stm32f407xx.h.
| #define USART_CR1_IDLEIE 0x0010U |
IDLE Interrupt Enable
Definition at line 6495 of file stm32f407xx.h.
| #define USART_CR1_M 0x1000U |
Word length
Definition at line 6503 of file stm32f407xx.h.
| #define USART_CR1_OVER8 0x8000U |
USART Oversampling by 8 enable
Definition at line 6505 of file stm32f407xx.h.
| #define USART_CR1_PCE 0x0400U |
Parity Control Enable
Definition at line 6501 of file stm32f407xx.h.
| #define USART_CR1_PEIE 0x0100U |
PE Interrupt Enable
Definition at line 6499 of file stm32f407xx.h.
| #define USART_CR1_PS 0x0200U |
Parity Selection
Definition at line 6500 of file stm32f407xx.h.
| #define USART_CR1_RE 0x0004U |
Receiver Enable
Definition at line 6493 of file stm32f407xx.h.
| #define USART_CR1_RWU 0x0002U |
Receiver wakeup
Definition at line 6492 of file stm32f407xx.h.
| #define USART_CR1_RXNEIE 0x0020U |
RXNE Interrupt Enable
Definition at line 6496 of file stm32f407xx.h.
| #define USART_CR1_SBK 0x0001U |
Send Break
Definition at line 6491 of file stm32f407xx.h.
| #define USART_CR1_TCIE 0x0040U |
Transmission Complete Interrupt Enable
Definition at line 6497 of file stm32f407xx.h.
| #define USART_CR1_TE 0x0008U |
Transmitter Enable
Definition at line 6494 of file stm32f407xx.h.
| #define USART_CR1_TXEIE 0x0080U |
PE Interrupt Enable
Definition at line 6498 of file stm32f407xx.h.
| #define USART_CR1_UE 0x2000U |
USART Enable
Definition at line 6504 of file stm32f407xx.h.
| #define USART_CR1_WAKE 0x0800U |
Wakeup method
Definition at line 6502 of file stm32f407xx.h.
| #define USART_CR2_ADD 0x000FU |
Address of the USART node
Definition at line 6508 of file stm32f407xx.h.
| #define USART_CR2_CLKEN 0x0800U |
Clock Enable
Definition at line 6514 of file stm32f407xx.h.
| #define USART_CR2_CPHA 0x0200U |
Clock Phase
Definition at line 6512 of file stm32f407xx.h.
| #define USART_CR2_CPOL 0x0400U |
Clock Polarity
Definition at line 6513 of file stm32f407xx.h.
| #define USART_CR2_LBCL 0x0100U |
Last Bit Clock pulse
Definition at line 6511 of file stm32f407xx.h.
| #define USART_CR2_LBDIE 0x0040U |
LIN Break Detection Interrupt Enable
Definition at line 6510 of file stm32f407xx.h.
| #define USART_CR2_LBDL 0x0020U |
LIN Break Detection Length
Definition at line 6509 of file stm32f407xx.h.
| #define USART_CR2_LINEN 0x4000U |
LIN mode enable
Definition at line 6520 of file stm32f407xx.h.
| #define USART_CR2_STOP 0x3000U |
STOP[1:0] bits (STOP bits)
Definition at line 6516 of file stm32f407xx.h.
| #define USART_CR2_STOP_0 0x1000U |
Bit 0
Definition at line 6517 of file stm32f407xx.h.
| #define USART_CR2_STOP_1 0x2000U |
Bit 1
Definition at line 6518 of file stm32f407xx.h.
| #define USART_CR3_CTSE 0x0200U |
CTS Enable
Definition at line 6532 of file stm32f407xx.h.
| #define USART_CR3_CTSIE 0x0400U |
CTS Interrupt Enable
Definition at line 6533 of file stm32f407xx.h.
| #define USART_CR3_DMAR 0x0040U |
DMA Enable Receiver
Definition at line 6529 of file stm32f407xx.h.
| #define USART_CR3_DMAT 0x0080U |
DMA Enable Transmitter
Definition at line 6530 of file stm32f407xx.h.
| #define USART_CR3_EIE 0x0001U |
Error Interrupt Enable
Definition at line 6523 of file stm32f407xx.h.
| #define USART_CR3_HDSEL 0x0008U |
Half-Duplex Selection
Definition at line 6526 of file stm32f407xx.h.
| #define USART_CR3_IREN 0x0002U |
IrDA mode Enable
Definition at line 6524 of file stm32f407xx.h.
| #define USART_CR3_IRLP 0x0004U |
IrDA Low-Power
Definition at line 6525 of file stm32f407xx.h.
| #define USART_CR3_NACK 0x0010U |
Smartcard NACK enable
Definition at line 6527 of file stm32f407xx.h.
| #define USART_CR3_ONEBIT 0x0800U |
USART One bit method enable
Definition at line 6534 of file stm32f407xx.h.
| #define USART_CR3_RTSE 0x0100U |
RTS Enable
Definition at line 6531 of file stm32f407xx.h.
| #define USART_CR3_SCEN 0x0020U |
Smartcard mode enable
Definition at line 6528 of file stm32f407xx.h.
| #define USART_DR_DR 0x01FFU |
Data value
Definition at line 6484 of file stm32f407xx.h.
| #define USART_GTPR_GT 0xFF00U |
Guard time value
Definition at line 6547 of file stm32f407xx.h.
| #define USART_GTPR_PSC 0x00FFU |
PSC[7:0] bits (Prescaler value)
Definition at line 6537 of file stm32f407xx.h.
| #define USART_GTPR_PSC_0 0x0001U |
Bit 0
Definition at line 6538 of file stm32f407xx.h.
| #define USART_GTPR_PSC_1 0x0002U |
Bit 1
Definition at line 6539 of file stm32f407xx.h.
| #define USART_GTPR_PSC_2 0x0004U |
Bit 2
Definition at line 6540 of file stm32f407xx.h.
| #define USART_GTPR_PSC_3 0x0008U |
Bit 3
Definition at line 6541 of file stm32f407xx.h.
| #define USART_GTPR_PSC_4 0x0010U |
Bit 4
Definition at line 6542 of file stm32f407xx.h.
| #define USART_GTPR_PSC_5 0x0020U |
Bit 5
Definition at line 6543 of file stm32f407xx.h.
| #define USART_GTPR_PSC_6 0x0040U |
Bit 6
Definition at line 6544 of file stm32f407xx.h.
| #define USART_GTPR_PSC_7 0x0080U |
Bit 7
Definition at line 6545 of file stm32f407xx.h.
| #define USART_SR_CTS 0x0200U |
CTS Flag
Definition at line 6481 of file stm32f407xx.h.
| #define USART_SR_FE 0x0002U |
Framing Error
Definition at line 6473 of file stm32f407xx.h.
| #define USART_SR_IDLE 0x0010U |
IDLE line detected
Definition at line 6476 of file stm32f407xx.h.
| #define USART_SR_LBD 0x0100U |
LIN Break Detection Flag
Definition at line 6480 of file stm32f407xx.h.
| #define USART_SR_NE 0x0004U |
Noise Error Flag
Definition at line 6474 of file stm32f407xx.h.
| #define USART_SR_ORE 0x0008U |
OverRun Error
Definition at line 6475 of file stm32f407xx.h.
| #define USART_SR_PE 0x0001U |
Parity Error
Definition at line 6472 of file stm32f407xx.h.
| #define USART_SR_RXNE 0x0020U |
Read Data Register Not Empty
Definition at line 6477 of file stm32f407xx.h.
| #define USART_SR_TC 0x0040U |
Transmission Complete
Definition at line 6478 of file stm32f407xx.h.
| #define USART_SR_TXE 0x0080U |
Transmit Data Register Empty
Definition at line 6479 of file stm32f407xx.h.
| #define USB_OTG_BCNT 0x00007FF0U |
Byte count
Definition at line 7390 of file stm32f407xx.h.
| #define USB_OTG_BCNT 0x00007FF0U |
Byte count
Definition at line 7390 of file stm32f407xx.h.
| #define USB_OTG_CHNUM 0x0000000FU |
Channel number
Definition at line 7385 of file stm32f407xx.h.
| #define USB_OTG_CHNUM 0x0000000FU |
Channel number
Definition at line 7385 of file stm32f407xx.h.
| #define USB_OTG_CHNUM_0 0x00000001U |
Bit 0
Definition at line 7386 of file stm32f407xx.h.
| #define USB_OTG_CHNUM_0 0x00000001U |
Bit 0
Definition at line 7386 of file stm32f407xx.h.
| #define USB_OTG_CHNUM_1 0x00000002U |
Bit 1
Definition at line 7387 of file stm32f407xx.h.
| #define USB_OTG_CHNUM_1 0x00000002U |
Bit 1
Definition at line 7387 of file stm32f407xx.h.
| #define USB_OTG_CHNUM_2 0x00000004U |
Bit 2
Definition at line 7388 of file stm32f407xx.h.
| #define USB_OTG_CHNUM_2 0x00000004U |
Bit 2
Definition at line 7388 of file stm32f407xx.h.
| #define USB_OTG_CHNUM_3 0x00000008U |
Bit 3
Definition at line 7389 of file stm32f407xx.h.
| #define USB_OTG_CHNUM_3 0x00000008U |
Bit 3
Definition at line 7389 of file stm32f407xx.h.
| #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU |
Product ID field
Definition at line 7499 of file stm32f407xx.h.
| #define USB_OTG_DAINT_IEPINT 0x0000FFFFU |
IN endpoint interrupt bits
Definition at line 7336 of file stm32f407xx.h.
| #define USB_OTG_DAINT_OEPINT 0xFFFF0000U |
OUT endpoint interrupt bits
Definition at line 7337 of file stm32f407xx.h.
| #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU |
IN EP interrupt mask bits
Definition at line 7349 of file stm32f407xx.h.
| #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U |
OUT EP interrupt mask bits
Definition at line 7350 of file stm32f407xx.h.
| #define USB_OTG_DCFG_DAD 0x000007F0U |
Device address
Definition at line 7115 of file stm32f407xx.h.
| #define USB_OTG_DCFG_DAD_0 0x00000010U |
Bit 0
Definition at line 7116 of file stm32f407xx.h.
| #define USB_OTG_DCFG_DAD_1 0x00000020U |
Bit 1
Definition at line 7117 of file stm32f407xx.h.
| #define USB_OTG_DCFG_DAD_2 0x00000040U |
Bit 2
Definition at line 7118 of file stm32f407xx.h.
| #define USB_OTG_DCFG_DAD_3 0x00000080U |
Bit 3
Definition at line 7119 of file stm32f407xx.h.
| #define USB_OTG_DCFG_DAD_4 0x00000100U |
Bit 4
Definition at line 7120 of file stm32f407xx.h.
| #define USB_OTG_DCFG_DAD_5 0x00000200U |
Bit 5
Definition at line 7121 of file stm32f407xx.h.
| #define USB_OTG_DCFG_DAD_6 0x00000400U |
Bit 6
Definition at line 7122 of file stm32f407xx.h.
| #define USB_OTG_DCFG_DSPD 0x00000003U |
Device speed
Definition at line 7110 of file stm32f407xx.h.
| #define USB_OTG_DCFG_DSPD_0 0x00000001U |
Bit 0
Definition at line 7111 of file stm32f407xx.h.
| #define USB_OTG_DCFG_DSPD_1 0x00000002U |
Bit 1
Definition at line 7112 of file stm32f407xx.h.
| #define USB_OTG_DCFG_NZLSOHSK 0x00000004U |
Nonzero-length status OUT handshake
Definition at line 7113 of file stm32f407xx.h.
| #define USB_OTG_DCFG_PERSCHIVL 0x03000000U |
Periodic scheduling interval
Definition at line 7128 of file stm32f407xx.h.
| #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U |
Bit 0
Definition at line 7129 of file stm32f407xx.h.
| #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U |
Bit 1
Definition at line 7130 of file stm32f407xx.h.
| #define USB_OTG_DCFG_PFIVL 0x00001800U |
Periodic (micro)frame interval
Definition at line 7124 of file stm32f407xx.h.
| #define USB_OTG_DCFG_PFIVL_0 0x00000800U |
Bit 0
Definition at line 7125 of file stm32f407xx.h.
| #define USB_OTG_DCFG_PFIVL_1 0x00001000U |
Bit 1
Definition at line 7126 of file stm32f407xx.h.
| #define USB_OTG_DCTL_CGINAK 0x00000100U |
Clear global IN NAK
Definition at line 7156 of file stm32f407xx.h.
| #define USB_OTG_DCTL_CGONAK 0x00000400U |
Clear global OUT NAK
Definition at line 7158 of file stm32f407xx.h.
| #define USB_OTG_DCTL_GINSTS 0x00000004U |
Global IN NAK status
Definition at line 7148 of file stm32f407xx.h.
| #define USB_OTG_DCTL_GONSTS 0x00000008U |
Global OUT NAK status
Definition at line 7149 of file stm32f407xx.h.
| #define USB_OTG_DCTL_POPRGDNE 0x00000800U |
Power-on programming done
Definition at line 7159 of file stm32f407xx.h.
| #define USB_OTG_DCTL_RWUSIG 0x00000001U |
Remote wakeup signaling
Definition at line 7146 of file stm32f407xx.h.
| #define USB_OTG_DCTL_SDIS 0x00000002U |
Soft disconnect
Definition at line 7147 of file stm32f407xx.h.
| #define USB_OTG_DCTL_SGINAK 0x00000080U |
Set global IN NAK
Definition at line 7155 of file stm32f407xx.h.
| #define USB_OTG_DCTL_SGONAK 0x00000200U |
Set global OUT NAK
Definition at line 7157 of file stm32f407xx.h.
| #define USB_OTG_DCTL_TCTL 0x00000070U |
Test control
Definition at line 7151 of file stm32f407xx.h.
| #define USB_OTG_DCTL_TCTL_0 0x00000010U |
Bit 0
Definition at line 7152 of file stm32f407xx.h.
| #define USB_OTG_DCTL_TCTL_1 0x00000020U |
Bit 1
Definition at line 7153 of file stm32f407xx.h.
| #define USB_OTG_DCTL_TCTL_2 0x00000040U |
Bit 2
Definition at line 7154 of file stm32f407xx.h.
| #define USB_OTG_DEACHINT_IEP1INT 0x00000002U |
IN endpoint 1interrupt bit
Definition at line 7483 of file stm32f407xx.h.
| #define USB_OTG_DEACHINT_OEP1INT 0x00020000U |
OUT endpoint 1 interrupt bit
Definition at line 7484 of file stm32f407xx.h.
| #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U |
IN Endpoint 1 interrupt mask bit
Definition at line 7495 of file stm32f407xx.h.
| #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U |
OUT Endpoint 1 interrupt mask bit
Definition at line 7496 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_CNAK 0x04000000U |
Clear NAK
Definition at line 7571 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U |
Even/odd frame
Definition at line 7558 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_EPDIS 0x40000000U |
Endpoint disable
Definition at line 7575 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_EPENA 0x80000000U |
Endpoint enable
Definition at line 7576 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U |
Endpoint type
Definition at line 7561 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U |
Bit 0
Definition at line 7562 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U |
Bit 1
Definition at line 7563 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU |
Maximum packet size
Definition at line 7556 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U |
NAK status
Definition at line 7559 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U |
Set DATA0 PID
Definition at line 7573 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_SNAK 0x08000000U |
Set NAK
Definition at line 7572 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U |
Set odd frame
Definition at line 7574 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_STALL 0x00200000U |
STALL handshake
Definition at line 7564 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U |
TxFIFO number
Definition at line 7566 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U |
Bit 0
Definition at line 7567 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U |
Bit 1
Definition at line 7568 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U |
Bit 2
Definition at line 7569 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U |
Bit 3
Definition at line 7570 of file stm32f407xx.h.
| #define USB_OTG_DIEPCTL_USBAEP 0x00008000U |
USB active endpoint
Definition at line 7557 of file stm32f407xx.h.
| #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU |
DMA address
Definition at line 7688 of file stm32f407xx.h.
| #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U |
BNA interrupt mask
Definition at line 7509 of file stm32f407xx.h.
| #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U |
Endpoint disabled interrupt mask
Definition at line 7503 of file stm32f407xx.h.
| #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U |
IN endpoint NAK effective mask
Definition at line 7507 of file stm32f407xx.h.
| #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U |
IN token received with EP mismatch mask
Definition at line 7506 of file stm32f407xx.h.
| #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U |
IN token received when TxFIFO empty mask
Definition at line 7505 of file stm32f407xx.h.
| #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U |
NAK interrupt mask
Definition at line 7510 of file stm32f407xx.h.
| #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U |
Timeout condition mask (nonisochronous endpoints)
Definition at line 7504 of file stm32f407xx.h.
| #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U |
FIFO underrun mask
Definition at line 7508 of file stm32f407xx.h.
| #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U |
Transfer completed interrupt mask
Definition at line 7502 of file stm32f407xx.h.
| #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU |
IN EP Tx FIFO empty interrupt mask bits
Definition at line 7480 of file stm32f407xx.h.
| #define USB_OTG_DIEPINT_BERR 0x00001000U |
Babble error interrupt
Definition at line 7658 of file stm32f407xx.h.
| #define USB_OTG_DIEPINT_BNA 0x00000200U |
Buffer not available interrupt
Definition at line 7656 of file stm32f407xx.h.
| #define USB_OTG_DIEPINT_EPDISD 0x00000002U |
Endpoint disabled interrupt
Definition at line 7650 of file stm32f407xx.h.
| #define USB_OTG_DIEPINT_INEPNE 0x00000040U |
IN endpoint NAK effective
Definition at line 7653 of file stm32f407xx.h.
| #define USB_OTG_DIEPINT_ITTXFE 0x00000010U |
IN token received when TxFIFO is empty
Definition at line 7652 of file stm32f407xx.h.
| #define USB_OTG_DIEPINT_NAK 0x00002000U |
NAK interrupt
Definition at line 7659 of file stm32f407xx.h.
| #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U |
Packet dropped status
Definition at line 7657 of file stm32f407xx.h.
| #define USB_OTG_DIEPINT_TOC 0x00000008U |
Timeout condition
Definition at line 7651 of file stm32f407xx.h.
| #define USB_OTG_DIEPINT_TXFE 0x00000080U |
Transmit FIFO empty
Definition at line 7654 of file stm32f407xx.h.
| #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U |
Transmit Fifo Underrun
Definition at line 7655 of file stm32f407xx.h.
| #define USB_OTG_DIEPINT_XFRC 0x00000001U |
Transfer completed interrupt
Definition at line 7649 of file stm32f407xx.h.
| #define USB_OTG_DIEPMSK_BIM 0x00000200U |
BNA interrupt mask
Definition at line 7242 of file stm32f407xx.h.
| #define USB_OTG_DIEPMSK_EPDM 0x00000002U |
Endpoint disabled interrupt mask
Definition at line 7236 of file stm32f407xx.h.
| #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U |
IN endpoint NAK effective mask
Definition at line 7240 of file stm32f407xx.h.
| #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U |
IN token received with EP mismatch mask
Definition at line 7239 of file stm32f407xx.h.
| #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U |
IN token received when TxFIFO empty mask
Definition at line 7238 of file stm32f407xx.h.
| #define USB_OTG_DIEPMSK_TOM 0x00000008U |
Timeout condition mask (nonisochronous endpoints)
Definition at line 7237 of file stm32f407xx.h.
| #define USB_OTG_DIEPMSK_TXFURM 0x00000100U |
FIFO underrun mask
Definition at line 7241 of file stm32f407xx.h.
| #define USB_OTG_DIEPMSK_XFRCM 0x00000001U |
Transfer completed interrupt mask
Definition at line 7235 of file stm32f407xx.h.
| #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U |
Packet count
Definition at line 7678 of file stm32f407xx.h.
| #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U |
Packet count
Definition at line 7677 of file stm32f407xx.h.
| #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU |
Transfer size
Definition at line 7676 of file stm32f407xx.h.
| #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U |
IN endpoint TxFIFO depth
Definition at line 7698 of file stm32f407xx.h.
| #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU |
IN endpoint FIFOx transmit RAM start address
Definition at line 7697 of file stm32f407xx.h.
| #define USB_OTG_DOEPCTL_CNAK 0x04000000U |
Clear NAK
Definition at line 7712 of file stm32f407xx.h.
| #define USB_OTG_DOEPCTL_EPDIS 0x40000000U |
Endpoint disable
Definition at line 7714 of file stm32f407xx.h.
| #define USB_OTG_DOEPCTL_EPENA 0x80000000U |
Endpoint enable
Definition at line 7715 of file stm32f407xx.h.
| #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U |
Endpoint type
Definition at line 7707 of file stm32f407xx.h.
| #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U |
Bit 0
Definition at line 7708 of file stm32f407xx.h.
| #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U |
Bit 1
Definition at line 7709 of file stm32f407xx.h.
| #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ |
Bit 1
Definition at line 7702 of file stm32f407xx.h.
| #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U |
NAK status
Definition at line 7704 of file stm32f407xx.h.
| #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U |
Set DATA0 PID
Definition at line 7705 of file stm32f407xx.h.
| #define USB_OTG_DOEPCTL_SNAK 0x08000000U |
Set NAK
Definition at line 7713 of file stm32f407xx.h.
| #define USB_OTG_DOEPCTL_SNPM 0x00100000U |
Snoop mode
Definition at line 7710 of file stm32f407xx.h.
| #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U |
Set odd frame
Definition at line 7706 of file stm32f407xx.h.
| #define USB_OTG_DOEPCTL_STALL 0x00200000U |
STALL handshake
Definition at line 7711 of file stm32f407xx.h.
| #define USB_OTG_DOEPCTL_USBAEP 0x00008000U |
USB active endpoint
Definition at line 7703 of file stm32f407xx.h.
| #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U |
Bubble error interrupt mask
Definition at line 7547 of file stm32f407xx.h.
| #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U |
BNA interrupt mask
Definition at line 7546 of file stm32f407xx.h.
| #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U |
Endpoint disabled interrupt mask
Definition at line 7540 of file stm32f407xx.h.
| #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U |
IN endpoint NAK effective mask
Definition at line 7544 of file stm32f407xx.h.
| #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U |
IN token received with EP mismatch mask
Definition at line 7543 of file stm32f407xx.h.
| #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U |
IN token received when TxFIFO empty mask
Definition at line 7542 of file stm32f407xx.h.
| #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U |
NAK interrupt mask
Definition at line 7548 of file stm32f407xx.h.
| #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U |
NYET interrupt mask
Definition at line 7549 of file stm32f407xx.h.
| #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U |
Timeout condition mask
Definition at line 7541 of file stm32f407xx.h.
| #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U |
OUT packet error mask
Definition at line 7545 of file stm32f407xx.h.
| #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U |
Transfer completed interrupt mask
Definition at line 7539 of file stm32f407xx.h.
| #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U |
Back-to-back SETUP packets received
Definition at line 7722 of file stm32f407xx.h.
| #define USB_OTG_DOEPINT_EPDISD 0x00000002U |
Endpoint disabled interrupt
Definition at line 7719 of file stm32f407xx.h.
| #define USB_OTG_DOEPINT_NYET 0x00004000U |
NYET interrupt
Definition at line 7723 of file stm32f407xx.h.
| #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U |
OUT token received when endpoint disabled
Definition at line 7721 of file stm32f407xx.h.
| #define USB_OTG_DOEPINT_STUP 0x00000008U |
SETUP phase done
Definition at line 7720 of file stm32f407xx.h.
| #define USB_OTG_DOEPINT_XFRC 0x00000001U |
Transfer completed interrupt
Definition at line 7718 of file stm32f407xx.h.
| #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U |
Back-to-back SETUP packets received mask
Definition at line 7275 of file stm32f407xx.h.
| #define USB_OTG_DOEPMSK_BOIM 0x00000200U |
BNA interrupt mask
Definition at line 7277 of file stm32f407xx.h.
| #define USB_OTG_DOEPMSK_EPDM 0x00000002U |
Endpoint disabled interrupt mask
Definition at line 7272 of file stm32f407xx.h.
| #define USB_OTG_DOEPMSK_OPEM 0x00000100U |
OUT packet error mask
Definition at line 7276 of file stm32f407xx.h.
| #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U |
OUT token received when endpoint disabled mask
Definition at line 7274 of file stm32f407xx.h.
| #define USB_OTG_DOEPMSK_STUPM 0x00000008U |
SETUP phase done mask
Definition at line 7273 of file stm32f407xx.h.
| #define USB_OTG_DOEPMSK_XFRCM 0x00000001U |
Transfer completed interrupt mask
Definition at line 7271 of file stm32f407xx.h.
| #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U |
Packet count
Definition at line 7728 of file stm32f407xx.h.
| #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U |
SETUP packet count
Definition at line 7730 of file stm32f407xx.h.
| #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U |
Bit 0
Definition at line 7731 of file stm32f407xx.h.
| #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U |
Bit 1
Definition at line 7732 of file stm32f407xx.h.
| #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU |
Transfer size
Definition at line 7727 of file stm32f407xx.h.
| #define USB_OTG_DPID 0x00018000U |
Data PID
Definition at line 7392 of file stm32f407xx.h.
| #define USB_OTG_DPID 0x00018000U |
Data PID
Definition at line 7392 of file stm32f407xx.h.
| #define USB_OTG_DPID_0 0x00008000U |
Bit 0
Definition at line 7393 of file stm32f407xx.h.
| #define USB_OTG_DPID_0 0x00008000U |
Bit 0
Definition at line 7393 of file stm32f407xx.h.
| #define USB_OTG_DPID_1 0x00010000U |
Bit 1
Definition at line 7394 of file stm32f407xx.h.
| #define USB_OTG_DPID_1 0x00010000U |
Bit 1
Definition at line 7394 of file stm32f407xx.h.
| #define USB_OTG_DSTS_EERR 0x00000008U |
Erratic error
Definition at line 7174 of file stm32f407xx.h.
| #define USB_OTG_DSTS_ENUMSPD 0x00000006U |
Enumerated speed
Definition at line 7171 of file stm32f407xx.h.
| #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U |
Bit 0
Definition at line 7172 of file stm32f407xx.h.
| #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U |
Bit 1
Definition at line 7173 of file stm32f407xx.h.
| #define USB_OTG_DSTS_FNSOF 0x003FFF00U |
Frame number of the received SOF
Definition at line 7175 of file stm32f407xx.h.
| #define USB_OTG_DSTS_SUSPSTS 0x00000001U |
Suspend status
Definition at line 7169 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_ARPEN 0x08000000U |
Arbiter parking enable
Definition at line 7477 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U |
ISO IN endpoint threshold enable
Definition at line 7453 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U |
Nonisochronous IN endpoints threshold enable
Definition at line 7452 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U |
Receive threshold enable
Definition at line 7465 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U |
Receive threshold length
Definition at line 7467 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U |
Bit 0
Definition at line 7468 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U |
Bit 1
Definition at line 7469 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U |
Bit 2
Definition at line 7470 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U |
Bit 3
Definition at line 7471 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U |
Bit 4
Definition at line 7472 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U |
Bit 5
Definition at line 7473 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U |
Bit 6
Definition at line 7474 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U |
Bit 7
Definition at line 7475 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U |
Bit 8
Definition at line 7476 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU |
Transmit threshold length
Definition at line 7455 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U |
Bit 0
Definition at line 7456 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U |
Bit 1
Definition at line 7457 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U |
Bit 2
Definition at line 7458 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U |
Bit 3
Definition at line 7459 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U |
Bit 4
Definition at line 7460 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U |
Bit 5
Definition at line 7461 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U |
Bit 6
Definition at line 7462 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U |
Bit 7
Definition at line 7463 of file stm32f407xx.h.
| #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U |
Bit 8
Definition at line 7464 of file stm32f407xx.h.
| #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU |
IN endpoint TxFIFO space avail
Definition at line 7694 of file stm32f407xx.h.
| #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU |
Device VBUS discharge time
Definition at line 7418 of file stm32f407xx.h.
| #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU |
Device VBUS pulsing time
Definition at line 7427 of file stm32f407xx.h.
| #define USB_OTG_EPNUM 0x0000000FU |
Endpoint number
Definition at line 7402 of file stm32f407xx.h.
| #define USB_OTG_EPNUM 0x0000000FU |
Endpoint number
Definition at line 7402 of file stm32f407xx.h.
| #define USB_OTG_EPNUM_0 0x00000001U |
Bit 0
Definition at line 7403 of file stm32f407xx.h.
| #define USB_OTG_EPNUM_0 0x00000001U |
Bit 0
Definition at line 7403 of file stm32f407xx.h.
| #define USB_OTG_EPNUM_1 0x00000002U |
Bit 1
Definition at line 7404 of file stm32f407xx.h.
| #define USB_OTG_EPNUM_1 0x00000002U |
Bit 1
Definition at line 7404 of file stm32f407xx.h.
| #define USB_OTG_EPNUM_2 0x00000004U |
Bit 2
Definition at line 7405 of file stm32f407xx.h.
| #define USB_OTG_EPNUM_2 0x00000004U |
Bit 2
Definition at line 7405 of file stm32f407xx.h.
| #define USB_OTG_EPNUM_3 0x00000008U |
Bit 3
Definition at line 7406 of file stm32f407xx.h.
| #define USB_OTG_EPNUM_3 0x00000008U |
Bit 3
Definition at line 7406 of file stm32f407xx.h.
| #define USB_OTG_FRMNUM 0x01E00000U |
Frame number
Definition at line 7408 of file stm32f407xx.h.
| #define USB_OTG_FRMNUM 0x01E00000U |
Frame number
Definition at line 7408 of file stm32f407xx.h.
| #define USB_OTG_FRMNUM_0 0x00200000U |
Bit 0
Definition at line 7409 of file stm32f407xx.h.
| #define USB_OTG_FRMNUM_0 0x00200000U |
Bit 0
Definition at line 7409 of file stm32f407xx.h.
| #define USB_OTG_FRMNUM_1 0x00400000U |
Bit 1
Definition at line 7410 of file stm32f407xx.h.
| #define USB_OTG_FRMNUM_1 0x00400000U |
Bit 1
Definition at line 7410 of file stm32f407xx.h.
| #define USB_OTG_FRMNUM_2 0x00800000U |
Bit 2
Definition at line 7411 of file stm32f407xx.h.
| #define USB_OTG_FRMNUM_2 0x00800000U |
Bit 2
Definition at line 7411 of file stm32f407xx.h.
| #define USB_OTG_FRMNUM_3 0x01000000U |
Bit 3
Definition at line 7412 of file stm32f407xx.h.
| #define USB_OTG_FRMNUM_3 0x01000000U |
Bit 3
Definition at line 7412 of file stm32f407xx.h.
| #define USB_OTG_GAHBCFG_DMAEN 0x00000020U |
DMA enable
Definition at line 7185 of file stm32f407xx.h.
| #define USB_OTG_GAHBCFG_GINT 0x00000001U |
Global interrupt mask
Definition at line 7178 of file stm32f407xx.h.
| #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU |
Burst length/type
Definition at line 7180 of file stm32f407xx.h.
| #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U |
Bit 0
Definition at line 7181 of file stm32f407xx.h.
| #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U |
Bit 1
Definition at line 7182 of file stm32f407xx.h.
| #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U |
Bit 2
Definition at line 7183 of file stm32f407xx.h.
| #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U |
Bit 3
Definition at line 7184 of file stm32f407xx.h.
| #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U |
Periodic TxFIFO empty level
Definition at line 7187 of file stm32f407xx.h.
| #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U |
TxFIFO empty level
Definition at line 7186 of file stm32f407xx.h.
| #define USB_OTG_GCCFG_I2CPADEN 0x00020000U |
Enable I2C bus connection for the external I2C PHY interface
Definition at line 7488 of file stm32f407xx.h.
| #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U |
VBUS sensing disable option
Definition at line 7492 of file stm32f407xx.h.
| #define USB_OTG_GCCFG_PWRDWN 0x00010000U |
Power down
Definition at line 7487 of file stm32f407xx.h.
| #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U |
SOF output enable
Definition at line 7491 of file stm32f407xx.h.
| #define USB_OTG_GCCFG_VBUSASEN 0x00040000U |
Enable the VBUS sensing device
Definition at line 7489 of file stm32f407xx.h.
| #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U |
Enable the VBUS sensing device
Definition at line 7490 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U |
Connector ID status change mask
Definition at line 7330 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_DISCINT 0x20000000U |
Disconnect detected interrupt mask
Definition at line 7331 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U |
Enumeration done mask
Definition at line 7318 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_EOPFM 0x00008000U |
End of periodic frame interrupt mask
Definition at line 7320 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_EPMISM 0x00020000U |
Endpoint mismatch interrupt mask
Definition at line 7321 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_ESUSPM 0x00000400U |
Early suspend mask
Definition at line 7315 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_FSUSPM 0x00400000U |
Data fetch suspended mask
Definition at line 7326 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U |
Global nonperiodic IN NAK effective mask
Definition at line 7313 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U |
Global OUT NAK effective mask
Definition at line 7314 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_HCIM 0x02000000U |
Host channels interrupt mask
Definition at line 7328 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_IEPINT 0x00040000U |
IN endpoints interrupt mask
Definition at line 7322 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U |
Incomplete isochronous IN transfer mask
Definition at line 7324 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U |
Isochronous OUT packet dropped interrupt mask
Definition at line 7319 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_MMISM 0x00000002U |
Mode mismatch interrupt mask
Definition at line 7308 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U |
Nonperiodic TxFIFO empty mask
Definition at line 7312 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_OEPINT 0x00080000U |
OUT endpoints interrupt mask
Definition at line 7323 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_OTGINT 0x00000004U |
OTG interrupt mask
Definition at line 7309 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_PRTIM 0x01000000U |
Host port interrupt mask
Definition at line 7327 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_PTXFEM 0x04000000U |
Periodic TxFIFO empty mask
Definition at line 7329 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U |
Incomplete periodic transfer mask
Definition at line 7325 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U |
Receive FIFO nonempty mask
Definition at line 7311 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_SOFM 0x00000008U |
Start of frame mask
Definition at line 7310 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_SRQIM 0x40000000U |
Session request/new session detected interrupt mask
Definition at line 7332 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_USBRST 0x00001000U |
USB reset mask
Definition at line 7317 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U |
USB suspend mask
Definition at line 7316 of file stm32f407xx.h.
| #define USB_OTG_GINTMSK_WUIM 0x80000000U |
Resume/remote wakeup detected interrupt mask
Definition at line 7333 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U |
Global OUT NAK effective
Definition at line 7287 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U |
Connector ID status change
Definition at line 7302 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_CMOD 0x00000001U |
Current mode of operation
Definition at line 7280 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U |
Data fetch suspended
Definition at line 7298 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_DISCINT 0x20000000U |
Disconnect detected interrupt
Definition at line 7303 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U |
Enumeration done
Definition at line 7291 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_EOPF 0x00008000U |
End of periodic frame interrupt
Definition at line 7293 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_ESUSP 0x00000400U |
Early suspend
Definition at line 7288 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U |
Global IN nonperiodic NAK effective
Definition at line 7286 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_HCINT 0x02000000U |
Host channels interrupt
Definition at line 7300 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_HPRTINT 0x01000000U |
Host port interrupt
Definition at line 7299 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_IEPINT 0x00040000U |
IN endpoint interrupt
Definition at line 7294 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U |
Incomplete isochronous IN transfer
Definition at line 7296 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_ISOODRP 0x00004000U |
Isochronous OUT packet dropped interrupt
Definition at line 7292 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_MMIS 0x00000002U |
Mode mismatch interrupt
Definition at line 7281 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_NPTXFE 0x00000020U |
Nonperiodic TxFIFO empty
Definition at line 7285 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_OEPINT 0x00080000U |
OUT endpoint interrupt
Definition at line 7295 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_OTGINT 0x00000004U |
OTG interrupt
Definition at line 7282 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_PTXFE 0x04000000U |
Periodic TxFIFO empty
Definition at line 7301 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U |
Incomplete periodic transfer
Definition at line 7297 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_RXFLVL 0x00000010U |
RxFIFO nonempty
Definition at line 7284 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_SOF 0x00000008U |
Start of frame
Definition at line 7283 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_SRQINT 0x40000000U |
Session request/new session detected interrupt
Definition at line 7304 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_USBRST 0x00001000U |
USB reset
Definition at line 7290 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_USBSUSP 0x00000800U |
USB suspend
Definition at line 7289 of file stm32f407xx.h.
| #define USB_OTG_GINTSTS_WKUINT 0x80000000U |
Resume/remote wakeup detected interrupt
Definition at line 7305 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U |
Nonperiodic transmit request queue space available
Definition at line 7432 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U |
Bit 0
Definition at line 7433 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U |
Bit 1
Definition at line 7434 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U |
Bit 2
Definition at line 7435 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U |
Bit 3
Definition at line 7436 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U |
Bit 4
Definition at line 7437 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U |
Bit 5
Definition at line 7438 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U |
Bit 6
Definition at line 7439 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U |
Bit 7
Definition at line 7440 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU |
Nonperiodic TxFIFO space available
Definition at line 7430 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U |
Top of the nonperiodic transmit request queue
Definition at line 7442 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U |
Bit 0
Definition at line 7443 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U |
Bit 1
Definition at line 7444 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U |
Bit 2
Definition at line 7445 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U |
Bit 3
Definition at line 7446 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U |
Bit 4
Definition at line 7447 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U |
Bit 5
Definition at line 7448 of file stm32f407xx.h.
| #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U |
Bit 6
Definition at line 7449 of file stm32f407xx.h.
| #define USB_OTG_GOTGCTL_ASVLD 0x00040000U |
A-session valid
Definition at line 7098 of file stm32f407xx.h.
| #define USB_OTG_GOTGCTL_BSVLD 0x00080000U |
B-session valid
Definition at line 7099 of file stm32f407xx.h.
| #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U |
Connector ID status
Definition at line 7096 of file stm32f407xx.h.
| #define USB_OTG_GOTGCTL_DBCT 0x00020000U |
Long/short debounce time
Definition at line 7097 of file stm32f407xx.h.
| #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U |
Device HNP enabled
Definition at line 7095 of file stm32f407xx.h.
| #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U |
Host negotiation success
Definition at line 7092 of file stm32f407xx.h.
| #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U |
HNP request
Definition at line 7093 of file stm32f407xx.h.
| #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U |
Host set HNP enable
Definition at line 7094 of file stm32f407xx.h.
| #define USB_OTG_GOTGCTL_SRQ 0x00000002U |
Session request
Definition at line 7091 of file stm32f407xx.h.
| #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U |
Session request success
Definition at line 7090 of file stm32f407xx.h.
| #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U |
A-device timeout change
Definition at line 7142 of file stm32f407xx.h.
| #define USB_OTG_GOTGINT_DBCDNE 0x00080000U |
Debounce done
Definition at line 7143 of file stm32f407xx.h.
| #define USB_OTG_GOTGINT_HNGDET 0x00020000U |
Host negotiation detected
Definition at line 7141 of file stm32f407xx.h.
| #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U |
Host negotiation success status change
Definition at line 7140 of file stm32f407xx.h.
| #define USB_OTG_GOTGINT_SEDET 0x00000004U |
Session end detected
Definition at line 7138 of file stm32f407xx.h.
| #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U |
Session request success status change
Definition at line 7139 of file stm32f407xx.h.
| #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U |
AHB master idle
Definition at line 7232 of file stm32f407xx.h.
| #define USB_OTG_GRSTCTL_CSRST 0x00000001U |
Core soft reset
Definition at line 7219 of file stm32f407xx.h.
| #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U |
DMA request signal
Definition at line 7231 of file stm32f407xx.h.
| #define USB_OTG_GRSTCTL_FCRST 0x00000004U |
Host frame counter reset
Definition at line 7221 of file stm32f407xx.h.
| #define USB_OTG_GRSTCTL_HSRST 0x00000002U |
HCLK soft reset
Definition at line 7220 of file stm32f407xx.h.
| #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U |
RxFIFO flush
Definition at line 7222 of file stm32f407xx.h.
| #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U |
TxFIFO flush
Definition at line 7223 of file stm32f407xx.h.
| #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U |
TxFIFO number
Definition at line 7225 of file stm32f407xx.h.
| #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U |
Bit 0
Definition at line 7226 of file stm32f407xx.h.
| #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U |
Bit 1
Definition at line 7227 of file stm32f407xx.h.
| #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U |
Bit 2
Definition at line 7228 of file stm32f407xx.h.
| #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U |
Bit 3
Definition at line 7229 of file stm32f407xx.h.
| #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U |
Bit 4
Definition at line 7230 of file stm32f407xx.h.
| #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU |
RxFIFO depth
Definition at line 7415 of file stm32f407xx.h.
| #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U |
OUT EP interrupt mask bits
Definition at line 7344 of file stm32f407xx.h.
| #define USB_OTG_GRXSTSP_DPID 0x00018000U |
OUT EP interrupt mask bits
Definition at line 7345 of file stm32f407xx.h.
| #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU |
IN EP interrupt mask bits
Definition at line 7343 of file stm32f407xx.h.
| #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U |
OUT EP interrupt mask bits
Definition at line 7346 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U |
Corrupt Tx packet
Definition at line 7216 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_FDMOD 0x40000000U |
Forced peripheral mode
Definition at line 7215 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_FHMOD 0x20000000U |
Forced host mode
Definition at line 7214 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U |
HNP-capable
Definition at line 7197 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_PCCI 0x00800000U |
Indicator complement
Definition at line 7211 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U |
PHY Low-power clock select
Definition at line 7204 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U |
USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
Definition at line 7195 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_PTCI 0x01000000U |
Indicator pass through
Definition at line 7212 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U |
SRP-capable
Definition at line 7196 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_TOCAL 0x00000007U |
FS timeout calibration
Definition at line 7191 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U |
Bit 0
Definition at line 7192 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U |
Bit 1
Definition at line 7193 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U |
Bit 2
Definition at line 7194 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_TRDT 0x00003C00U |
USB turnaround time
Definition at line 7199 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U |
Bit 0
Definition at line 7200 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U |
Bit 1
Definition at line 7201 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U |
Bit 2
Definition at line 7202 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U |
Bit 3
Definition at line 7203 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_TSDPS 0x00400000U |
TermSel DLine pulsing selection
Definition at line 7210 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U |
ULPI Auto-resume
Definition at line 7206 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U |
ULPI Clock SuspendM
Definition at line 7207 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U |
ULPI External VBUS Drive
Definition at line 7208 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U |
ULPI external VBUS indicator
Definition at line 7209 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U |
ULPI FS/LS select
Definition at line 7205 of file stm32f407xx.h.
| #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U |
ULPI interface protect disable
Definition at line 7213 of file stm32f407xx.h.
| #define USB_OTG_HAINT_HAINT 0x0000FFFFU |
Channel interrupts
Definition at line 7268 of file stm32f407xx.h.
| #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU |
Channel interrupt mask
Definition at line 7340 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_CHDIS 0x40000000U |
Channel disable
Definition at line 7606 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_CHENA 0x80000000U |
Channel enable
Definition at line 7607 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_DAD 0x1FC00000U |
Device address
Definition at line 7597 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_DAD_0 0x00400000U |
Bit 0
Definition at line 7598 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_DAD_1 0x00800000U |
Bit 1
Definition at line 7599 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_DAD_2 0x01000000U |
Bit 2
Definition at line 7600 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_DAD_3 0x02000000U |
Bit 3
Definition at line 7601 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_DAD_4 0x04000000U |
Bit 4
Definition at line 7602 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_DAD_5 0x08000000U |
Bit 5
Definition at line 7603 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_DAD_6 0x10000000U |
Bit 6
Definition at line 7604 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_EPDIR 0x00008000U |
Endpoint direction
Definition at line 7586 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_EPNUM 0x00007800U |
Endpoint number
Definition at line 7581 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U |
Bit 0
Definition at line 7582 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U |
Bit 1
Definition at line 7583 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U |
Bit 2
Definition at line 7584 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U |
Bit 3
Definition at line 7585 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_EPTYP 0x000C0000U |
Endpoint type
Definition at line 7589 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U |
Bit 0
Definition at line 7590 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U |
Bit 1
Definition at line 7591 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_LSDEV 0x00020000U |
Low-speed device
Definition at line 7587 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_MC 0x00300000U |
Multi Count (MC) / Error Count (EC)
Definition at line 7593 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_MC_0 0x00100000U |
Bit 0
Definition at line 7594 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_MC_1 0x00200000U |
Bit 1
Definition at line 7595 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU |
Maximum packet size
Definition at line 7579 of file stm32f407xx.h.
| #define USB_OTG_HCCHAR_ODDFRM 0x20000000U |
Odd frame
Definition at line 7605 of file stm32f407xx.h.
| #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU |
DMA address
Definition at line 7691 of file stm32f407xx.h.
| #define USB_OTG_HCFG_FSLSPCS 0x00000003U |
FS/LS PHY clock select
Definition at line 7103 of file stm32f407xx.h.
| #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U |
Bit 0
Definition at line 7104 of file stm32f407xx.h.
| #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U |
Bit 1
Definition at line 7105 of file stm32f407xx.h.
| #define USB_OTG_HCFG_FSLSS 0x00000004U |
FS- and LS-only support
Definition at line 7106 of file stm32f407xx.h.
| #define USB_OTG_HCINT_ACK 0x00000020U |
ACK response received/transmitted interrupt
Definition at line 7641 of file stm32f407xx.h.
| #define USB_OTG_HCINT_AHBERR 0x00000004U |
AHB error
Definition at line 7638 of file stm32f407xx.h.
| #define USB_OTG_HCINT_BBERR 0x00000100U |
Babble error
Definition at line 7644 of file stm32f407xx.h.
| #define USB_OTG_HCINT_CHH 0x00000002U |
Channel halted
Definition at line 7637 of file stm32f407xx.h.
| #define USB_OTG_HCINT_DTERR 0x00000400U |
Data toggle error
Definition at line 7646 of file stm32f407xx.h.
| #define USB_OTG_HCINT_FRMOR 0x00000200U |
Frame overrun
Definition at line 7645 of file stm32f407xx.h.
| #define USB_OTG_HCINT_NAK 0x00000010U |
NAK response received interrupt
Definition at line 7640 of file stm32f407xx.h.
| #define USB_OTG_HCINT_NYET 0x00000040U |
Response received interrupt
Definition at line 7642 of file stm32f407xx.h.
| #define USB_OTG_HCINT_STALL 0x00000008U |
STALL response received interrupt
Definition at line 7639 of file stm32f407xx.h.
| #define USB_OTG_HCINT_TXERR 0x00000080U |
Transaction error
Definition at line 7643 of file stm32f407xx.h.
| #define USB_OTG_HCINT_XFRC 0x00000001U |
Transfer completed
Definition at line 7636 of file stm32f407xx.h.
| #define USB_OTG_HCINTMSK_ACKM 0x00000020U |
ACK response received/transmitted interrupt mask
Definition at line 7667 of file stm32f407xx.h.
| #define USB_OTG_HCINTMSK_AHBERR 0x00000004U |
AHB error
Definition at line 7664 of file stm32f407xx.h.
| #define USB_OTG_HCINTMSK_BBERRM 0x00000100U |
Babble error mask
Definition at line 7670 of file stm32f407xx.h.
| #define USB_OTG_HCINTMSK_CHHM 0x00000002U |
Channel halted mask
Definition at line 7663 of file stm32f407xx.h.
| #define USB_OTG_HCINTMSK_DTERRM 0x00000400U |
Data toggle error mask
Definition at line 7672 of file stm32f407xx.h.
| #define USB_OTG_HCINTMSK_FRMORM 0x00000200U |
Frame overrun mask
Definition at line 7671 of file stm32f407xx.h.
| #define USB_OTG_HCINTMSK_NAKM 0x00000010U |
NAK response received interrupt mask
Definition at line 7666 of file stm32f407xx.h.
| #define USB_OTG_HCINTMSK_NYET 0x00000040U |
response received interrupt mask
Definition at line 7668 of file stm32f407xx.h.
| #define USB_OTG_HCINTMSK_STALLM 0x00000008U |
STALL response received interrupt mask
Definition at line 7665 of file stm32f407xx.h.
| #define USB_OTG_HCINTMSK_TXERRM 0x00000080U |
Transaction error mask
Definition at line 7669 of file stm32f407xx.h.
| #define USB_OTG_HCINTMSK_XFRCM 0x00000001U |
Transfer completed mask
Definition at line 7662 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U |
Do complete split
Definition at line 7632 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U |
Hub address
Definition at line 7620 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U |
Bit 0
Definition at line 7621 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U |
Bit 1
Definition at line 7622 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U |
Bit 2
Definition at line 7623 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U |
Bit 3
Definition at line 7624 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U |
Bit 4
Definition at line 7625 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U |
Bit 5
Definition at line 7626 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U |
Bit 6
Definition at line 7627 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU |
Port address
Definition at line 7611 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U |
Bit 0
Definition at line 7612 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U |
Bit 1
Definition at line 7613 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U |
Bit 2
Definition at line 7614 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U |
Bit 3
Definition at line 7615 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U |
Bit 4
Definition at line 7616 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U |
Bit 5
Definition at line 7617 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U |
Bit 6
Definition at line 7618 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_SPLITEN 0x80000000U |
Split enable
Definition at line 7633 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U |
XACTPOS
Definition at line 7629 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U |
Bit 0
Definition at line 7630 of file stm32f407xx.h.
| #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U |
Bit 1
Definition at line 7631 of file stm32f407xx.h.
| #define USB_OTG_HCTSIZ_DOPING 0x80000000U |
Do PING
Definition at line 7682 of file stm32f407xx.h.
| #define USB_OTG_HCTSIZ_DPID 0x60000000U |
Data PID
Definition at line 7683 of file stm32f407xx.h.
| #define USB_OTG_HCTSIZ_DPID_0 0x20000000U |
Bit 0
Definition at line 7684 of file stm32f407xx.h.
| #define USB_OTG_HCTSIZ_DPID_1 0x40000000U |
Bit 1
Definition at line 7685 of file stm32f407xx.h.
| #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U |
Packet count
Definition at line 7681 of file stm32f407xx.h.
| #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU |
Transfer size
Definition at line 7680 of file stm32f407xx.h.
| #define USB_OTG_HFIR_FRIVL 0x0000FFFFU |
Frame interval
Definition at line 7162 of file stm32f407xx.h.
| #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU |
Frame number
Definition at line 7165 of file stm32f407xx.h.
| #define USB_OTG_HFNUM_FTREM 0xFFFF0000U |
Frame time remaining
Definition at line 7166 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PCDET 0x00000002U |
Port connect detected
Definition at line 7514 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PCSTS 0x00000001U |
Port connect status
Definition at line 7513 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PENA 0x00000004U |
Port enable
Definition at line 7515 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PENCHNG 0x00000008U |
Port enable/disable change
Definition at line 7516 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PLSTS 0x00000C00U |
Port line status
Definition at line 7523 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PLSTS_0 0x00000400U |
Bit 0
Definition at line 7524 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PLSTS_1 0x00000800U |
Bit 1
Definition at line 7525 of file stm32f407xx.h.
| #define USB_OTG_HPRT_POCA 0x00000010U |
Port overcurrent active
Definition at line 7517 of file stm32f407xx.h.
| #define USB_OTG_HPRT_POCCHNG 0x00000020U |
Port overcurrent change
Definition at line 7518 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PPWR 0x00001000U |
Port power
Definition at line 7526 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PRES 0x00000040U |
Port resume
Definition at line 7519 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PRST 0x00000100U |
Port reset
Definition at line 7521 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PSPD 0x00060000U |
Port speed
Definition at line 7534 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PSPD_0 0x00020000U |
Bit 0
Definition at line 7535 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PSPD_1 0x00040000U |
Bit 1
Definition at line 7536 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PSUSP 0x00000080U |
Port suspend
Definition at line 7520 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PTCTL 0x0001E000U |
Port test control
Definition at line 7528 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PTCTL_0 0x00002000U |
Bit 0
Definition at line 7529 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PTCTL_1 0x00004000U |
Bit 1
Definition at line 7530 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PTCTL_2 0x00008000U |
Bit 2
Definition at line 7531 of file stm32f407xx.h.
| #define USB_OTG_HPRT_PTCTL_3 0x00010000U |
Bit 3
Definition at line 7532 of file stm32f407xx.h.
| #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U |
Host periodic TxFIFO depth
Definition at line 7553 of file stm32f407xx.h.
| #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU |
Host periodic TxFIFO start address
Definition at line 7552 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU |
Periodic transmit data FIFO space available
Definition at line 7245 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U |
Periodic transmit request queue space available
Definition at line 7247 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U |
Bit 0
Definition at line 7248 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U |
Bit 1
Definition at line 7249 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U |
Bit 2
Definition at line 7250 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U |
Bit 3
Definition at line 7251 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U |
Bit 4
Definition at line 7252 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U |
Bit 5
Definition at line 7253 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U |
Bit 6
Definition at line 7254 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U |
Bit 7
Definition at line 7255 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U |
Top of the periodic transmit request queue
Definition at line 7257 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U |
Bit 0
Definition at line 7258 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U |
Bit 1
Definition at line 7259 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U |
Bit 2
Definition at line 7260 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U |
Bit 3
Definition at line 7261 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U |
Bit 4
Definition at line 7262 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U |
Bit 5
Definition at line 7263 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U |
Bit 6
Definition at line 7264 of file stm32f407xx.h.
| #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U |
Bit 7
Definition at line 7265 of file stm32f407xx.h.
| #define USB_OTG_NPTXFD 0xFFFF0000U |
Nonperiodic TxFIFO depth
Definition at line 7422 of file stm32f407xx.h.
| #define USB_OTG_NPTXFSA 0x0000FFFFU |
Nonperiodic transmit RAM start address
Definition at line 7421 of file stm32f407xx.h.
| #define USB_OTG_PCGCCTL_GATECLK 0x00000002U |
Bit 0
Definition at line 7736 of file stm32f407xx.h.
| #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U |
Bit 1
Definition at line 7737 of file stm32f407xx.h.
| #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U |
SETUP packet count
Definition at line 7735 of file stm32f407xx.h.
| #define USB_OTG_PCGCR_GATEHCLK 0x00000002U |
Gate HCLK
Definition at line 7134 of file stm32f407xx.h.
| #define USB_OTG_PCGCR_PHYSUSP 0x00000010U |
PHY suspended
Definition at line 7135 of file stm32f407xx.h.
| #define USB_OTG_PCGCR_STPPCLK 0x00000001U |
Stop PHY clock
Definition at line 7133 of file stm32f407xx.h.
| #define USB_OTG_PKTSTS 0x001E0000U |
Packet status
Definition at line 7396 of file stm32f407xx.h.
| #define USB_OTG_PKTSTS 0x001E0000U |
Packet status
Definition at line 7396 of file stm32f407xx.h.
| #define USB_OTG_PKTSTS_0 0x00020000U |
Bit 0
Definition at line 7397 of file stm32f407xx.h.
| #define USB_OTG_PKTSTS_0 0x00020000U |
Bit 0
Definition at line 7397 of file stm32f407xx.h.
| #define USB_OTG_PKTSTS_1 0x00040000U |
Bit 1
Definition at line 7398 of file stm32f407xx.h.
| #define USB_OTG_PKTSTS_1 0x00040000U |
Bit 1
Definition at line 7398 of file stm32f407xx.h.
| #define USB_OTG_PKTSTS_2 0x00080000U |
Bit 2
Definition at line 7399 of file stm32f407xx.h.
| #define USB_OTG_PKTSTS_2 0x00080000U |
Bit 2
Definition at line 7399 of file stm32f407xx.h.
| #define USB_OTG_PKTSTS_3 0x00100000U |
Bit 3
Definition at line 7400 of file stm32f407xx.h.
| #define USB_OTG_PKTSTS_3 0x00100000U |
Bit 3
Definition at line 7400 of file stm32f407xx.h.
| #define USB_OTG_TX0FD 0xFFFF0000U |
Endpoint 0 TxFIFO depth
Definition at line 7424 of file stm32f407xx.h.
| #define USB_OTG_TX0FSA 0x0000FFFFU |
Endpoint 0 transmit RAM start address
Definition at line 7423 of file stm32f407xx.h.
| #define WWDG_CFR_EWI 0x0200U |
Early Wakeup Interrupt
Definition at line 6599 of file stm32f407xx.h.
| #define WWDG_CFR_W 0x007FU |
W[6:0] bits (7-bit window value)
Definition at line 6575 of file stm32f407xx.h.
| #define WWDG_CFR_W0 WWDG_CFR_W_0 |
Definition at line 6584 of file stm32f407xx.h.
| #define WWDG_CFR_W1 WWDG_CFR_W_1 |
Definition at line 6585 of file stm32f407xx.h.
| #define WWDG_CFR_W2 WWDG_CFR_W_2 |
Definition at line 6586 of file stm32f407xx.h.
| #define WWDG_CFR_W3 WWDG_CFR_W_3 |
Definition at line 6587 of file stm32f407xx.h.
| #define WWDG_CFR_W4 WWDG_CFR_W_4 |
Definition at line 6588 of file stm32f407xx.h.
| #define WWDG_CFR_W5 WWDG_CFR_W_5 |
Definition at line 6589 of file stm32f407xx.h.
| #define WWDG_CFR_W6 WWDG_CFR_W_6 |
Definition at line 6590 of file stm32f407xx.h.
| #define WWDG_CFR_W_0 0x0001U |
Bit 0
Definition at line 6576 of file stm32f407xx.h.
| #define WWDG_CFR_W_1 0x0002U |
Bit 1
Definition at line 6577 of file stm32f407xx.h.
| #define WWDG_CFR_W_2 0x0004U |
Bit 2
Definition at line 6578 of file stm32f407xx.h.
| #define WWDG_CFR_W_3 0x0008U |
Bit 3
Definition at line 6579 of file stm32f407xx.h.
| #define WWDG_CFR_W_4 0x0010U |
Bit 4
Definition at line 6580 of file stm32f407xx.h.
| #define WWDG_CFR_W_5 0x0020U |
Bit 5
Definition at line 6581 of file stm32f407xx.h.
| #define WWDG_CFR_W_6 0x0040U |
Bit 6
Definition at line 6582 of file stm32f407xx.h.
| #define WWDG_CFR_WDGTB 0x0180U |
WDGTB[1:0] bits (Timer Base)
Definition at line 6592 of file stm32f407xx.h.
| #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 |
Definition at line 6596 of file stm32f407xx.h.
| #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 |
Definition at line 6597 of file stm32f407xx.h.
| #define WWDG_CFR_WDGTB_0 0x0080U |
Bit 0
Definition at line 6593 of file stm32f407xx.h.
| #define WWDG_CFR_WDGTB_1 0x0100U |
Bit 1
Definition at line 6594 of file stm32f407xx.h.
| #define WWDG_CR_T 0x7FU |
T[6:0] bits (7-Bit counter (MSB to LSB))
Definition at line 6555 of file stm32f407xx.h.
| #define WWDG_CR_T0 WWDG_CR_T_0 |
Definition at line 6564 of file stm32f407xx.h.
| #define WWDG_CR_T1 WWDG_CR_T_1 |
Definition at line 6565 of file stm32f407xx.h.
| #define WWDG_CR_T2 WWDG_CR_T_2 |
Definition at line 6566 of file stm32f407xx.h.
| #define WWDG_CR_T3 WWDG_CR_T_3 |
Definition at line 6567 of file stm32f407xx.h.
| #define WWDG_CR_T4 WWDG_CR_T_4 |
Definition at line 6568 of file stm32f407xx.h.
| #define WWDG_CR_T5 WWDG_CR_T_5 |
Definition at line 6569 of file stm32f407xx.h.
| #define WWDG_CR_T6 WWDG_CR_T_6 |
Definition at line 6570 of file stm32f407xx.h.
| #define WWDG_CR_T_0 0x01U |
Bit 0
Definition at line 6556 of file stm32f407xx.h.
| #define WWDG_CR_T_1 0x02U |
Bit 1
Definition at line 6557 of file stm32f407xx.h.
| #define WWDG_CR_T_2 0x04U |
Bit 2
Definition at line 6558 of file stm32f407xx.h.
| #define WWDG_CR_T_3 0x08U |
Bit 3
Definition at line 6559 of file stm32f407xx.h.
| #define WWDG_CR_T_4 0x10U |
Bit 4
Definition at line 6560 of file stm32f407xx.h.
| #define WWDG_CR_T_5 0x20U |
Bit 5
Definition at line 6561 of file stm32f407xx.h.
| #define WWDG_CR_T_6 0x40U |
Bit 6
Definition at line 6562 of file stm32f407xx.h.
| #define WWDG_CR_WDGA 0x80U |
Activation bit
Definition at line 6572 of file stm32f407xx.h.
| #define WWDG_SR_EWIF 0x01U |
Early Wakeup Interrupt Flag
Definition at line 6602 of file stm32f407xx.h.